********************************************************************************************************
Detailed Description:
On WDOG timeout, the WDOG module requests reset in the Reset Control Module (RCM).
The reset request to RCM can be delayed by 128 bus clock cycles if the WDOG interrupt is enabled (WDOG_CS[INT] = 1).
If enabled, the WDOG interrupt vector is fetched or it becomes pending in NVIC.
After the delay, the reset is requested in RCM.
Independently of the WDOG interrupt, the RCM can again delay the reset by up to 514 LPO additional clock cycles
if the corresponding RCM_WDOG interrupt is enabled (RCM_SRIE[GIE, WDOG] = 1).
If so, instead of forcing reset immediately, the module requests the RCM interrupt in NVIC
and forces the reset after the additional delay (RCM_SRIE[DELAY]).
Either way, the reset is forced, it can’t be stopped only delayed.
This example enables the WDOG interrupt in the WDOG_CS register but leaves this interrupt disabled in NVIC.
That means that this interrupt becomes pending in NVIC on the WDOG timeout, it sets the WDOG_CS_FLG,
but the vector doesn’t get fetched.
The RCM interrupt is enabled and it gets asserted in NVIC after the WDOG interrupt delay (2.67us (48MHz BUS CLK)).
The WDOG flag (WDOG_CS_FLG) is read in the RCM ISR instead.
The execution stays in an infinite loop for 514 LPO (128kHz) cycles (~ 4ms) until the reset is forced.
-------------------------------------------------------------------------------------------------------------------------
Test HW: S32K144EVB-Q100
MCU: S32K144 0N57U
Debugger: S32DSR1 OpenSDA
Target: internal_FLASH
********************************************************************************************************
