FAQs
English (US) 日本語 | Japanese 中文 | Chinese (Simplified)

[RTD400 MCAL 3] K312 MCU clock system configuration

cancel
Turn on suggestions
Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.
Showing results for 
Show  only  | Search instead for 
Did you mean: 

[RTD400 MCAL 3] K312 MCU clock system configuration

[RTD400 MCAL 3] K312 MCU clock system configuration

【RTD400 MCAL 3】 K312 MCU clock system configuration

1. Abstract

This document is talking about how to configure the clock system in the MCU of the K3 chip MCAL. This topic was always disdainful to talk about when I was doing LLD before, because the clock system of K3 is too simple, with internal fast and slow clock sources, external fast and slow clock sources, a PLL multiplier, and then various core peripherals to share. K3's RM even made a few options to frame the rules. From the perspective of LLD, especially the perspective of S32DS CT configuration, it is even more concise and clear. Here is a CT picture to show it:

kerryzhou_0-1737807670859.png

 

Fig 1

 

kerryzhou_1-1737807677834.png

 

Fig 2

With such a clock system, you can generate code with just a few taps and pokes. However, LLD is too free, and MCAL often encounters problems. Therefore, I decided to spend some time to understand the entire clock system of this MCAL MCU. This article takes K312 as an example to explain. Other K3 series are similar.

2. Clock system theory and configuration

2.1 K312 clock system

From the clock chapter of RM, you can see the whole system block diagram:

 

kerryzhou_2-1737807691162.png

 

Fig 3

This block diagram clearly shows the situation of each part. There are four clock sources:

Internal fast clock FIRC: 48MHz, +/-5% error, maximum startup time 25us

Internal slow clock SIRC: 32KHz, +/-10% error, maximum startup time 3ms

External fast clock FXOSC: 8-40MHz, startup stabilization time FXOSC_CTRL[EOCV] × 128

External slow clock SXOSC: 32.768KHz, startup stabilization time SXOSC_CTRL[EOCV] x 128

One PLL: input 8-40MHZ, VOC output 640M-1280Mhz, PLL_PHIn_CLK output 25-480MHz.

MUX_0: Output CORE_CLK, AIPS_PLAT_CLK, AIPS_SLOW_CLK, HSE_CLK, DCM_CLK

MUX_1: Output system timer STM0_CLK

MUX_3: Output FLEXCAN0-2 clock

MUX_4: Output FLEXCAN3-5 clock

MUX_5: Output CLKOUT_STANDBY

MUX_6: Output CLKOUT_RUN

MUX_11: Output TRACE_CLK

RTC_CLK: RTC clock

2.1.1 PLL

From the PLL perspective, we need to know which values ​​the frequency multiplier is related to, which can be calculated using the following formula:

 

kerryzhou_3-1737807699042.png

 

Fig 4

If it is an integer, the red box in the above figure is the common method, and this article will also use the above method to configure.

PLL_PHI is the clock output by the final PLL, which is provided to the MC corresponding to other MUXs for selection.

2.1.2 MUX_0 System

The MUX_0 system with details can be seen from RM:

 

kerryzhou_4-1737807714498.png

 

Fig 5

As you can see, the clock source of MUX_0 can be two types: PLL or internal FIRC.

Then the core clock can be generated later, AIPS_PLAT_CLK, AIPS_SLOW_CLK, HSE_CLK, DCM_CLK.

So what is the specific frequency of the generated clock? In principle, it can meet the maximum clock corresponding to each module, but the K3 series also makes some option recommendations. For example, K312 recommends using option B mode when RUN, especially the HSE clock, which usually needs to strictly meet the option recommendation.

2.1.3 MUX_6 Clock output

In order to check the corresponding clock situation in the chip, the corresponding clock can be output through the CLKOUT pin. The CLKOUT pin can correspond to the selection of multiple clock sources. The specific situation is as follows:

 

kerryzhou_5-1737807720158.png

 

Fig 6

The yellow content in the figure is what K312's CLKOUT_RUN can support. After the clock is configured, the corresponding clock will be selected to test whether the output is consistent with the configuration.

2.1.4 option B Recommended Solution

In this article, K312 will configure the clock of option B in EB.

 

kerryzhou_6-1737807735724.png

 

Fig 7

2.2 EB configuration

       First, create a new K312 EB project. For the specific creation method, please refer to the previous article:

[S32K3 Tools Part] How to port RTD's existing MCAL demo to other K3 chips

This article will focus on the clock configuration corresponding to the MCU module based on RTD400 MCAL. For MCU configuration, two documents need to be consulted as reference books:

C:\NXP\SW32K3_S32M27x_RTD_R21-11_4.0.0\eclipse\plugins\Mcu_TS_T40D34M40I0R0\doc: RTD_MCU_UM.pdf and RTD_MCU_IM.pdf

If you don’t know how to configure, just follow the default values ​​recommended by the document.

The following figure is an overview of the MCU. The main configured modules have the following three components:

General, McuClockSettingConfig, McuModeSettingConf

 

kerryzhou_7-1737807749313.png

 

Fig 8

2.2.1 General configuration

In addition to Figure 8, you need to turn on the internal and external fast and slow clock control and PLL control, and add the corresponding API, as well as the crystal oscillator frequency. If this is not turned on, the corresponding configuration later will not be able to be configured.

 

kerryzhou_8-1737807754646.png

 

Fig 9

2.2.2 McuClockSettingConfig configuration

       This is the core area of ​​MCU clock configuration, which includes clock source, PLL, and various MUX conditions.

First, you need to add a clock configuration:

 

kerryzhou_9-1737807770429.png

 

Fig 10

Click in and there will be detailed configuration:

 

kerryzhou_10-1737807778011.png

 

Fig 11

There are 17 items in total. You can keep the default configuration for options 1 and 6. Since the board does not connect to the external slow crystal oscillator 5, it is not configured. The rest should be configured according to the actual situation. The following explains them one by one:

2.2.2.1 McuFIRC configuration

   Internal fast clock, 48MHz:

 

kerryzhou_11-1737807791866.png

 

Fig 12

2.2.2.2 McuSIRC configuration

Internal slow clock 32Khz

 

kerryzhou_12-1737807801198.png

 

Fig 13

2.2.2.3 McuFXOSC configuration

External crystal oscillator 16MHZ, fill in according to the actual connection situation.

 

kerryzhou_13-1737807813718.png

 

Fig 14

2.2.2.4 McuCgm0ClockMux0 configuration

Mux0 configuration, here are configured core clock, AIPS_PLAT_CLK, AIPS_SLOW_CLK, HSE, DCM_CLK, is to meet the optionB requirements, and the clock comes from PLL_PHI0_CLK. When actually configuring, first configure the PLL clock to output the correct PLL_PHI0_CLK, PLL_PHI1_CLK clock.

 

kerryzhou_14-1737807826426.png

 

Fig 15

2.2.2.5 McuCgm0ClockMux1 configuration

 

kerryzhou_15-1737807916728.png

 

Fig 16

It can be configured according to the clock source required by the actual module.

2.2.2.6 McuCgm0ClockMux3 configuration

Configure the clock source of the FLEXCAN0-2 module:

 

kerryzhou_16-1737807926938.png

 

Fig 17

2.2.2.7 McuCgm0ClockMux4 configuration

Configure the clock source of the FLEXCAN3-5 module:

 

kerryzhou_17-1737807941602.png

 

Fig 18

2.2.2.8 McuCgm0ClockMux5 configuration

Configure the clock source of the CLKOUT_STANBY module:

 

kerryzhou_18-1737807946406.png

 

Fig 19

2.2.2.9 McuCgm0ClockMux6 configuration

Configure the clock source of the CLKOUT_RUN module

 

kerryzhou_19-1737807964974.png

 

Fig 20

2.2.2.10 McuCgm0ClockMux11 configuration

Configure the clock source of the TRACE_CLK module

 

kerryzhou_20-1737807973402.png

 

Fig 21

2.2.2.11 McuRtcClockSelect configuration

Configure the clock source of the RTC module

 

kerryzhou_21-1737807987068.png

 

Fig 22

2.2.2.12 McuPLL configuration

Configure the clock source of the PLL module

 

kerryzhou_22-1737807991862.png

 

Fig 23

2.2.2.13 McuClockReferencePoint configuration

Configure the reference clock and the clock source selection interface of the peripheral modules.

 

kerryzhou_23-1737808007938.png

 

Fig 24

At this point, the clock configuration is complete.

For verification, you can use the CLKOUT_RUN output to output the corresponding clock to pin PTD10 for viewing.

2.2.3 McuModeSettingConf  configuration

In Mcu's McuModeSettingConf->McuPeripheral, you need to turn on the peripherals you want to use:

 

kerryzhou_24-1737808019153.png

 

Fig 25

2.2.4 PORT  configuration

Because the internal clock needs to be output to CLKOUT_RUN, K312's PTD10 MSCR106 is checked, so the PORT pin is added as follows:

 

kerryzhou_25-1737808030584.png

 

Fig 26

3. Test Result

Next, on the S32K312-EVB board, we modify the clock source of EB's CLKOUT_RUN to test whether the clock matches the configuration.

Commonly used MCU-related drivers are as follows:

 

kerryzhou_26-1737808035339.png

 

Fig 27

The calling sequence of system startup MCU initialization is as follows:

1）. Mcu_Init()

2）. Mcu_InitClock()

3）. Mcu_GetPllStatus() - Till PLL is locked.

4）. Mcu_DistributePllClock()

5）. Mcu_SetMode()

6）. Mcu_InitRamSection() - If required

The corresponding main code is as follows:

#include "Mcu.h"
#include "Mcu_Cfg.h"
#include "Port.h"
#include "Dio.h"
#include "Port_Cfg.h"
#include "Platform.h"
void TestDelay(uint32 delay);
void TestDelay(uint32 delay)
{
    static volatile uint32 DelayTimer = 0;
    while(DelayTimer < delay)
    {
        DelayTimer++;
    }
    DelayTimer = 0;
}

/**
* @brief        Main function of the example
* @details      Initialize the used drivers and uses the Icu
*               and Dio drivers to toggle a LED on a push button
*/
int main(void)
{
    uint8 count = 0U;
    uint8 u8TimeOut = 100U;

    /* Initialize the Mcu driver */
#if (MCU_PRECOMPILE_SUPPORT == STD_ON)
    Mcu_Init(NULL_PTR);
#elif (MCU_PRECOMPILE_SUPPORT == STD_OFF)
    Mcu_Init(&Mcu_Config_VS_0);
#endif /* (MCU_PRECOMPILE_SUPPORT == STD_ON) */

    /* Initialize the clock tree and apply PLL as system clock */
    Mcu_InitClock(McuClockSettingConfig_0);

#if (MCU_NO_PLL == STD_OFF)
    while ( MCU_PLL_LOCKED != Mcu_GetPllStatus() )
    {

    }

    Mcu_DistributePllClock();
#endif

    /* Apply a mode configuration */
    Mcu_SetMode(McuModeSettingConf_0);

    /* Initialize all pins using the Port driver */
    Port_Init(NULL_PTR);
    /* Initialize Platform driver */
    Platform_Init(NULL_PTR);

    while (count++ < 10)
    {
        Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_Q172, STD_HIGH);
        Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_Q257, STD_HIGH);
        TestDelay(5000000);
        Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_Q172, STD_LOW);
        Dio_WriteChannel(DioConf_DioChannel_Digital_Output_LED_Q257, STD_LOW);
        TestDelay(5000000);
    }

//    Exit_Example(TRUE);

    return (0U);
}


#ifdef __cplusplus
}
#endif

3.1 CLKOUT FIRC_CLK DIV2

 

kerryzhou_27-1737808056154.png

 

Fig 28

It can be seen that the original 48Mhz clock of FIRC is divided by 2 and the clock waveform of 24Mhz is obtained, which is correct!

3.2 CLKOUT SIRC_CLK DIV2

 

kerryzhou_28-1737808060208.png

 

Fig 29

It can be seen that the original 32Khz clock of SIRC is divided by 2 and the clock waveform of 16khz is obtained, which is correct!

3.3 CLKOUT FXOSC_CLK DIV10

 

kerryzhou_29-1737808075509.png

 

Fig 30

It can be seen that the original 16Mhz clock of FXOSC is divided by 10 and the clock waveform of 1.6Mhz is obtained.

3.4 CLKOUT PLLPH0 CLK DIV10

 

kerryzhou_30-1737808081217.png

 

Fig 31

It can be seen that the original 120Mhz clock of PLLPH0 is divided by 10 and the 12Mhz clock waveform is obtained, which is correct.

3.5 CLKOUT CORE CLK DIV10

 

kerryzhou_31-1737808094772.png

 

Fig 32

It can be seen that the original 120Mhz clock of CORE is divided by 10 and the 12Mhz clock waveform is obtained, which is correct.

3.6 CLKOUT PLLPH1 CLK DIV4

 

kerryzhou_32-1737808099268.png

 

Fig 33

It can be seen that the original 48Mhz clock of PLLPH1 is divided by 4 and the 12Mhz clock waveform is obtained.

3.7 CLKOUT HSE CLK DIV10

 

kerryzhou_33-1737808116460.png

 

Fig 34

It can be seen that the original 60Mhz clock of HSE is divided by 10 and the clock waveform of 6Mhz is obtained, which is correct.

3.8 CLKOUT AIPS_PLAT CLK DIV10

 

kerryzhou_34-1737808124117.png

 

Fig 35

It can be seen that the original 60Mhz clock of AIPS_PLAT_CLK is divided by 10 and the clock waveform of 6Mhz is obtained, which is correct.

3.9 CLKOUT AIPS_SLOW CLK DIV10

 

kerryzhou_35-1737808132759.png

 

Fig 36

It can be seen that the original 30Mhz clock of AIPS_SLOW_CLK is divided by 10 and the clock waveform of 3Mhz is obtained, which is correct.

 

Attachments
Mcal_CAN_S32K312_RTD400.zip
Was this article helpful? Yes No
No ratings
Version history
Last update:
‎01-25-2025 05:38 AM
Updated by:
NXP TechSupport