Basics of Bus Fault in S32DS Program Hi team, I was trying to run a simple complementary program on a S32K358 microcontroller using the S32DS IDE. But i'm facing an error called as bus fault in the program. I have attached the highlighted screenshot of the error message below. I ran the same program in an S32K344 evaluation board and there I didn't face such an error. Please explain me this fault and also the solution to this as I'm new to this IDE's programming. It would be really helpful. S32DS-S32PLATFORM #S32K358 #BusFault  Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  I sent you a private message Re: Basics of Bus Fault in S32DS Program Hi @VaneB  This is the Lpspi_Ip_UpdateTransferMode() function in my code Lpspi_Ip_StatusType Lpspi_Ip_UpdateTransferMode(uint8 Instance, Lpspi_Ip_ModeType Mode) { Lpspi_Ip_StateStructureType* State; Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS; #if (LPSPI_IP_DMA_USED == STD_ON) Dma_Ip_LogicChannelTransferListType DmaTcdList[1u]; #endif #if (LPSPI_IP_DEV_ERROR_DETECT == STD_ON) DevAssert(Instance < LPSPI_INSTANCE_COUNT); #endif State = Lpspi_Ip_apxStateStructureArray[Instance]; #if (LPSPI_IP_DEV_ERROR_DETECT == STD_ON) DevAssert(NULL_PTR != State); #endif /* Transfer mode can be changed when no transfers are in progress. */ if (State->Status != LPSPI_IP_BUSY) { State->TransferMode = Mode; #if (LPSPI_IP_DMA_USED == STD_ON) if (TRUE == State->PhyUnitConfig->DmaUsed) { /* Activate TX DMA and RX DMA interrupt in interrupt mode or disable then in polling mode. */ DmaTcdList[0u].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT; switch (State->TransferMode) { case LPSPI_IP_POLLING: /* Disable DMA major interrupt. */ DmaTcdList[0u].Value = 0u; break; case LPSPI_IP_INTERRUPT: /* Enable DMA major interrupt. */ DmaTcdList[0u].Value = 1u; break; default: /* Nothing to do */ break; } (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 1u); (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, DmaTcdList, 1u); } #endif } else { Status = LPSPI_IP_STATUS_FAIL; } return Status; } The below mentioned are the SPI configurations, SpiDriver   SpiGeneral Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  It seems that your code fails in the Lpspi_Ip_UpdateTransferMode() function. How do you call this function? Also, could you share the SPI configurations? Re: Basics of Bus Fault in S32DS Program Dear @VaneB, Here is the screenshot of the right side of debug window you requested. What could be the problem? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  Could you share a picture of the Debug tab displayed on the left side of the S32DS during debugging? This tab shows where the code failed. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  In a new custom project file, I'm now experiencing this type of bus and hard fault with the message highlighted as shown, , I haven't connected any peripherals or devices to the custom microcontroller. Do you think that the fault is due to the SPI data not being transmitted/received to the controller? Or is it something else? Re: Basics of Bus Fault in S32DS Program Hi @VaneB  You were right about the failure in the Clock_Ip_init() function. The problem was not with the hardware. The problem was in specifying the right clock frequency in the FXOSC section in the clock configuration tool (which makes the Clock_Ip_init() function). My custom hardware was using 40 MHz oscillator and I was running the code in 16 MHz FXOSC in the clock configuration tool of my program. Once I changed that to 40 MHz and uploaded the code again, the busfault error was gone and the code was running.  Thanks for all the help you have given me sir. I deeply appreciate it. Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  From the shared images I deduce that it is a clock problem because the failure occurs in the Clock_Ip_init() function. To verify if this is the case, test the Clock_Ip_Example_S32K358 making the necessary changes to match your HW. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  As per the Hardware Design Guidelines for S32K3xx Microcontrollers the crystal oscillator design of our hardware seems to be correct. What could be other possible hardware/software reason(s) for the BusFault and HardFault errors? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  It seems to be a hardware problem. Since the Hard fault occurs during clock initialization, a possible root cause could be the connections of the EXTAL and XTAL pins, for this you can use as a reference the Hardware Design Guidelines for S32K3xx Microcontrollers. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  I ran the Emios_PWM_Ip example code, that comes with the SDK, on my custom board with the S32K358 controller. I'm still getting the same HardFault error mentioned before. What could be the problem then? Re: Basics of Bus Fault in S32DS Program Hi @VaneB  Yes, you are right. I'm using a custom made board which uses the S32K358. What may the problem then? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  I have flashed your code on my S32K3X8EVB-Q289 and I did not get a bus Fault. Are you using a custom board? Is it necessary to use both Cortex-M7_0_0 (Boot) and Cortex-M7_0_2 files for programming S32K358? No, depends if you want to work with multicore.  Why does the design studio create two files for this processor and only one file for S32K344? Because S32K358 devices have 1 LS core and 1 single core and S32K344 devices have only 1 LS core. So one project is created for each device core. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  I have attached the .zip file of the project that the code is in. I'm using version 4.0.0 of PlatformSDK kit from NXP.  P.S.: Is it necessary to use both Cortex-M7_0_0 (Boot) and Cortex-M7_0_2 files for programming S32K358? Why does the design studio make two files for this processor and only one file for S32K344?? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  BusFault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit). HardFault: is the default exception and can be triggered because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. If there is no handler for a specific fault, it is escalated to HardFault. As the code works with a S32K344, there could be a configuration problem. If it is possible could you share your project or configurations? Also, which RTD version are you using?  BR, VaneB

evkbrt1170 romapi Hi,  I am using evkbrt1170 to test romapi in flash. To get straight to the point, it is no longer working in rom_api_flexspi_nor_get_config(). After searching the community, I found advice to change FLASH_DUMMY_CYCLES and FLASH_DUMMY_VALUE in evkbmimxrt1170_flexspi_nor_config.c to 0x06 and 0x00, respectively. However, it still doesn't work. It worked without any issues when I previously used evkmimxrt1060_fsl_romapi. Why isn't it working on evkbrt1170? Are there any specific conditions for using it in flash? Additionally, I need to test it in flash, not in RAM. Here is the code I am testing. Please review it. Best regards, Re: evkbrt1170 romapi I agree with your opinion. Thank you very much. Best regards, Re: evkbrt1170 romapi Hi @seobi  Make sure to mass erase the flash memory and let me know your results. I am now able to run the demo fsl_romapi demo from SDK v2.16.0 after doing this. Here are more details from our  SDK team:   Please note you need to ensure flash is on default status(You can erase the flash and click reset button to ensure the default status.) This issue is caused by ROM API use default dummy cycles to read data from external flash. If dummy cycles changed by users, ROMAPI don't know the changes.   Thank you for your patience, if you are still having issues  or comments do not hesitate to get back to me. Diego Re: evkbrt1170 romapi Hi @seobi  I still have not received confirmation  from SDK team regarding demo failure, as our team is currently a little bit busy with more  SDK releases. If a minor version update is required  to the SDK, I still do not have a date yet. However, as soon I get any information, I will get back to you.  Are you still getting issues or require further help to get the demo running? If so, please do not hesitate to let me know.  Previously, I was able to get the demo working for SDK v2.15.x, but I still have not tryed previous workarrounds on latest version.  Thank you for your patience.  Diego. Re: evkbrt1170 romapi Thank you for your detailed response. Could you provide information on the schedule for the related SDK? Re: evkbrt1170 romapi Hi @seobi  We did had issues on  SDK v2.15.x to get the fsl_romapi demo working, as seen on the thread you mentioned, they where related to EVK flash configuration (dummy cycles). As far I know release v2.16.0 should have changes implemented already, to make the demo operate properly.  Which SDK release version are you using?   Did you also get issues running the fsl_romapi demo? Let me try on my end this demo too. Edit: today I ran with issues  the fsl_romapi demo from RT1170 EVKB SDK 2.16.0. I am currently checking this issue, I will get back to you as soon as possible with more feedback regarding the demo.  Thank you for reaching out. Diego Re: evkbrt1170 romapi I confirmed that the ROMAPI functions properly after downloading using the MCUXpresso secure provisioning tool. However, it is not functioning properly when using the IDE. Is there a way to make it work with the IDE?

Industrial i.MX8QM clock frequencies Hi everyone, We are currently doing tests on the MIMX8QM5CVUFFAB and found some strange behaviour regarding clocks. The first thing we noted is that even though the clock is limited to 1.3 GHz for the Cortex A72 and 1.104 GHz for the Cortex A53, the cpufreq driver allows us to set the higher frequency of 1.6 GHz and 1.2 GHz. The SCFW seems to correctly ignore the higher frequencies but this leads to a missmatch between cpufreq and the actual clock rate: root@apalis-imx8-15556460:~# cat /sys/bus/cpu/devices/cpu4/cpufreq/scaling_cur_freq 1596000 root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep a72 a72_clk 0 0 0 1296000000 0 0 50000 Y cpu4 no_connection_id root@apalis-imx8-15556460:~# cat /sys/bus/cpu/devices/cpu0/cpufreq/scaling_cur_freq 1200000 root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep a53 a53_clk 0 0 0 1104000000 0 0 50000 Y cpu0 We would expect that this is either solved by a special cpufreq driver or then by a fdt fixup in U-Boot. However, I can't find any of this solutions in the BSP. Can you confirm that this is currently not implemented? A second clocking issue affects the GPU, even though according to the datasheet the GPU should only run at 625 MHz it runs at 800MHz: root@apalis-imx8-15556460:~# cat /sys/kernel/debug/gc/clk gpu0 mc clock: 797983833 HZ. gpu0 sh clock: 996002801 HZ. gpu1 mc clock: 798002539 HZ. gpu1 sh clock: 995989749 HZ. root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep gpu gpu_shader1_clk 0 0 0 996000000 0 0 50000 Y 54100000.gpu shader gpu_core1_clk 0 0 0 798000000 0 0 50000 Y 54100000.gpu core gpu_shader0_clk 0 0 0 996000000 0 0 50000 Y 53100000.gpu shader gpu_core0_clk 0 0 0 798000000 0 0 50000 Y 53100000.gpu Here the SCFW does not limit the clock, which seems to be a violation of what is written in the datasheet. My expectation would also be here that there is a fdt fixup in U-Boot to address this but I could not find it. Can you confirm that this is currently not implemented? The version of the SCFW, ATF and U-Boot should be recent enough to properly support the i.MX8QM with the 1.3 GHz limitation: U-Boot 2024.04-34984-g64f00b21ff8 (Dec 04 2024 - 14:42:45 +0100) CPU: NXP i.MX8QM RevB A53 at 1104 MHz at 33C DRAM: 4 GiB Core: 203 devices, 24 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: Toradex 0091 Apalis iMX8QM 4GB WB IT V1.1A Serial#: 15556460 Boot: MMC0 Reset cause: POR BuildInfo: - SCFW 83624b99, SECO-FW c9de51c0, IMX-MKIMAGE ca5d6b2d, ATF 616a458 - U-Boot 2024.04-34984-g64f00b21ff8 Best regards, Stefan i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Re: Industrial i.MX8QM clock frequencies current bsp is based on nxp mek board, don't find specific bsp for industrial, you can change the bsp by yourself Re: Industrial i.MX8QM clock frequencies Hi @joanxie  Thanks for the update. Can you point me to the right BSP for the industrial version of the i.MX8? Thanks and best regards Stefan Re: Industrial i.MX8QM clock frequencies the bsp you used isn't for industrial, so the A72 core define 1596000000 as max, you can remove this from a72_opp_table: opp-table-1 linux-imx/arch/arm64/boot/dts/freescale/imx8qm.dtsi at lf-6.6.y · nxp-imx/linux-imx · GitHub you also can refer to this workaround, for the 1.3G imx8qm  [OUTDATED] Workaround for de-rating i.MX 8QM/QP parts before SCFW 1.16.0 releases - NXP Community Re: Industrial i.MX8QM clock frequencies Hi @joanxie  The following versions are used: SCFW: 1.17.0 (83624b99) U-Boot: lf_v2022.04 https://github.com/nxp-imx/uboot-imx/tree/lf_v2024.04 Linux: lf-6.6.y https://github.com/nxp-imx/linux-imx/tree/lf-6.6.y Regards, Stefan Re: Industrial i.MX8QM clock frequencies what bsp version and SCFW version do you test? let me double check it

如何将文本置于 spangroup 的中心？ 中心文本似乎是 spangroup 中缺少的一个选项。如何最好地实现这一目标？ 回复：如何将文本置于 spangroup 的中心？ 如果您的建议放在屏幕下方右侧栏的“自定义”代码按钮中，则有效。 如果放在代码中，它会被覆盖。如果放置在事件中，编译就会崩溃。 回复：如何将文本置于 spangroup 的中心？ 如果在 custom.c 中，则崩溃并作为一个事件。 回复：如何将文本置于 spangroup 的中心？ 似乎每次重新编译代码时，这个手动添加的内容都会丢失。有没有一种方法可以减少代码被破坏的可能？ 图形指南 1.8.1-GA

S32K344-Memory configuration after HSE_B firmware usage feature flag is enabled Hello： I found in the section [32.3.1.2 Configuration details when the HSE_B firmware usage feature flag is enabled] in RM that the Reserved area, Application flash memory area, and Application data flash memory area have all been reduced. What data are stored in these areas after the HSE firmware is installed and used? BestRegards, Simon Re: S32K344-Memory configuration after HSE_B firmware usage feature flag is enabled You'll find out when you download HSE_B Firmware Reference Manual. It is a secure file, so following procedure is needed to follow unless you have already done it before: https://www.nxp.com/docs/en/user-guide/nxp-secure-access-rights-registration.pdf For better understanding you may also see following link: https://www.nxp.com/support/support/secure-access-rights:SEC-ACCESS

MC33774无法给出AIN4~AIN7测量结果的正确值 我正在调试MC33774程序并使用应用模式来测量温度和电压。我们有一个 MCAL 包，我调用这个包中的函数。我发现在恩智浦提供的示例代码中，Bcc_774a_MSR_SetMode 函数被调用了两次。为什么这个寄存器要被写入两次？现在出现了一个很奇怪的问题，MC33774 的 AIN4~AIN7 测量结果总是给出无效值。但是 VC 和 AIN0~AIN3 的测量结果正常，它们属于主数字模块。我尝试读取周期模式测量结果寄存器和应用模式测量结果寄存器，但所有数据都无效（0x8000）。我想知道是否有人可以帮助我解决这个问题。 并且我将MC33774工作时记录的SPI数据上传到附件中。 请帮我解决这个问题。 谢谢

S32K3 MCUのフラッシュセクタとブロックロックセクタレジスタのリンクを見つける方法 こんにちは フラッシュセクタを消去したいのですが、消去したいフラッシュセクタのロックセクタビットが何なのかわかりません。MPC574xでは、うーんと、それが非常に明確だったのを覚えています。S32K3のうーんにリンクが見つかりません。 探し方を教えてください。 Re:S32K3 MCUのフラッシュセクタとブロックロックセクタレジスタのリンクを見つける方法 大丈夫です。詳細はアプリケーションノートにも記載されています。ありがとうございます。

Linux i3c-dev userspace driver? There is an article about an i3c-dev driver pacth for i.MX9 SoC in NXP website: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Expose-the-i3c-device-to-the-linux-dev-directory/ta-p/1875290 Where can i download the mentioned "add_i3c_device_to_dev.patch" files? By the way is there any official i3c-dev userpsace driver (which exposed in /dev/i3c-X which is available in Linux mainline? Linux Re: Linux i3c-dev userspace driver? It works only with lf-6.1.55-2.2.0 linux-imx branch/release. When it will be ported and able to use for the newest lf-6.12.3-1.0.0? https://github.com/nxp-imx/linux-imx/tree/lf-6.12.y Re: Linux i3c-dev userspace driver? @pengyong_zhang  Happy New Year! After the long holiday, I haven't received the patch yet. Was it not sent to me? Could you please send it to me? Thank you. Re: Linux i3c-dev userspace driver? @pengyong_zhang  Could you please send me a copy? Thanks a lot.  Re: Linux i3c-dev userspace driver? HI @Livius  I've already sent it to your email, Please check it. B.R Re: Linux i3c-dev userspace driver? @pengyong_zhang  Could you please also send me a copy of the corresponding file via email? Thank you

RW612 SDK - MFlash 文件库 const 不正确 MFlash 文件系统库 (mflash_file.h) 的 API 不是 const-correct，因为mflash_file_t 结构和 mflash_file_save() 和 mflash_file_mmap() 函数中的文件名参数不是声明为“const char *”，而是声明为“char *”。 typedef struct { char *path; uint32_t max_size; } mflash_file_t; status_t mflash_file_save(char *path, uint8_t *data, uint32_t size); status_t mflash_file_mmap(char *path, uint8_t **pdata, uint32_t *psize); 在 C++ 翻译单元中声明 mflash_file_t 结构表时会引发警告： C:\NXP\workspace\[redacted]\config/kvstore_config.h:50:28: warning: ISO C++ forbids converting a string constant to 'char*' [-Wwrite-strings] 50 | #define KVSTORE_FILE_PATH ("/kvstore") | ~^~~~~~~~~~~ ../source/program.cpp:47:15: note: in expansion of macro 'KVSTORE_FILE_PATH' 47 | { .path = KVSTORE_FILE_PATH, .max_size = 3000 }, | ^~~~~~~~~~~~~~~~~ 字符串文字永远不应被视为可写的；在某些情况下，如果由于字符串被声明为可写而将其分配给 RAM 而不是闪存，则可能会导致过多的内存使用。 请修复这些功能的 API。此外，请为这个和其他头文件添加缺少的 extern "C" { } 声明；我必须放置 #include 声明在 extern "C" { } 声明内，以便我的应用程序正确链接。 达娜·M. 回复：RW612 SDK - MFlash 文件库 const 不正确 由于某种原因，我的附件没有显示出来。再试一次。 达娜·M. 回复：RW612 SDK - MFlash 文件库 const 不正确 我正在使用最新的 SDK（v2.16.1），并使用任何包含 MFlash 驱动程序的示例（例如“wifi_mqtt”）。我附上了我的“修复”版本，其中仅涉及用“const char *”替换“char *”的所有实例。 达娜·M.

Flash Read Alignment Issue - Data Reads from 2n Instead of 2n+1 Recently, when using the S32G274 M7 core to read data from flash, I encountered a forced alignment issue. When attempting to read data starting from an address 2n+1, the returned data starts from address 2n. However, reading from address 2n does not have this problem. We are bypassing FEE and directly using the FLS driver to operate the flash. The MCAL version is: SWS32G_RTD_4.4_4.0.2.   Who can help me, thank you. Re: Flash Read Alignment Issue - Data Reads from 2n Instead of 2n+1 Hi @zyz,  great to hear that. Let us know if there is anything we can do to help. Re: Flash Read Alignment Issue - Data Reads from 2n Instead of 2n+1 Hi carlos_o, Thank you for your support. I have already solved the problem on my side. This 2-byte alignment issue is caused by the inherent characteristics of FLASH and is not related to the software. Re: Flash Read Alignment Issue - Data Reads from 2n Instead of 2n+1 Hi @zyz  I recommend try first with the IP functions instead of MCAL, you can see how it works at the Spi_Ip_Transfer example. Let me know if the issue persists.  Re: Flash Read Alignment Issue - Data Reads from 2n Instead of 2n+1 Hello carlos_o, Yes, I am using our custom board with QSPI DDR mode. The flash model is MX25UW51245G.   I discovered this issue when directly using FLS. Re: Flash Read Alignment Issue - Data Reads from 2n Instead of 2n+1 Hi @zyz, Are you using a custom board? if not is it an RDB or EVB?  If you are using a custom board, which model of QSPI are you using?  The problem is when you are doing the bypass of the FEE driver and using directly the FLS? or this is a workaround? 

Routing CAN and Ethernet pins using S32DS pin configurator I'm trying to port the MR-CANHUB code to S32DS 3.6 + RTD 5.0.0 and ran into an issue with the CAN and Ethernet peripherals in the pin configurator.   The tool is telling me: Issue: Incorrect assignment on 'Peripheral', 'Signal' items. Level: Error Type: Tool problem Tool: Pins Origin: Pins:PortContainer_0_BOARD_InitPeripherals Resource: #102-FlexCAN_0.rxd Information: ERRORS:   – The selected peripheral is not supported for routing.   – The FlexCAN_0 peripheral does not support routing. ---   I noticed the FlexCAN example from the RTD disables the pin configurator.   Do these need to be manually configured or are they supported by the pin configurator?     Re: Routing CAN and Ethernet pins using S32DS pin configurator The pin names changed since the MR-CANHUB source was developed in RTD 2.0.0 and S32DS 3.4. I was able to create new pin assignments for these and delete the originals. There are no longer any errors in the configurator.

S32K3 FlexCan in Polling mode Hello,  Im trying to set up the CAN on S32K3, I did not found an example based on polling (not interrupts), using RTD and no Autosar, I did the following config : Pins used are PTA28 – PTA27 (CAN-0) Standard CAN with 500Kb – 8 bytes payload Clock for CAN enabled FlexCan_Send function will execute successfully only once, after that the bus goes into busy state and will not transmit any CAN frame, after adding   FlexCAN_Ip_AbortTransfer seems to work, but im not sure if this was the correct approach ? Flexcan_Ip_StatusType FlexCan_Send(uint16_t Idx, uint8_t *data) { Flexcan_Ip_StatusType retVal = E_NOT_OK; Flexcan_Ip_DataInfoType tx_info = { .msg_id_type = FLEXCAN_MSG_ID_STD, .data_length = 8u, .is_polling = FALSE, /* Specifies if the MB is in polling mode */ .is_remote = FALSE, /* Specifies if the frame is standard or remote */ }; if(FlexCAN_Ip_GetTransferStatus(INST_BOARD_INITPERIPHERALS_FLEXCAN_0, TX_MB_IDX) == FLEXCAN_STATUS_BUSY) { FlexCAN_Ip_AbortTransfer(INST_BOARD_INITPERIPHERALS_FLEXCAN_0, TX_MB_IDX); } retVal = FlexCAN_Ip_Send(INST_BOARD_INITPERIPHERALS_FLEXCAN_0,TX_MB_IDX,&tx_info, Idx, &data[0]); return retVal; } A Task runs each 5ms for reading the CAN frames in polling mode, the FlexCAN_Ip_Receive keep returning Status_Busy __attribute__((__noreturn__)) void Can_Polling_Tsk_5ms( void *pvParameters ) { (void)pvParameters; for( ;; ) { FlexCan_Read(); vTaskDelay(pdMS_TO_TICKS(5)); } } Flexcan_Ip_StatusType FlexCan_Read() { Flexcan_Ip_StatusType retVal = E_NOT_OK; Flexcan_Ip_MsgBuffType recvBuff; retVal = FlexCAN_Ip_Receive(INST_BOARD_INITPERIPHERALS_FLEXCAN_0, RX_MB_IDX, &recvBuff, TRUE); if(retVal == FLEXCAN_STATUS_SUCCESS) { // Process the received frame... } return retVal; } Thank you. Re: S32K3 FlexCan in Polling mode Hi @Kazarian, Sorry for the late reply. You can refer to this community post: S32K1xx-FlexCAN Mask Setting Demo - NXP Community. It does refer to the S32K1xx, but the theory is the same. You must call the functions below in stop or freeze mode. FlexCAN_Ip_SetRxMaskType(); FlexCAN_Ip_SetRxMbGlobalMask(); This community post may also prove helpful: Solved: S32K344 FlexCAN: How to setup Rx MB mask to receive the CAN FD messages with different IDs? - NXP Community. Best regards, Julián  Re: S32K3 FlexCan in Polling mode Hello @Julián_AragónM  Any idea how you can set the RX filter for a range of IDs ? Regards. Re: S32K3 FlexCan in Polling mode Thanks a lot @Julián_AragónM this works,  There is another question on how to enable the reception of all Ids not only the ID configured with the function FlexCAN_Ip_ConfigRxMb : retVal |= FlexCAN_Ip_ConfigRxMb(INST_BOARD_INITPERIPHERALS_FLEXCAN_0, RX_MB_IDX, &rx_info, MSG_ID); is there a function where i can set a kind of mask across a range of Ids i want to receive, say for example from 0x10 to 0x74D. Regards. Re: S32K3 FlexCan in Polling mode Hi @Kazarian, I understand you are creating your own functions implementing the RTD. Even though it is working, the abort mechanism provides a safe way to request the abortion of a pending transmission. A feedback mechanism is provided to inform the CPU whether the transmission was aborted, or the frame could not be aborted and was transmitted instead. There is an existing polling example (although it is based in S32K312) in the following community post: Example S32K312 CAN Transmit & Receive Using Polling mode DS3.5 RTD300 - NXP Community. It implements both write and read in polling mode like this: rx_info.is_polling = TRUE; //Dinesh FlexCAN_Ip_Send(INST_FLEXCAN_0, TX_MB_IDX, &rx_info, MSG_ID, (uint8 *)&dummyData); // Polling while(FlexCAN_Ip_GetTransferStatus(INST_FLEXCAN_0, TX_MB_IDX) != FLEXCAN_STATUS_SUCCESS) { FlexCAN_Ip_MainFunctionWrite(INST_FLEXCAN_0, TX_MB_IDX); } // Polling while(FlexCAN_Ip_GetTransferStatus(INST_FLEXCAN_0, RX_MB_IDX) != FLEXCAN_STATUS_SUCCESS) { FlexCAN_Ip_MainFunctionRead(INST_FLEXCAN_0, RX_MB_IDX); } Nevertheless, if your configuration is working, there should be no problem. Best regards, Julián

Can not find the driver Hello,   I meet a problem as the attached picture, I need some help to solve it, Thanks.  Re: Can not find the driver @Senlent  Thank you, I don't know what happend to my project just after a PC restart or some other system issue yesterday and I have done a reactivate to S32DS v3.4 too, However I tried to create a new empty project and migrate my project and it take effect, the problem resolved. Thank you Re: Can not find the driver Hi@jinT This kind of problem may can be solved by click "update code". If click "update code" can't solve your problem , i will help you to check it if you can provided the project.

Regarding the limitations of Key Scramble settings Hi NXP According to NXP application note, OTFAD_KEY_SCRAMBLE and ALIGN were arbitrary word and byte. But when I set non-SPT default values (0x33AA55CC & 0x1B), the RT10101 fails to decrypt and boot .[On my EVT board] .It stops in ISP mdoe. =================================================================== On the NXP RT1010 EVB, writing the default settings(0x33AA55CC & 0x1B) allows it to boot successfully. The following are the steps on NXP EVB Step 1. Burning fuses[OTFAD KEK & SCRAMBLE] => boot successfully. Step 2. Burning fuses[HAB] => boot successfully. =================================================================== On non-NXP EVB device, writing the non-default settings ,the RT10101 fails to decrypt and boot and stops in ISP mdoe. The following are the steps on my EVT board Step 1. Burning fuses[OTFAD KEK] => boot successfully. Step 2. Burning fuses[HAB] => boot successfully. Step 3. Burning fuses[SCRAMBLE] => boot Fail. I use SPT for programming, and during the programming process, it will verify that the SPT fuses settings match the device. Therefore, my settings should be correctly written to my EVT board. Using the SPT OTP setting function, I also confirmed that my settings were successfully written to the eFuses. I tried changing the OTFAD encryption block to an unwritten block (e.g., 0x60020000), and my EVT board can boot normally. =>This indicates that there might be an issue with the decryption process. =================================================================== Based on the above successful and failed boot cases: 1. Does the order of writing eFuses affect the functionality of OTFAD and Scramble? 2. Are there any configuration limitations for OTFAD_KEY_SCRAMBLE and ALIGN? Does this mean there is an issue with OTFAD and Scramble? Re: Regarding the limitations of Key Scramble settings Hi Stefano, Here is an update for your problem: for i.MX RT116x/7x, the image_enc utility was replaced by nxpimage already in SEC v7. That's why SEC v7 produces same problem in keyblob as SEC v10. For RT117x kindly use SEC v6. You can still use the processor with your custom fuses, only the keyblob needs to be fixed (bootable_images\otfad_keyblobs.bin).  Alternatively, it shall be also possible to generate keyblob in SEC v6 and replace the keyblob generated by SEC v10 (it is possible to add hook into SEC v10 build script). To do this, you must have all keys and all OTFAD parameters same in both workspaces. We are sorry for inconvenience Re: Regarding the limitations of Key Scramble settings Hello Marek, I can confirm that image produced with V7 using a scramble value of 0x19a8c836 and a scramble align of 0xd6 doesn't work - while using the default values the image works. Note however that I used different keys and random counter. I carefully checked fuse settings on the non-working board (the one with the mentioned scramble values) and they look correct. Apparently, image_enc tool is producing a bad key blob. As a side note, I am surprised that issues on such a sensitive topic (image protection) are not being appropriately addressed: how is it possible that, although ages have passed, it is still not possible to reliably get a correctly formed bootable image from SPT? Best regards, Stefano Re: Regarding the limitations of Key Scramble settings Hi Stefano, scramble for RT116x/7x and RT10xx is confirmed bug in MCUXpresso Secure Provisioning tool v10 and currently there is not planned any hotfix. RT117x is supported since MCUXpresso Secure Provisioning tool v5, so we recommend to use older version (v7). There is not known such problem for image_enc tool. For the input image, kindly follow the description in chapter 6.2.1.1 and disable XIP_BOOT_HEADER_ENABLE (images with the header are not supported in tool version 7). We are sorry for inconvenience Re: Regarding the limitations of Key Scramble settings Hello, having same trouble on rt1176 using SEC V10 - can you confirm the problem still exists on V10? Besides, since V7 does not accept binary images with boot header nor ELF files (at least, not those built within MCUXpresso IDE v11.9.0 Build 2144), I'm having hard times with V7 too - and the encrypted image (from blinky sample) does not work anyway. Looks like older image_enc tool suffers the same bug with some scrambling value and/or align. I am quite surprised this issue has not been addressed yet, since it is actually a security flaw - scrambling is definitely useless if you can (safely) use only default values. Kudos Stefano Re: Regarding the limitations of Key Scramble settings Hi Omar, yes, use SEC v7. The problem is in nxpimage utility, which is used to generate keyblob since SEC v8. In the older versions, keyblob was generated using image_enc utility. Re: Regarding the limitations of Key Scramble settings Hi @marek-trmac     I am using SPT V9.0.1.  Do you mean that I need to use version V7.0 to generate the correct keyblob data based on my scramble values ?  Re: Regarding the limitations of Key Scramble settings Hi Omar, we confirm the problem, we found the keyblob is generated wrongly for same scramble values. The problem is reproducible since SEC tool v8. Could you use SEC tool v7? In version 7 the tool uses image_enc utility to generate the keyblob and there is no such issue. We are sorry for the inconvenience. We'll fix the problem for next release. Re: Regarding the limitations of Key Scramble settings Hi @marek-trmac  Thank you for your reply.  what ALIGN fuse value did you burn? =>Since the setting values are intended for future production, it is inconvenient to disclose them. I can only say that I have set them within the range of 0x00 to 0xFF. Does default OTFAD settings works on your custom board? =>Due to concerns about causing the aforementioned situation again, I am currently not burn any scramble config( OTFAD_KEY_SCRAMBLE and ALIGN) to the custom board. Re: Regarding the limitations of Key Scramble settings Hi Omar, what ALIGN fuse value did you burn? Does default OTFAD settings works on your custom board? Re: Regarding the limitations of Key Scramble settings Hi @marek-trmac      Thank you for your reply.     I have used SPT to erase the flash in the above steps, and then used SPT to rewrite the updated KEY blobs and firmware. Re: Regarding the limitations of Key Scramble settings Hi Omar, after you burn SCRAMBLE, you need to update key blobs (because key blobs are affected by the SCRAMBLE). There is application note with details about OTFAD encryption on RT101x, which might help: AN12670 How to use encrypted XIP boot.in i.MX RT1010 About ALIGN, please refer to chapter "Key blob KEK details" in Security Reference Manual.

spi5に関連するハードウェアリセット コミュニティの皆さん、こんにちは。 ボード:S32G399AAAVUC ソフトウェア:bsp40 Mcoreでspi5を使用し、Acoreのデバイスツリーでspi5ノードを無効にすると、奇妙な問題が発生しました。shutdownコマンドを使用し、シャットダウンが完了した後にハードウェアのリセットが発生しました。問題を解決するためにAcoreのデバイスツリーでspi5ノードを削除しましたが、再びは発生しませんでした。特にこのノードはすでに無効になっているため、この問題の原因を知りたいです。なぜ削除する必要があるのですか? S32G3の  Re: spi5に関連するハードウェアのリセット こんにちは、 @chenyin_h あなたの通知をどうもありがとう、私はより高いレベルのデバイスツリーがそのステータスを大丈夫に設定しているのを見つけました。心から感謝します。 BRの ヤン

ADC SC1 への DMA 書き込み 皆さん、こんにちは サンプリングしたいADC入力は>8個あり、FTM PWM INITトリガと同期しています。 これにはPDBを使用しています。しかし、W 以外の S32K を使用しているため、PDB で CH0 と CH1 をバックツーバック リンクすることはできません。 私は、DMA(ADC COCOによってトリガーされる)がADC_SC1nを書き換えて、より多くの入力をパルスごとに「リンク」する解決策が機能することを考えました。しかし、DMAを介してSC1nに書き込むと、PDBがADCを再度トリガーできなくなるようです(最初のチャネルのESがハイになります)。 これを達成する方法について誰かがアドバイスできますか? ありがとうございます ジョーイ

imx93evk 重建内核映像并替换 ！这是我为imx93evk构建的命令 $ mkdir imx-yocto-bsp $cd imx-yocto-bsp $ repo init -u https://github.com/nxp-imx/imx-manifest-b imx-linux-scarthgap -m imx-6.6.36-2.1.0.xml $ repo 同步 $ mkdir -p 下载 $ CD下载 $ mkdir linux-imx；cd linux-imx $ git clone https://github.com/nxp-imx/linux-imx.git $ cd../.. $导出BSPDIR = $（pwd） $ DISTRO=fsl-imx-wayland MACHINE=imx93-11x11-lpddr4x-evk 源 imx-setup-release.sh -b buildwayland $ bitbake imx-图像多媒体 构建完成后，目录 imx-yocto-bsp/buildwayland/tmp/sysroots组件/imx93_11x11_lpddr4x_evk/imx-boot/boot 将包含 imx-boot-imx93-11x11-lpddr4x-evk-sd.bin-flash_单启动 ! 正在使用 $ sudo ./uuu-b emmc_all imx-boot-imx93-11x11-lpddr4x-evk-sd.bin-flash_singleboot ！更新图像以反映我在 linux-imx 中所做的内核更改的正确方法？ ! 推荐的仅构建 Linux 内核并仅替换内核的方法是什么？ 是吗 $ cd linux-imx $制作imx93_11x11_evk_defconfig $ make ！我应该专门刻录哪个映像来替换内核？ BR，科林         回复：imx93evk 重建内核映像并替换 完成重建后，您可以使用scp命令将内核映像复制到您的主板 回复：imx93evk 重建内核映像并替换 是的，您能提供我们可以遵循的步骤吗？ 回复：imx93evk 重建内核映像并替换 这里您是否只需要重建并更新板上的内核？

Calibration features Hello,  I wonder if FreeMaster is capable of being used as a calibration tool. For example, calibrate a thermistor with a NXP board.  Another question on top of this: is it possible to apply a function to a raw signal before it is displayed on a graph in FreeMaster? Thanks  Re: Calibration features Hi @Vast-Horizon, Yes, you can use FreeMASTER as calibration tool. Here's an example of how it could be used in such scenario: Implement the algorithm in the embedded application Store algorithm parameters in global volatile variables Use FreeMASTER to read algorithm parameters at runtime Use FreeMASTER to update parameter values to fine tune the algorithm You can also apply transformation functions on the variables before those are displayed. This option is available in the Variable menu (Project -> Variables -> Edit): Note: transformations are applicable only to REAL values (top right option) Hope it helps, Iulian

About MC33PT2000 software：BASIC-FRDMPKPT2000EVM We used the same PSC assembly code in the file(BASIC-FRDMPKPT2000EVM) with the PT2000 IDE to generate the PT2000_LoadData.c file, but it is different from the file in BASIC-FRDMPKPT2000EVM, as shown in the picture.  user code: Original: The number of arrays is different. One is unsigned short PT2000_code_RAM1[105], another is  unsigned short PT2000_code_RAM1[107]. Is there an error in the document assembly code? Can you provide consistent code? Re: About MC33PT2000 software：BASIC-FRDMPKPT2000EVM Thank you！ I didn't changed anything on  BASIC-FRDMPKPT2000EVM Project. The download address: The Original C code: But,Both methods worked, so the issue is resolved. Thank you very much! Re: About MC33PT2000 software：BASIC-FRDMPKPT2000EVM Hello Hongyu, Where did get your BASIC-FRDMPKPT2000EVM Project? For PSC assembly code, we usually call it microcode. Can you share your SW project here? I think you have changed something on your  BASIC-FRDMPKPT2000EVM Project but you didn't notice. Or you can generate a new BASIC-FRDMPKPT2000EVM Project as below way and try it again And below is the Original RAMx section as your first page. Re: About MC33PT2000 software：BASIC-FRDMPKPT2000EVM Hello Hongyu, I have asked our application engineer who is in charge of the PT2000 to look into it. He is currently OoO, but will be back next week.  Thank you in advance for your patience. BRs, Tomas

Debuggers cannot connect to MIMXRT1062 after core calls NVIC_SystemReset Hi, I'm here to bring back a ghost from the past.  Specifically, this thread. I'm working on the port of Mbed OS CE to MIMXRT1062, and have run into this issue when trying to set up our test suite.  Basically, anytime the code running on the M7 core calls NVIC_SystemReset, debuggers lose the ability to connect to the core. LinkServer prints: Ns: MCUXpresso IDE RedlinkMulti Driver v11.6 (Oct 3 2022 08:09:13 - crt_emu_cm_redlink.exe build 9) Pc: ( 0) Reading remote configuration Wc(03). No cache support. Nc: Found chip XML file in I:/RPL/mbed-os/targets/upload_method_cfg/redlink_cfgs\MIMXRT1052xxxxB.xml Pc: ( 5) Remote configuration complete Nc: Restarted LinkServer process (PID 30668). Wc: ============= SCRIPT: RT1050_connect.scp ============= Wc: RT1050 Connect Script Wc: DpID = 0BD11477 Wc: APID = 0x04770041 Wc: Disabling MPU Wc: Configure FlexRAM for 256KB OC RAM, 128KB I-TCM, 128KB D-TCM Wc: Finished Wc: ============= END SCRIPT ============================= Nc: Probe Firmware: DAPLink CMSIS-DAP (ARM) Nc: Serial Number: 0227000047784e4500559004d7450044ddb1000097969900 Nc: VID:PID: 0D28:0204 Nc: USB Path: \\?\hid#vid_0d28&pid_0204&mi_03#7&316d2a6&0&0000#{4d1e55b2-f16f-11cf-88cb-001111000030} Nc: Using memory from core 0 after searching for a good core Pc: ( 30) Emulator Connected Xr: Pc: ( 40) Debug Halt Nc: connection failed - Ep(03). Invalid ID for processor... Retrying Nc: Using memory from core 0 after searching for a good core Nc: On debug connection - reset using system reset Pc: ( 30) Emulator Connected Pc: ( 40) Debug Halt Ed:02: Failed on connect: Ep(03). Invalid ID for processor. Et: Probe(0): Connected&Reset. Was: NotConnected. DpID: 0BD11477. CpuID: 00000FFF. Info: Nc: Last stub error 0: OK Nc: Last sticky error: 0x0 AIndex: 0 Nc: Debug bus selected: MemAp 0 Nc: DAP Speed test unexecuted or failed Nc: Debug protocol: SWD. RTCK: Disabled. Vector catch: Disabled. Pc: (100) Target Connection Failed PyOCD prints: 0000350 I Target type is mimxrt1060 [board] 0000405 I DP IDR = 0x0bd11477 (v1 MINDP rev0) [dap] 0000433 I AHB-AP#0 IDR = 0x04770041 (AHB-AP var4 rev0) [discovery] 0000446 W Invalid coresight component, cidr=0x0 [rom_table] 0000450 I IMXRT Boot Mode: Boot From Fuses [target_imxrt] 0000458 I CPU core #0: Unknown (CPUID=0x00000000) r0p0, v6.0-M architecture [cortex_m] 0000471 I Loading /home/jamie/Mbed/mbed-os/cmake-build-develop-mimxrt1060evk/hal/tests/TESTS/mbed_hal/rtc_reset/test-mbed-hal-rtc-reset.bin at 0x60000000 [load_cmd] 0000496 I IMXRT Boot Mode: Boot From Fuses [target_imxrt] 0000499 I IMXRT Boot Device: 0 [target_imxrt] 0000545 C cannot write registers r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, psp, msp, lr, pc, xpsr, cfbp because core #0 is not halted [__main__] OpenOCD prints: Info : 114 157 adi_v5_swd.c:370 swd_connect_single(): SWD DPIDR 0x0bd11477 Debug: 115 160 arm_adi_v5.c:679 dap_dp_init(): imxrt.dap Debug: 116 160 arm_adi_v5.c:711 dap_dp_init(): DAP: wait CDBGPWRUPACK Debug: 117 160 arm_adi_v5.h:638 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000 Debug: 118 164 arm_adi_v5.c:719 dap_dp_init(): DAP: wait CSYSPWRUPACK Debug: 119 164 arm_adi_v5.h:638 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000 Debug: 120 166 cmsis_dap.c:808 cmsis_dap_swd_write_from_queue(): refusing to enable sticky overrun detection Debug: 121 169 openocd.c:151 handle_init_command(): Examining targets... Debug: 122 169 target.c:1843 target_call_event_callbacks(): target event 19 (examine-start) for core imxrt.cpu Debug: 123 169 arm_adi_v5.c:1095 dap_get_ap(): refcount AP#0x0 get 1 Debug: 124 173 arm_adi_v5.c:1038 dap_find_get_ap(): Found MEM-AP AHB3 at AP index: 0 (IDR=0x04770041) Debug: 125 181 arm_adi_v5.c:825 mem_ap_init(): MEM_AP Packed Transfers: disabled Debug: 126 181 arm_adi_v5.c:836 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0 Debug: 127 185 target.c:2628 target_read_u32(): address: 0xe000ed00, value: 0x00000000 Error: 128 185 cortex_m.c:2363 cortex_m_examine(): [imxrt.cpu] Cortex-M PARTNO 0x0 is unrecognized Debug: 129 185 target.c:1843 target_call_event_callbacks(): target event 20 (examine-fail) for core imxrt.cpu Basically it seems like, in this situation, the CPU ID reads as 0, so no debugger is able to talk to the core. The original thread (linked above) implied that this error was due to not doing a JEDEC reset of the flash.  However, I dug into the article linked by the thread, and it looks like this is an issue specific to using the flash chip in XIP Enhanced mode. In this mode, normal commands don't work, so when you reset the chip, boot will fail if you do not use a JEDEC reset that gets the chip out of XIP Enhanced (AKA Continuous Read) mode first. However, this situation does not match the configuration that the MIMXRT1060_EVK board is in. I double checked all the flash sequences, and we do not enable XIP Enhanced mode -- in fact, the flash doesn't support it at all. Additionally, the MCU does continue to work after being reset. It just cannot be flashed. This is conclusive proof that this issue is not caused by an inability for the MCU to read its XIP flash. Instead, what I think is going on here is either (a) resetting the MCU somehow disables the ARM JTAG TAP, so the CPU will not talk over the debug port, or (b) resetting the MCU is interfering with some pin mapping used by SWD, so the SWD connection itself dies after the MCU is reset.   Would really appreciate if someone on the NXP side could confirm that this is an issue and explain what's going on here. For now, I did find one workaround, which is to pass "-Oconnect_mode=pre-reset" to pyocd.  This causes it to issue a reset before connecting, which appears to prevent the issue from happening.  Unfortunately, I have not been able to find a similar workaround with LinkServer, which makes it basically unusable for my application.  At minimum, I would really appreciate if you guys could add a "reset before connect" option to LinkServer, or some kind of fallback mode that detects when the MIMXRT CPUID is 0 and tried to reset it. i.MXRT 106x Re: Debuggers cannot connect to MIMXRT1062 after core calls NVIC_SystemReset Hi @MultipleMonomials , As far as I know, it should be at the evaluation stage at the moment. The real implementation will take some time, but if the project is deployed, it should greatly improve everyone's debugging experience in RT MCUs. The debugging experience is not only soft reset, but even the FDCB header of XIP will be improved. Thanks for your understanding! Best regards, Gavin Re: Debuggers cannot connect to MIMXRT1062 after core calls NVIC_SystemReset Thanks for looking at this Gavin. Do you know if any fix/workaround for this is on the LinkServer roadmap anytime soon? (either a fix for the actual issue or a way to make LinkServer do a HW reset before connecting). It makes it all but impossible to use LinkServer for our automated test suite in Mbed OS -- we have to use PyOCD and it's way slower. Re: Debuggers cannot connect to MIMXRT1062 after core calls NVIC_SystemReset Hi @MultipleMonomials , I've double-checked the internals for you over the last few days, and losing the debugger connection after calling NVIC_SystemReset seems to be the expected behavior. "0x202090" is ROMboot entry address. The linkserver debug probe will hold the MCU immediately after NVIC_SystemReset. And I have not found linkserver to have a similar feature as you describe. Sorry for that. Best regards, Gavin Re: Debuggers cannot connect to MIMXRT1062 after core calls NVIC_SystemReset Hi Gavin! I do not believe that this issue is related to Mbed OS at all.  In fact, Mbed OS is built on top of the MCUXpresso SDK, and we use the bootup code and NOR flash configs from the SDK almost unmodified. This issue should be reproducible by adding a call to NVIC_SystemReset() to any existing MCUXpresso project.  (it would probably be a good idea to reset only when a button is pressed to avoid sending the board into a reset loop). Yep, I am using an MIMXRT1060 EVKB board running DAPLink firmware, with LinkServer 24.9.75. Thanks for your help on this, hope this makes sense! Re: Debuggers cannot connect to MIMXRT1062 after core calls NVIC_SystemReset Hi @MultipleMonomials , Thanks for your interest in NXP MIMXRT series! Since the official SDK from NXP does not contain a support project for MEBED OS, it may be necessary for you to provide us with more information. Thanks in advance!  1. Can the phenomenon you mentioned be reproduced using the NXP SDK examples? Or does it only exist in the Mebed project? 2. If the latter, can you provide a reproducible routine? 3. Also, just to confirm with you, the environment you are using is DAP Debugger + LinkServer, right? Best regards, Gavin