S32K344 - LPSPI および DMA 構成 NXPのエキスパートの皆さん、こんにちは! 私はEVKのループバックでSPI通信を開発し始めています。 SPI が Tx と Rx (マスターとスレーブの両方) の DMA で構成された例はありますか。 どうもありがとうございます！ 日時:S32K344 - LPSPIおよびDMAの構成 サポートしてくれてありがとう、 このトピックを終了します。3番目の質問については、送信者と受信者を指定できる半二重モードが答えだと思います。 どうもありがとうございます！ 日時:S32K344 - LPSPIおよびDMAの構成 ハード faul ハンドラは、main.c の 220 行目のタイプミスが原因で発生しました。 Lpspi_Ip_AsyncTransmit(&MASTER_EXTERNAL_DEVICE, TxMasterBuffer, RxMasterBuffer, NUMBER_OF_BYTES, TIMEOUT); コールバックでTIMEOUTを変更しましたが、LSPI間でデータが交換されません。 エラーをありがとう、そして申し訳ありません。 Re: S32K344 - LPSPI and DMA configuration 基本的なLPSPI + DMAのサンプルを提供していただきありがとうございます。S32K344MINI-EVBで6.0.0 RTDを使用するように、あなたのプロジェクトを修正しました。lpspi2の代わりにlpspi1を使用しました。lpspi0はArduinoヘッダーを介してlpspi1に接続されています。また、USBデバッグケーブル経由で経過時間を出力するためにlpuart6を追加しました。

LS1046A L1 および L2 キャッシュ ECC ECC は、LS1046A の L1 キャッシュと L2 キャッシュに対してデフォルトで有効になっていますか? この情報はレジスタL2CTLR_EL1に含まれていることは知っていますが、プログラムでこのレジスタにアクセスできるかどうか疑問に思います よろしくお願いいたします Re:LS1046A L1およびL2キャッシュECC こんにちは@Hector_Villarruel 、 ご返信ありがとうございます。L2CTLR_EL1 レジスタは、LS1046A リファレンス マニュアルに付属の ARM® Cortex-A72® MPCore プロセッサ TRM に示されています。いずれにせよ、ECCが常に有効になっていると述べていれば、そのようなレジスタをチェックする必要はなく、解決策としてあなたの返信を受け入れることができます 敬具

How to modify the SRAM in the LD file when installing HSE FW (AB_SWAP) on S32K311? Hello, I am installing HSE FW (AB_Swap) on S32K311 chip. I understand that 48KB SRAM needs to be reserved for HSE firmware use, but S32K311 chip only has 32KB SRAM. How should I allocate SRAM in the ld file? Re: How to modify the SRAM in the LD file when installing HSE FW (AB_SWAP) on S32K311? It is some comment related to old SBAF version. Installing AB_SWAP also updates SBAF so I would not see any issue. Re: How to modify the SRAM in the LD file when installing HSE FW (AB_SWAP) on S32K311? As described in the following figure, in addition, it can also be seen from the ld file of demo "S32K344-HSE_SW-INSTALL" that 48K SRAM is reserved. Re: How to modify the SRAM in the LD file when installing HSE FW (AB_SWAP) on S32K311? Could you point out where this information came from? I don't think HSE would require any portion of system RAM.

Inquiry of usage eMMC for i.MX8ULP I would like to use eMMC to storage boot image for i.MX8ULP Single Boot Mode. I expect that there is certain empty memory region except eMMC region storing boot image. Could I use certain empty memory region as region to storage data of Application? I would like to use eMMC not only  flash memory for saving data but memory for saving boot image simultaneously. Re: Inquiry of usage eMMC for i.MX8ULP Hi, Salas, I have checked what you said. Thanks, Hyunwoo You Re: Inquiry of usage eMMC for i.MX8ULP Hello @hwyou0212  You can check the Yocto user's guide, there is explained how to build a partitioned image for an i.MX8ULP processor: After flashing your built image you will see two partitions, boot and root.  In root partition will be stored your data applications (Linux OS). I hope this can helps to you. Best regards, --... ...-- Salas. 

SBC fault detection hi, experts Now we are working on SBC FS6513, and MCU is S32K324. and regarding the SBC fault detection, I have following questions: 1)what kind of SBC fault shall we detect in normal case? such as self-test fail, communication error, over voltage, under voltage and so on.. 2)how can we detect above fault(DTC report is required), only read DIAG register is enough? 3)is there any fault which will shut off regulator? in this case, MCU will not work. Re: SBC fault detection Hi Witness, for the fault tests description please refer to the Safety Manual attached.  With Best Regards, Jozef Re: SBC fault detection hi，Jozef Thanks so much for your kind reply. I have one another question, how can we test the SBC fault? is there any safety lib code or any other method we can refer?  Re: SBC fault detection Hi Withness, first please let me inform you, that for the the S32K3xx MCU family the recommended SBCs are newer FS26 and FS23. Please refer to this link. To your questions. 1)what kind of SBC fault shall we detect in normal case? such as self-test fail, communication error, over voltage, under voltage and so on. [A] In Normal operation, please check the RSTB, FS0B pins, depending on the WD_IMPACT_1:0 bits setting. If default, then only the RSTB pin. Then you can periodically check all the DIAG registers for faults. 2)how can we detect above fault(DTC report is required), only read DIAG register is enough? [A] Yes, only the DIAG registers are enough for the FS65.  3)is there any fault which will shut off regulator? in this case, MCU will not work. [A] We have FMEDA (Failure Mode Effects and Diagnostic Analysis) reports describing detailly impacts of the faults. Please download the documents from the FS65 product page, under the Secure section. Please also check the Safety Analysis Report.  High temperature fault will shutdown individual regulators. With Best Regards, Jozef

Questions about the internal SRAM of S32G Hi， I recently tested the bootloader to boot multi-core programs and found that the bootloader will move the complete bin file of each M7 core from QSPI to internal SRAM and then execute it. However, I noticed that the internal SRAM of S32G2 is only 8M, and the space allocated to each M7 core in LD is about 1M. Question: If my M7 core program is very large, such as 10M, how should I operate it? thanks， Re: Questions about the internal SRAM of S32G Hi chenyi,     As we know, if multi-core is enabled, it takes a long time for A-core to boot Linux. During the startup of Core A, if Core M collects 100MB of data that requires saving, how should this be handled?      I'm having this problem right now.S32G QSPI issue - NXP Community Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your reply. In common,  the 8M of SRAM should be bigger enough to run a M7 application, I suggest checking the code to reduce the size. Regarding to XIP, yes, it is theoretically supported,  but there are no example or some documentations about XIP on S32G. It's not easy and not common to implement XIP from NOR flash on S32G,  the S32G didn't have internal nor flash, so the cpu can not directly access the nor flash. you could use a bootloader to initialize the QSPI controller and DDR controller at first and then let cpu to execute the application stored in Qflash or DDR on running time. I hope it will help.  BR Chenyin Re: Questions about the internal SRAM of S32G hi, 已解决: S32G2xx M7 execute code from external flash ? - NXP Community I saw this document introducing an XIP(eXecute-In-Place) mechanism that can execute code from external flash. Do you have any relevant materials or demos? thanks Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for you reply. As per my understanding, there is not formal sample/document regarding to this topic, you may reference the ddr init code from A53 side if willing to initialize the DDR for M7 side. Sorry for your inconvenience. BR Chenyin Re: Questions about the internal SRAM of S32G hi， Do you have any relevant demos or materials within NXP? thanks Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your reply. Yes, I think both method may work for your situation, but as far as I know , most customers do not use DDR from M core side, it is  one option to solve your specific case. BR Chenyin Re: Questions about the internal SRAM of S32G Hi， What do you mean, if the M core wants to execute a large image, there are two options: 1. M7 first transfers a portion of the code to the internal SRAM for initializing DDR. After initializing DDR, the complete code is transferred to DDR for execution; 2. The M7 core waits first, and after the A core initializes the DDR, it moves the M7 core image to the DDR and executes it; Is that so? Re: Questions about the internal SRAM of S32G Hello, @youke  Thank for the reply. If the large size image is indeed caused by code(for example, large libs linked) and cannot be resized via linker file, then it cannot be directly loaded to the SRAM to run.  if so, I think you may have to initialize the DDR for running the code. But, unlike A53 side, the DDR is not by default enabled from sample code/bootloader from M7 side. BR Chenyin Re: Questions about the internal SRAM of S32G hi, Thank you for your reply Because I have written too much code, the compiled file is very large. Based on your answer, S32G2 does not support M7 core images exceeding 8MB because they cannot be copied to internal SRAM for execution. Is that correct? Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your reply. I am not sure why your images are so large, since they have been far larger than the 8M ram size(24 M in total). One possible method is to check the linker file, for example,  edit it to make it to 1-2M size each. Then re-build 3 images, note that do not overlap the address of each other. If the big size of image is because multi-libs linked(large sized libs), then edit the linker file may not work for the case from my understanding. BR Chenyin Re: Questions about the internal SRAM of S32G Hi， We will use three M7 cores to run separate programs here, with each core having an image size of approximately 8M, totaling 24M, Because the internal SRAM of S32G2 is only 8MB, how should I plan the LD file thanks, Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your post. In common, the actual size of the M7 image would not be that so big, if so, I suggest modify the linker file to change the address range of each part, thus resize the image.  BR Chenyin

RW612 SDK - Config Tools creates C prototypes without C++ guards I'm currently writing a C++-based program for the RW612.  I have integrated some of the functions in the original board.c into my own Board object, which has a .CPP source file.  I have properly declared the functions inside my own header file: #ifdef __cplusplus extern "C" { #endif /* Configures static voltage compensation and sensors, and in XIP case, change * FlexSPI clock to a stable source before clock tree (such as PLL and Main * clock) update. */ void BOARD_ClockPreConfig(void); /* Updates FlexSPI clock source and set flash to full speed. */ void BOARD_ClockPostConfig(void); /* Configure FlexSPI clock source and divider when using XIP flash. Must run * in RAM. */ AT_QUICKACCESS_SECTION_CODE(void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint32_t src, uint32_t divider)); /* De-initializes XIP flash. Must run in RAM. */ AT_QUICKACCESS_SECTION_CODE(void BOARD_DeinitFlash(FLEXSPI_Type *base)); /* Initializes XIP flash. Must run in RAM. */ AT_QUICKACCESS_SECTION_CODE(void BOARD_InitFlash(FLEXSPI_Type *base)); #ifdef __cplusplus } // extern "C" #endif However, when I compile, I get an error that both BOARD_ClockPreConfig() and BOARD_ClockPostConfig() have previously been defined with C++ linkage: Errors showing conflicting C/C++ linkageErrors showing conflicting C/C++ linkage I examined clock_config.h to locate the prototypes for those two functions: Function prototypes in clock_config.hFunction prototypes in clock_config.h The problem is that those two prototypes (and the AVPLL config extern declaration) are not placed inside an extern "C" { } declaration.  Several things in clock_config.h do appear within an extern "C" { }, but those items do not, and it throws off the compiler.  This is additionally frustrating because clock_config.h is automatically generated by MCU Config Tools, so I have to either disable re-generation of clock_config.h or manually edit in an extern "C" { } declaration each time I re-generate code. Please fix this defect in MCU Config Tools for the RW612.  Thank you. Dana M. Re: RW612 SDK - Config Tools creates C prototypes without C++ guards Dear @dmarks_ls , Good job! and thanks for you sharing! I will report the issue to internal team. Anyway, fortunately, this did not affect the continuation of your project! In the current situation, you can only proceed according to the method you have adopted. Thanks! Regards, weidong Re: RW612 SDK - Config Tools creates C prototypes without C++ guards No, the compilation issues are resolved because the declarations in the header file are recognized as having C binding in all locations.  I've attached the original header file and my fixed version of the header file.  Please review the Config Tools for RW612 and make sure that any extern declarations, type declarations, and function prototypes are enclosed by an extern "C" { } declaration, thanks. Dana M. Re: RW612 SDK - Config Tools creates C prototypes without C++ guards Dear @dmarks_ls , After   editing in an extern "C" { } in config_clock.h,  Are there any compilation errors in the code? Thanks! Regards, weidong

PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? Hi Team, Originally, I would like to use PCA9509 as voltage translator of 5V<-->3.3V, but when I checked the details, I found VIL of PCA9509 is 0.15V, which is too low for slave 6# in below schematic. Can you kindly recommend an option with higher VIL? For example, 0.8V or higher.  Thank you.    Kind Regards, Boler Re: PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? Hi Guowei, It's great, thanks. Re: PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? HI Boler： You can refer to below: Re: PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? Hi Guowei, Thanks for the quick update. I also notice a similar part PCA9306 as NTS0102 , any difference? Re: PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? Hi Boler If only for  level translating we have lots: NVT2002.NTS0102: Voltage Level Translators (Level Shifters) | NXP Semiconductors NTS0102 | NXP Semiconductors Re: PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? Hi Guowei, I use PCA9509 only for level translating, so I would like to change PCA9509 to a common voltage-level translator, such as TI TCA39306. Can you please advise NXP option in place of TI TCA39306? Thank you. Kind regards, Boler Re: PCA9509: VIL 0.15V is too low for my application, any option with higher VIL? Hi Boler You can consider about PCA9617!

Basics of Bus Fault in S32DS Program Hi team, I was trying to run a simple complementary program on a S32K358 microcontroller using the S32DS IDE. But i'm facing an error called as bus fault in the program. I have attached the highlighted screenshot of the error message below. I ran the same program in an S32K344 evaluation board and there I didn't face such an error. Please explain me this fault and also the solution to this as I'm new to this IDE's programming. It would be really helpful. S32DS-S32PLATFORM #S32K358 #BusFault  Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  I sent you a private message Re: Basics of Bus Fault in S32DS Program Hi @VaneB  This is the Lpspi_Ip_UpdateTransferMode() function in my code Lpspi_Ip_StatusType Lpspi_Ip_UpdateTransferMode(uint8 Instance, Lpspi_Ip_ModeType Mode) { Lpspi_Ip_StateStructureType* State; Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS; #if (LPSPI_IP_DMA_USED == STD_ON) Dma_Ip_LogicChannelTransferListType DmaTcdList[1u]; #endif #if (LPSPI_IP_DEV_ERROR_DETECT == STD_ON) DevAssert(Instance < LPSPI_INSTANCE_COUNT); #endif State = Lpspi_Ip_apxStateStructureArray[Instance]; #if (LPSPI_IP_DEV_ERROR_DETECT == STD_ON) DevAssert(NULL_PTR != State); #endif /* Transfer mode can be changed when no transfers are in progress. */ if (State->Status != LPSPI_IP_BUSY) { State->TransferMode = Mode; #if (LPSPI_IP_DMA_USED == STD_ON) if (TRUE == State->PhyUnitConfig->DmaUsed) { /* Activate TX DMA and RX DMA interrupt in interrupt mode or disable then in polling mode. */ DmaTcdList[0u].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT; switch (State->TransferMode) { case LPSPI_IP_POLLING: /* Disable DMA major interrupt. */ DmaTcdList[0u].Value = 0u; break; case LPSPI_IP_INTERRUPT: /* Enable DMA major interrupt. */ DmaTcdList[0u].Value = 1u; break; default: /* Nothing to do */ break; } (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 1u); (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, DmaTcdList, 1u); } #endif } else { Status = LPSPI_IP_STATUS_FAIL; } return Status; } The below mentioned are the SPI configurations, SpiDriver   SpiGeneral Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  It seems that your code fails in the Lpspi_Ip_UpdateTransferMode() function. How do you call this function? Also, could you share the SPI configurations? Re: Basics of Bus Fault in S32DS Program Dear @VaneB, Here is the screenshot of the right side of debug window you requested. What could be the problem? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  Could you share a picture of the Debug tab displayed on the left side of the S32DS during debugging? This tab shows where the code failed. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  In a new custom project file, I'm now experiencing this type of bus and hard fault with the message highlighted as shown, , I haven't connected any peripherals or devices to the custom microcontroller. Do you think that the fault is due to the SPI data not being transmitted/received to the controller? Or is it something else? Re: Basics of Bus Fault in S32DS Program Hi @VaneB  You were right about the failure in the Clock_Ip_init() function. The problem was not with the hardware. The problem was in specifying the right clock frequency in the FXOSC section in the clock configuration tool (which makes the Clock_Ip_init() function). My custom hardware was using 40 MHz oscillator and I was running the code in 16 MHz FXOSC in the clock configuration tool of my program. Once I changed that to 40 MHz and uploaded the code again, the busfault error was gone and the code was running.  Thanks for all the help you have given me sir. I deeply appreciate it. Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  From the shared images I deduce that it is a clock problem because the failure occurs in the Clock_Ip_init() function. To verify if this is the case, test the Clock_Ip_Example_S32K358 making the necessary changes to match your HW. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  As per the Hardware Design Guidelines for S32K3xx Microcontrollers the crystal oscillator design of our hardware seems to be correct. What could be other possible hardware/software reason(s) for the BusFault and HardFault errors? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  It seems to be a hardware problem. Since the Hard fault occurs during clock initialization, a possible root cause could be the connections of the EXTAL and XTAL pins, for this you can use as a reference the Hardware Design Guidelines for S32K3xx Microcontrollers. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  I ran the Emios_PWM_Ip example code, that comes with the SDK, on my custom board with the S32K358 controller. I'm still getting the same HardFault error mentioned before. What could be the problem then? Re: Basics of Bus Fault in S32DS Program Hi @VaneB  Yes, you are right. I'm using a custom made board which uses the S32K358. What may the problem then? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  I have flashed your code on my S32K3X8EVB-Q289 and I did not get a bus Fault. Are you using a custom board? Is it necessary to use both Cortex-M7_0_0 (Boot) and Cortex-M7_0_2 files for programming S32K358? No, depends if you want to work with multicore.  Why does the design studio create two files for this processor and only one file for S32K344? Because S32K358 devices have 1 LS core and 1 single core and S32K344 devices have only 1 LS core. So one project is created for each device core. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  I have attached the .zip file of the project that the code is in. I'm using version 4.0.0 of PlatformSDK kit from NXP.  P.S.: Is it necessary to use both Cortex-M7_0_0 (Boot) and Cortex-M7_0_2 files for programming S32K358? Why does the design studio make two files for this processor and only one file for S32K344?? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  BusFault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit). HardFault: is the default exception and can be triggered because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. If there is no handler for a specific fault, it is escalated to HardFault. As the code works with a S32K344, there could be a configuration problem. If it is possible could you share your project or configurations? Also, which RTD version are you using?  BR, VaneB

Industrial i.MX8QM clock frequencies Hi everyone, We are currently doing tests on the MIMX8QM5CVUFFAB and found some strange behaviour regarding clocks. The first thing we noted is that even though the clock is limited to 1.3 GHz for the Cortex A72 and 1.104 GHz for the Cortex A53, the cpufreq driver allows us to set the higher frequency of 1.6 GHz and 1.2 GHz. The SCFW seems to correctly ignore the higher frequencies but this leads to a missmatch between cpufreq and the actual clock rate: root@apalis-imx8-15556460:~# cat /sys/bus/cpu/devices/cpu4/cpufreq/scaling_cur_freq 1596000 root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep a72 a72_clk 0 0 0 1296000000 0 0 50000 Y cpu4 no_connection_id root@apalis-imx8-15556460:~# cat /sys/bus/cpu/devices/cpu0/cpufreq/scaling_cur_freq 1200000 root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep a53 a53_clk 0 0 0 1104000000 0 0 50000 Y cpu0 We would expect that this is either solved by a special cpufreq driver or then by a fdt fixup in U-Boot. However, I can't find any of this solutions in the BSP. Can you confirm that this is currently not implemented? A second clocking issue affects the GPU, even though according to the datasheet the GPU should only run at 625 MHz it runs at 800MHz: root@apalis-imx8-15556460:~# cat /sys/kernel/debug/gc/clk gpu0 mc clock: 797983833 HZ. gpu0 sh clock: 996002801 HZ. gpu1 mc clock: 798002539 HZ. gpu1 sh clock: 995989749 HZ. root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep gpu gpu_shader1_clk 0 0 0 996000000 0 0 50000 Y 54100000.gpu shader gpu_core1_clk 0 0 0 798000000 0 0 50000 Y 54100000.gpu core gpu_shader0_clk 0 0 0 996000000 0 0 50000 Y 53100000.gpu shader gpu_core0_clk 0 0 0 798000000 0 0 50000 Y 53100000.gpu Here the SCFW does not limit the clock, which seems to be a violation of what is written in the datasheet. My expectation would also be here that there is a fdt fixup in U-Boot to address this but I could not find it. Can you confirm that this is currently not implemented? The version of the SCFW, ATF and U-Boot should be recent enough to properly support the i.MX8QM with the 1.3 GHz limitation: U-Boot 2024.04-34984-g64f00b21ff8 (Dec 04 2024 - 14:42:45 +0100) CPU: NXP i.MX8QM RevB A53 at 1104 MHz at 33C DRAM: 4 GiB Core: 203 devices, 24 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: Toradex 0091 Apalis iMX8QM 4GB WB IT V1.1A Serial#: 15556460 Boot: MMC0 Reset cause: POR BuildInfo: - SCFW 83624b99, SECO-FW c9de51c0, IMX-MKIMAGE ca5d6b2d, ATF 616a458 - U-Boot 2024.04-34984-g64f00b21ff8 Best regards, Stefan i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Re: Industrial i.MX8QM clock frequencies current bsp is based on nxp mek board, don't find specific bsp for industrial, you can change the bsp by yourself Re: Industrial i.MX8QM clock frequencies Hi @joanxie  Thanks for the update. Can you point me to the right BSP for the industrial version of the i.MX8? Thanks and best regards Stefan Re: Industrial i.MX8QM clock frequencies the bsp you used isn't for industrial, so the A72 core define 1596000000 as max, you can remove this from a72_opp_table: opp-table-1 linux-imx/arch/arm64/boot/dts/freescale/imx8qm.dtsi at lf-6.6.y · nxp-imx/linux-imx · GitHub you also can refer to this workaround, for the 1.3G imx8qm  [OUTDATED] Workaround for de-rating i.MX 8QM/QP parts before SCFW 1.16.0 releases - NXP Community Re: Industrial i.MX8QM clock frequencies Hi @joanxie  The following versions are used: SCFW: 1.17.0 (83624b99) U-Boot: lf_v2022.04 https://github.com/nxp-imx/uboot-imx/tree/lf_v2024.04 Linux: lf-6.6.y https://github.com/nxp-imx/linux-imx/tree/lf-6.6.y Regards, Stefan Re: Industrial i.MX8QM clock frequencies what bsp version and SCFW version do you test? let me double check it

如何将文本置于 spangroup 的中心？ 中心文本似乎是 spangroup 中缺少的一个选项。如何最好地实现这一目标？ 回复：如何将文本置于 spangroup 的中心？ 如果您的建议放在屏幕下方右侧栏的“自定义”代码按钮中，则有效。 如果放在代码中，它会被覆盖。如果放置在事件中，编译就会崩溃。 回复：如何将文本置于 spangroup 的中心？ 如果在 custom.c 中，则崩溃并作为一个事件。 回复：如何将文本置于 spangroup 的中心？ 似乎每次重新编译代码时，这个手动添加的内容都会丢失。有没有一种方法可以减少代码被破坏的可能？ 图形指南 1.8.1-GA

S32K344-Memory configuration after HSE_B firmware usage feature flag is enabled Hello： I found in the section [32.3.1.2 Configuration details when the HSE_B firmware usage feature flag is enabled] in RM that the Reserved area, Application flash memory area, and Application data flash memory area have all been reduced. What data are stored in these areas after the HSE firmware is installed and used? BestRegards, Simon Re: S32K344-Memory configuration after HSE_B firmware usage feature flag is enabled You'll find out when you download HSE_B Firmware Reference Manual. It is a secure file, so following procedure is needed to follow unless you have already done it before: https://www.nxp.com/docs/en/user-guide/nxp-secure-access-rights-registration.pdf For better understanding you may also see following link: https://www.nxp.com/support/support/secure-access-rights:SEC-ACCESS

MC33774无法给出AIN4~AIN7测量结果的正确值 我正在调试MC33774程序并使用应用模式来测量温度和电压。我们有一个 MCAL 包，我调用这个包中的函数。我发现在恩智浦提供的示例代码中，Bcc_774a_MSR_SetMode 函数被调用了两次。为什么这个寄存器要被写入两次？现在出现了一个很奇怪的问题，MC33774 的 AIN4~AIN7 测量结果总是给出无效值。但是 VC 和 AIN0~AIN3 的测量结果正常，它们属于主数字模块。我尝试读取周期模式测量结果寄存器和应用模式测量结果寄存器，但所有数据都无效（0x8000）。我想知道是否有人可以帮助我解决这个问题。 并且我将MC33774工作时记录的SPI数据上传到附件中。 请帮我解决这个问题。 谢谢

S32K3 MCUのフラッシュセクタとブロックロックセクタレジスタのリンクを見つける方法 こんにちは フラッシュセクタを消去したいのですが、消去したいフラッシュセクタのロックセクタビットが何なのかわかりません。MPC574xでは、うーんと、それが非常に明確だったのを覚えています。S32K3のうーんにリンクが見つかりません。 探し方を教えてください。 Re:S32K3 MCUのフラッシュセクタとブロックロックセクタレジスタのリンクを見つける方法 大丈夫です。詳細はアプリケーションノートにも記載されています。ありがとうございます。

Linux i3c-dev userspace driver? There is an article about an i3c-dev driver pacth for i.MX9 SoC in NXP website: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Expose-the-i3c-device-to-the-linux-dev-directory/ta-p/1875290 Where can i download the mentioned "add_i3c_device_to_dev.patch" files? By the way is there any official i3c-dev userpsace driver (which exposed in /dev/i3c-X which is available in Linux mainline? Linux Re: Linux i3c-dev userspace driver? It works only with lf-6.1.55-2.2.0 linux-imx branch/release. When it will be ported and able to use for the newest lf-6.12.3-1.0.0? https://github.com/nxp-imx/linux-imx/tree/lf-6.12.y Re: Linux i3c-dev userspace driver? @pengyong_zhang  Happy New Year! After the long holiday, I haven't received the patch yet. Was it not sent to me? Could you please send it to me? Thank you. Re: Linux i3c-dev userspace driver? @pengyong_zhang  Could you please send me a copy? Thanks a lot.  Re: Linux i3c-dev userspace driver? HI @Livius  I've already sent it to your email, Please check it. B.R Re: Linux i3c-dev userspace driver? @pengyong_zhang  Could you please also send me a copy of the corresponding file via email? Thank you

RW612 SDK - MFlash 文件库 const 不正确 MFlash 文件系统库 (mflash_file.h) 的 API 不是 const-correct，因为mflash_file_t 结构和 mflash_file_save() 和 mflash_file_mmap() 函数中的文件名参数不是声明为“const char *”，而是声明为“char *”。 typedef struct { char *path; uint32_t max_size; } mflash_file_t; status_t mflash_file_save(char *path, uint8_t *data, uint32_t size); status_t mflash_file_mmap(char *path, uint8_t **pdata, uint32_t *psize); 在 C++ 翻译单元中声明 mflash_file_t 结构表时会引发警告： C:\NXP\workspace\[redacted]\config/kvstore_config.h:50:28: warning: ISO C++ forbids converting a string constant to 'char*' [-Wwrite-strings] 50 | #define KVSTORE_FILE_PATH ("/kvstore") | ~^~~~~~~~~~~ ../source/program.cpp:47:15: note: in expansion of macro 'KVSTORE_FILE_PATH' 47 | { .path = KVSTORE_FILE_PATH, .max_size = 3000 }, | ^~~~~~~~~~~~~~~~~ 字符串文字永远不应被视为可写的；在某些情况下，如果由于字符串被声明为可写而将其分配给 RAM 而不是闪存，则可能会导致过多的内存使用。 请修复这些功能的 API。此外，请为这个和其他头文件添加缺少的 extern "C" { } 声明；我必须放置 #include 声明在 extern "C" { } 声明内，以便我的应用程序正确链接。 达娜·M. 回复：RW612 SDK - MFlash 文件库 const 不正确 由于某种原因，我的附件没有显示出来。再试一次。 达娜·M. 回复：RW612 SDK - MFlash 文件库 const 不正确 我正在使用最新的 SDK（v2.16.1），并使用任何包含 MFlash 驱动程序的示例（例如“wifi_mqtt”）。我附上了我的“修复”版本，其中仅涉及用“const char *”替换“char *”的所有实例。 达娜·M.

Routing CAN and Ethernet pins using S32DS pin configurator I'm trying to port the MR-CANHUB code to S32DS 3.6 + RTD 5.0.0 and ran into an issue with the CAN and Ethernet peripherals in the pin configurator.   The tool is telling me: Issue: Incorrect assignment on 'Peripheral', 'Signal' items. Level: Error Type: Tool problem Tool: Pins Origin: Pins:PortContainer_0_BOARD_InitPeripherals Resource: #102-FlexCAN_0.rxd Information: ERRORS:   – The selected peripheral is not supported for routing.   – The FlexCAN_0 peripheral does not support routing. ---   I noticed the FlexCAN example from the RTD disables the pin configurator.   Do these need to be manually configured or are they supported by the pin configurator?     Re: Routing CAN and Ethernet pins using S32DS pin configurator The pin names changed since the MR-CANHUB source was developed in RTD 2.0.0 and S32DS 3.4. I was able to create new pin assignments for these and delete the originals. There are no longer any errors in the configurator.

S32K3 FlexCan in Polling mode Hello,  Im trying to set up the CAN on S32K3, I did not found an example based on polling (not interrupts), using RTD and no Autosar, I did the following config : Pins used are PTA28 – PTA27 (CAN-0) Standard CAN with 500Kb – 8 bytes payload Clock for CAN enabled FlexCan_Send function will execute successfully only once, after that the bus goes into busy state and will not transmit any CAN frame, after adding   FlexCAN_Ip_AbortTransfer seems to work, but im not sure if this was the correct approach ? Flexcan_Ip_StatusType FlexCan_Send(uint16_t Idx, uint8_t *data) { Flexcan_Ip_StatusType retVal = E_NOT_OK; Flexcan_Ip_DataInfoType tx_info = { .msg_id_type = FLEXCAN_MSG_ID_STD, .data_length = 8u, .is_polling = FALSE, /* Specifies if the MB is in polling mode */ .is_remote = FALSE, /* Specifies if the frame is standard or remote */ }; if(FlexCAN_Ip_GetTransferStatus(INST_BOARD_INITPERIPHERALS_FLEXCAN_0, TX_MB_IDX) == FLEXCAN_STATUS_BUSY) { FlexCAN_Ip_AbortTransfer(INST_BOARD_INITPERIPHERALS_FLEXCAN_0, TX_MB_IDX); } retVal = FlexCAN_Ip_Send(INST_BOARD_INITPERIPHERALS_FLEXCAN_0,TX_MB_IDX,&tx_info, Idx, &data[0]); return retVal; } A Task runs each 5ms for reading the CAN frames in polling mode, the FlexCAN_Ip_Receive keep returning Status_Busy __attribute__((__noreturn__)) void Can_Polling_Tsk_5ms( void *pvParameters ) { (void)pvParameters; for( ;; ) { FlexCan_Read(); vTaskDelay(pdMS_TO_TICKS(5)); } } Flexcan_Ip_StatusType FlexCan_Read() { Flexcan_Ip_StatusType retVal = E_NOT_OK; Flexcan_Ip_MsgBuffType recvBuff; retVal = FlexCAN_Ip_Receive(INST_BOARD_INITPERIPHERALS_FLEXCAN_0, RX_MB_IDX, &recvBuff, TRUE); if(retVal == FLEXCAN_STATUS_SUCCESS) { // Process the received frame... } return retVal; } Thank you. Re: S32K3 FlexCan in Polling mode Hi @Kazarian, Sorry for the late reply. You can refer to this community post: S32K1xx-FlexCAN Mask Setting Demo - NXP Community. It does refer to the S32K1xx, but the theory is the same. You must call the functions below in stop or freeze mode. FlexCAN_Ip_SetRxMaskType(); FlexCAN_Ip_SetRxMbGlobalMask(); This community post may also prove helpful: Solved: S32K344 FlexCAN: How to setup Rx MB mask to receive the CAN FD messages with different IDs? - NXP Community. Best regards, Julián  Re: S32K3 FlexCan in Polling mode Hello @Julián_AragónM  Any idea how you can set the RX filter for a range of IDs ? Regards. Re: S32K3 FlexCan in Polling mode Thanks a lot @Julián_AragónM this works,  There is another question on how to enable the reception of all Ids not only the ID configured with the function FlexCAN_Ip_ConfigRxMb : retVal |= FlexCAN_Ip_ConfigRxMb(INST_BOARD_INITPERIPHERALS_FLEXCAN_0, RX_MB_IDX, &rx_info, MSG_ID); is there a function where i can set a kind of mask across a range of Ids i want to receive, say for example from 0x10 to 0x74D. Regards. Re: S32K3 FlexCan in Polling mode Hi @Kazarian, I understand you are creating your own functions implementing the RTD. Even though it is working, the abort mechanism provides a safe way to request the abortion of a pending transmission. A feedback mechanism is provided to inform the CPU whether the transmission was aborted, or the frame could not be aborted and was transmitted instead. There is an existing polling example (although it is based in S32K312) in the following community post: Example S32K312 CAN Transmit & Receive Using Polling mode DS3.5 RTD300 - NXP Community. It implements both write and read in polling mode like this: rx_info.is_polling = TRUE; //Dinesh FlexCAN_Ip_Send(INST_FLEXCAN_0, TX_MB_IDX, &rx_info, MSG_ID, (uint8 *)&dummyData); // Polling while(FlexCAN_Ip_GetTransferStatus(INST_FLEXCAN_0, TX_MB_IDX) != FLEXCAN_STATUS_SUCCESS) { FlexCAN_Ip_MainFunctionWrite(INST_FLEXCAN_0, TX_MB_IDX); } // Polling while(FlexCAN_Ip_GetTransferStatus(INST_FLEXCAN_0, RX_MB_IDX) != FLEXCAN_STATUS_SUCCESS) { FlexCAN_Ip_MainFunctionRead(INST_FLEXCAN_0, RX_MB_IDX); } Nevertheless, if your configuration is working, there should be no problem. Best regards, Julián

Can not find the driver Hello,   I meet a problem as the attached picture, I need some help to solve it, Thanks.  Re: Can not find the driver @Senlent  Thank you, I don't know what happend to my project just after a PC restart or some other system issue yesterday and I have done a reactivate to S32DS v3.4 too, However I tried to create a new empty project and migrate my project and it take effect, the problem resolved. Thank you Re: Can not find the driver Hi@jinT This kind of problem may can be solved by click "update code". If click "update code" can't solve your problem , i will help you to check it if you can provided the project.

Regarding the limitations of Key Scramble settings Hi NXP According to NXP application note, OTFAD_KEY_SCRAMBLE and ALIGN were arbitrary word and byte. But when I set non-SPT default values (0x33AA55CC & 0x1B), the RT10101 fails to decrypt and boot .[On my EVT board] .It stops in ISP mdoe. =================================================================== On the NXP RT1010 EVB, writing the default settings(0x33AA55CC & 0x1B) allows it to boot successfully. The following are the steps on NXP EVB Step 1. Burning fuses[OTFAD KEK & SCRAMBLE] => boot successfully. Step 2. Burning fuses[HAB] => boot successfully. =================================================================== On non-NXP EVB device, writing the non-default settings ,the RT10101 fails to decrypt and boot and stops in ISP mdoe. The following are the steps on my EVT board Step 1. Burning fuses[OTFAD KEK] => boot successfully. Step 2. Burning fuses[HAB] => boot successfully. Step 3. Burning fuses[SCRAMBLE] => boot Fail. I use SPT for programming, and during the programming process, it will verify that the SPT fuses settings match the device. Therefore, my settings should be correctly written to my EVT board. Using the SPT OTP setting function, I also confirmed that my settings were successfully written to the eFuses. I tried changing the OTFAD encryption block to an unwritten block (e.g., 0x60020000), and my EVT board can boot normally. =>This indicates that there might be an issue with the decryption process. =================================================================== Based on the above successful and failed boot cases: 1. Does the order of writing eFuses affect the functionality of OTFAD and Scramble? 2. Are there any configuration limitations for OTFAD_KEY_SCRAMBLE and ALIGN? Does this mean there is an issue with OTFAD and Scramble? Re: Regarding the limitations of Key Scramble settings Hi Stefano, Here is an update for your problem: for i.MX RT116x/7x, the image_enc utility was replaced by nxpimage already in SEC v7. That's why SEC v7 produces same problem in keyblob as SEC v10. For RT117x kindly use SEC v6. You can still use the processor with your custom fuses, only the keyblob needs to be fixed (bootable_images\otfad_keyblobs.bin).  Alternatively, it shall be also possible to generate keyblob in SEC v6 and replace the keyblob generated by SEC v10 (it is possible to add hook into SEC v10 build script). To do this, you must have all keys and all OTFAD parameters same in both workspaces. We are sorry for inconvenience Re: Regarding the limitations of Key Scramble settings Hello Marek, I can confirm that image produced with V7 using a scramble value of 0x19a8c836 and a scramble align of 0xd6 doesn't work - while using the default values the image works. Note however that I used different keys and random counter. I carefully checked fuse settings on the non-working board (the one with the mentioned scramble values) and they look correct. Apparently, image_enc tool is producing a bad key blob. As a side note, I am surprised that issues on such a sensitive topic (image protection) are not being appropriately addressed: how is it possible that, although ages have passed, it is still not possible to reliably get a correctly formed bootable image from SPT? Best regards, Stefano Re: Regarding the limitations of Key Scramble settings Hi Stefano, scramble for RT116x/7x and RT10xx is confirmed bug in MCUXpresso Secure Provisioning tool v10 and currently there is not planned any hotfix. RT117x is supported since MCUXpresso Secure Provisioning tool v5, so we recommend to use older version (v7). There is not known such problem for image_enc tool. For the input image, kindly follow the description in chapter 6.2.1.1 and disable XIP_BOOT_HEADER_ENABLE (images with the header are not supported in tool version 7). We are sorry for inconvenience Re: Regarding the limitations of Key Scramble settings Hello, having same trouble on rt1176 using SEC V10 - can you confirm the problem still exists on V10? Besides, since V7 does not accept binary images with boot header nor ELF files (at least, not those built within MCUXpresso IDE v11.9.0 Build 2144), I'm having hard times with V7 too - and the encrypted image (from blinky sample) does not work anyway. Looks like older image_enc tool suffers the same bug with some scrambling value and/or align. I am quite surprised this issue has not been addressed yet, since it is actually a security flaw - scrambling is definitely useless if you can (safely) use only default values. Kudos Stefano Re: Regarding the limitations of Key Scramble settings Hi Omar, yes, use SEC v7. The problem is in nxpimage utility, which is used to generate keyblob since SEC v8. In the older versions, keyblob was generated using image_enc utility. Re: Regarding the limitations of Key Scramble settings Hi @marek-trmac     I am using SPT V9.0.1.  Do you mean that I need to use version V7.0 to generate the correct keyblob data based on my scramble values ?  Re: Regarding the limitations of Key Scramble settings Hi Omar, we confirm the problem, we found the keyblob is generated wrongly for same scramble values. The problem is reproducible since SEC tool v8. Could you use SEC tool v7? In version 7 the tool uses image_enc utility to generate the keyblob and there is no such issue. We are sorry for the inconvenience. We'll fix the problem for next release. Re: Regarding the limitations of Key Scramble settings Hi @marek-trmac  Thank you for your reply.  what ALIGN fuse value did you burn? =>Since the setting values are intended for future production, it is inconvenient to disclose them. I can only say that I have set them within the range of 0x00 to 0xFF. Does default OTFAD settings works on your custom board? =>Due to concerns about causing the aforementioned situation again, I am currently not burn any scramble config( OTFAD_KEY_SCRAMBLE and ALIGN) to the custom board. Re: Regarding the limitations of Key Scramble settings Hi Omar, what ALIGN fuse value did you burn? Does default OTFAD settings works on your custom board? Re: Regarding the limitations of Key Scramble settings Hi @marek-trmac      Thank you for your reply.     I have used SPT to erase the flash in the above steps, and then used SPT to rewrite the updated KEY blobs and firmware. Re: Regarding the limitations of Key Scramble settings Hi Omar, after you burn SCRAMBLE, you need to update key blobs (because key blobs are affected by the SCRAMBLE). There is application note with details about OTFAD encryption on RT101x, which might help: AN12670 How to use encrypted XIP boot.in i.MX RT1010 About ALIGN, please refer to chapter "Key blob KEK details" in Security Reference Manual.