SJA1110A DSA bring UP : 100BASE-TX TX failure and T1 link training issues Hello, I am bringing up an SJA1110AEL switch connected to a Microchip PolarFire SoC over SPI using the Linux DSA sja1105 driver from the Microchip Linux 6.12 FPGA tree: https://github.com/linux4microchip/linux/tree/linux-6.12-mchp%2Bfpga/drivers/net/dsa/sja1105 The switch is configured in SPI boot mode (BOOT_OPTION=11), and the static configuration upload appears successful. [ 2.546758] sja1105 spi9.0: Probed switch chip: SJA1110A
[ 2.546777] sja1105 spi9.0: max_xfer_len = 256 bytes
[ 2.549576] sja1105 spi9.0: Config buffer length: 1776 bytes
[ 2.549605] sja1105 spi9.0: Config buffer device_id at offset 0: 0x0f0300b7
[ 2.742531] sja1105 status decoded: CONFIGS=1 CRCCHKL=0 IDS=0 CRCCHKG=0 NSLOT=9
[ 2.742563] sja1105 spi9.0: sja1105_static_config_load done
[ 2.742579] sja1105 spi9.0: sja1105_clocking done
[ 2.742592] sja1105 spi9.0: sja1105_TAS and flower setup done
[ 2.743823] sja1105 spi9.0: sja1105_ptp_clock_register done
[ 2.888661] sja1105 spi9.0: sja1105_mdiobus_register done
[ 2.888699] sja1105 spi9.0: sja1105_devlink_setup done
[ 2.902778] sja1105 spi9.0: dsa_tag_8021q_register and rtnl_unlockdone
[ 2.904141] sja1105 spi9.0: configuring for fixed/sgmii link mode
[ 2.909745] sja1105 spi9.0: Link is Up - 1Gbps/Full - flow control off
[ 2.964511] sja1105 spi9.0 rj45 (uninitialized): PHY [spi9.0-base-tx:01] driver [NXP CBTX (SJA1110)] (irq=POLL)
[ 2.973125] sja1105 spi9.0 t1-1 (uninitialized): PHY [spi9.0-base-t1:01] driver [Generic Clause 45 PHY] (irq=POLL)
[ 2.976322] sja1105 spi9.0 t1-2 (uninitialized): PHY [spi9.0-base-t1:02] driver [Generic Clause 45 PHY] (irq=POLL)
[ 2.979382] sja1105 spi9.0 t1-3 (uninitialized): PHY [spi9.0-base-t1:03] driver [Generic Clause 45 PHY] (irq=POLL)
[ 2.982622] sja1105 spi9.0 t1-4 (uninitialized): PHY [spi9.0-base-t1:04] driver [Generic Clause 45 PHY] (irq=POLL)
[ 2.985855] sja1105 spi9.0 t1-5 (uninitialized): PHY [spi9.0-base-t1:05] driver [Generic Clause 45 PHY] (irq=POLL)
[ 2.989002] sja1105 spi9.0 t1-6 (uninitialized): PHY [spi9.0-base-t1:06] driver [Generic Clause 45 PHY] (irq=POLL)
[ 2.991420] macb 20110000.ethernet eth0: entered promiscuous mode
[ 2.991540] DSA: tree 0 setup
[ 2.993156] clk: Disabling unused clocks
##############################################
*************** FSW-PIXXEL ***************
*************** IN_xPC ***************
##############################################
# ip a
1: lo: mtu 65536 qdisc noqueue state UNKNOWN group default qlen 1000
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
inet 127.0.0.1/8 scope host lo
valid_lft forever preferred_lft forever
inet6 ::1/128 scope host proto kernel_lo
valid_lft forever preferred_lft forever
2: bond0: mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 4e:0a:f0:7b:bc:e0 brd ff:ff:ff:ff:ff:ff
3: can0: mtu 16 qdisc noop state DOWN group default qlen 10
link/can
4: can1: mtu 16 qdisc noop state DOWN group default qlen 10
link/can
5: eth0: mtu 1536 qdisc noop state DOWN group default qlen 1000
link/ether 5e:78:8f:24:86:53 brd ff:ff:ff:ff:ff:ff
6: eth1: mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 00:04:a3:61:cc:6f brd ff:ff:ff:ff:ff:ff
7: sit0@NONE: mtu 1480 qdisc noop state DOWN group default qlen 1000
link/sit 0.0.0.0 brd 0.0.0.0
8: rj45@eth0: mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 5e:78:8f:24:86:53 brd ff:ff:ff:ff:ff:ff
9: interswitch@eth0: mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 5e:78:8f:24:86:53 brd ff:ff:ff:ff:ff:ff
10: epc2-uplink@eth0: mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 5e:78:8f:24:86:53 brd ff:ff:ff:ff:ff:ff
11: t1-1@eth0: mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 5e:78:8f:24:86:53 brd ff:ff:ff:ff:ff:ff
12: t1-2@eth0: mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 5e:78:8f:24:86:53 brd ff:ff:ff:ff:ff:ff
13: t1-3@eth0: mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 5e:78:8f:24:86:53 brd ff:ff:ff:ff:ff:ff
14: t1-4@eth0: mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 5e:78:8f:24:86:53 brd ff:ff:ff:ff:ff:ff
15: t1-5@eth0: mtu 1500 qdisc noop state DOWN group default qlen 1000
link/ether 5e:78:8f:24:86:53 brd ff:ff:ff:ff:ff:ff
16: t1-6@eth0: mtu 1500 qdisc noop state DOWN group default qlen 1000 Current observations: CPU port (SGMII) comes up correctly. I can receive ARP packets from a laptop connected to the RJ45 100BASE-TX port. tcpdump on the board confirms incoming ARP requests from the laptop. When transmitting from the board (ping/arping), the laptop does not receive anything. Laptop tcpdump shows no RX packets from the board. My questions are: Is any additional runtime MAC configuration/forwarding / route-table setup required for TX traffic to work correctly on SJA1110 DSA ports? Is it expected that the 100BASE-T1 PHYs appear only as Generic Clause 45 PHY with this driver tree? Is there a missing dedicated BASE-T1 PHY driver in the current Linux 6.12 Microchip tree? For testing, I attempted a direct loopback between two T1 ports (t1-1 <-> t1-2) by connecting: (TRX_1_P<->TRX_2_P and TRX_2_P<->TRX_2_N ). Do the SJA1110 BASE-T1 PHYs require explicit master/slave configuration for link training? 8: rj45@eth0: mtu 1500 qdisc noqueue state UP group default qlen 1000
link/ether 5e:78:8f:24:86:53 brd ff:ff:ff:ff:ff:ff
inet6 fe80::5c78:8fff:fe24:8653/64 scope link proto kernel_ll
valid_lft forever preferred_lft forever
11: t1-1@eth0: mtu 1500 qdisc noqueue state LOWERLAYERDOWN group default qlen 1000
link/ether 5e:78:8f:24:86:53 brd ff:ff:ff:ff:ff:ff
inet 192.168.10.1/24 scope global t1-1
valid_lft forever preferred_lft forever
12: t1-2@eth0: mtu 1500 qdisc noqueue state LOWERLAYERDOWN group default qlen 1000
link/ether 5e:78:8f:24:86:53 brd ff:ff:ff:ff:ff:ff
inet 192.168.10.2/24 scope global t1-2
valid_lft forever preferred_lft forever
[ 133.739306] macb 20110000.ethernet eth0: configuring for fixed/sgmii link mode
[ 133.739364] MACB : HWSTAMP check running
[ 133.739414] MACB : HWSTAMP check passed found tsu_clk
[ 133.741036] macb 20110000.ethernet: gem-ptp-timer ptp clock registered.
[ 133.742794] sja1105 spi9.0 t1-1: configuring for phy/internal link mode
[ 149.008075] sja1105 spi9.0 t1-2: configuring for phy/internal link mode
[ 543.849763] sja1105 spi9.0 rj45: configuring for phy/internal link mode
[ 545.889486] sja1105 spi9.0 rj45: Link is Up - 100Mbps/Full - flow control off Hardware strap configuration: All PHY_MS pins are strapped LOW (slave mode). PHY_AUTO_MODE = HIGH AUTO_POL_DET = HIGH PHY addresses start from 0x09. Could the reason for no T1 link be that both PHYs are strapped as SLAVE, and therefore no master clock source exists for link training? Any guidance regarding: correct T1 bring-up, master/slave configuration, or expected PHY driver support would be greatly appreciated. Here is the DTSI that is being used for the Ethernet switch. /* MAC0 : DSA master into SJA1110A SGMII4 */
&mac0 {
/delete-property/ phy-handle;
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&fabric_fic3_clk>;
clock-names = "pclk", "hclk", "tsu_clk";
phy-mode = "sgmii";
status = "okay";
dma-noncoherent;
fixed-link {
speed = <1000>;
full-duplex;
};
};
/*
* SPI9: SJA1110A Host Access Port (HAP)
* CS0 (reg=0) -> SS0_N -> Switch AP endpoint (DSA driver)
* CS1 (reg=1) -> SS1_N -> Cortex-M7 uC endpoint (unused)
*
* BOOT_OPTION=11 (serial SPI boot):
* SJA1110A waits for host config at power-on.
* DSA driver sends static config tables at probe via CS0.
* Cortex-M7 is disabled by driver : CS1/SS1 never used.
*
* SPI mode: CPOL=1 CPHA=0 (mode 2) : as per sja1105.yaml
* SPI mode: CPOL=1 CPHA=1 (mode 3) : as per s32gxxxa-rdb.dtsi
*/
&spi9 {
microchip,motorola-mode = <3>; /* mode 3: CPOL=1 CPHA=1 */
num-cs = <2>;
status = "okay";
/*
* SJA1110A : DSA switch (mainline driver)
* reg=0 -> CS0 -> SS0_N -> switch AP endpoint
* ethernet-switch@0 uses reg=<0> (SS0 = switch AP)
* sja1110-uc@1 uses reg=<1> (SS1 = uC, disabled here)
*
* Port map
* port@0 RevMII Cortex-M7 uC (disabled by driver)
* port@1 100BASE-TX RJ45 diagnostic jack
* port@2 RGMII2 inter-switch trunk -> SJA port2
* port@3 SGMII3 EPC-2 MAC1 relay uplink
* port@4 SGMII4 EPC-1 MAC0 CPU port (this board)
* Confirm is actual physical address needs to be added here
* port@5 100BASE-T1 TRX_1 (PHY addr 9 on mdio@0)
* port@6 100BASE-T1 TRX_2 (PHY addr 10 on mdio@0)
* port@7 100BASE-T1 TRX_3 (PHY addr 11 on mdio@0)
* port@8 100BASE-T1 TRX_4 (PHY addr 12 on mdio@0)
* port@9 100BASE-T1 TRX_5 (PHY addr 13 on mdio@0)
* port@a 100BASE-T1 TRX_6 (PHY addr 14 on mdio@0)
*/
sja1110a: ethernet-switch@0 {
compatible = "nxp,sja1110a";
reg = <0>;
spi-max-frequency = <1000000>;
interrupt-parent = <&gpio8>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
mdios {
#address-cells = <1>;
#size-cells = <0>;
mdio_t1: mdio@0 {
compatible = "nxp,sja1110-base-t1-mdio";
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
port5_base_t1_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x01>;
};
port6_base_t1_phy: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x02>;
};
port7_base_t1_phy: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x03>;
};
port8_base_t1_phy: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x04>;
};
port9_base_t1_phy: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x05>;
};
port10_base_t1_phy: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x06>;
};
};
mdio_tx: mdio@1 {
compatible = "nxp,sja1110-base-tx-mdio";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
txphy1: ethernet-phy@1 {
reg = <1>;
};
};
};
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 { reg = <0>; status = "disabled"; };
/* -------------------------------------
* RJ45 diagnostic port
* ------------------------------------- */
port@1 {
reg = <1>;
label = "rj45";
phy-mode = "internal";
phy-handle = <&txphy1>;
};
port@2 {
reg = <2>;
label = "interswitch";
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
fixed-link { speed = <1000>; full-duplex; };
};
port@3 {
reg = <3>;
label = "epc2-uplink";
phy-mode = "sgmii";
fixed-link { speed = <1000>; full-duplex; };
};
/* -------------------------------------
* CPU port
* MAC0 <-> SGMII4 <-> port4
* ------------------------------------- */
port@4 {
reg = <4>;
label = "cpu";
ethernet = <&mac0>;
phy-mode = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@5 {
reg = <5>;
label = "t1-1";
phy-mode = "internal";
phy-handle = <&port5_base_t1_phy>;
};
port@6 {
reg = <6>;
label = "t1-2";
phy-mode = "internal";
phy-handle = <&port6_base_t1_phy>;
};
port@7 {
reg = <7>;
label = "t1-3";
phy-mode = "internal";
phy-handle = <&port7_base_t1_phy>;
};
port@8 {
reg = <8>;
label = "t1-4";
phy-mode = "internal";
phy-handle = <&port8_base_t1_phy>;
};
port@9 {
reg = <9>;
label = "t1-5";
phy-mode = "internal";
phy-handle = <&port9_base_t1_phy>;
};
port@a {
reg = <10>;
label = "t1-6";
phy-mode = "internal";
phy-handle = <&port10_base_t1_phy>;
};
};
};
/* SPIDEV for testing SPI lines using CS1 lines*/
sja110_spidev: spidev@1 {
compatible = "microchip,mpfs-spidev";
reg = <1>;
status = "okay";
spi-max-frequency = <1000000>;
};
}; -- Ankur Re: SJA1110A DSA bring UP : 100BASE-TX TX failure and T1 link training issues Hello @Ankur_pixl ,
Thank you for sharing all details at once.
Please find answers to your question below.
Q1. Is any additional runtime MAC configuration/forwarding / route-table setup required for TX traffic to work correctly on SJA1110 DSA ports?
A1. Yes, please find it below.
Q2. Is it expected that the 100BASE-T1 PHYs appear only as Generic Clause 45 PHY with this driver tree? Is there a missing dedicated BASE-T1 PHY driver in the current Linux 6.12 Microchip tree?
A2. No.
Q3. For testing, I attempted a direct loopback between two T1 ports (t1-1 <-> t1-2) by connecting: (TRX_1_P<->TRX_2_P and TRX_2_P<->TRX_2_N ).
A3: Yes, that's correct.
Q4. Do the SJA1110 BASE-T1 PHYs require explicit master/slave configuration for link training?
A4. Yes, 100BASE-T1 requires explicit Master/Slave settings. FYI, option "AUTO" in a driver usually means "follow pin strapping". For a valid link, one PHY must be configured as MASTER and the other as SLAVE, either via hardware strapping or PHY configuration.
From your logs and DT, the switch initialization and PHY binding look correct.
The behavior, where RX works but TX does not, is expected if no bridge is configured in Linux. In DSA, traffic is not forwarded automatically between the CPU port and user ports. DSA switch behaves like a hardware switch, but Linux does not enable forwarding between ports unless a bridge or VLAN configuration is explicitly created.
Please create a bridge and attach both the CPU port (eth0) and the user port (rj45):
ip link set eth0 up
ip link set rj45 up
ip link add br0 type bridge ip link set br0 up ip link set eth0 master br0 ip link set rj45 master br0
ip addr add 192.168.1.2/24 dev br0
Best regards,
Pavel
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