S32K148 45 節を使用して phy レジスタの書き込みを読み取ることはできますか? SMIインターフェースを使用してPHYチップを制御する予定です。しかし、SDKに45項のphy制御インターフェースが見つかりません。 ユーザーマニュアルを読みました。S32K148第45条を支持することができます。 SDKにインターフェースはありませんか? Re:S32K148節45を使用してphyレジスタの書き込み読み取りを実行できますか? アーム2.2にS32DSを使用しています。 SDk は 3.0.0 です。3.0.0の例第45節の例はありません。 アームのS32DSに対する第45条のサポートはありませんか?

Industrial i.MX8QM clock frequencies Hi everyone, We are currently doing tests on the MIMX8QM5CVUFFAB and found some strange behaviour regarding clocks. The first thing we noted is that even though the clock is limited to 1.3 GHz for the Cortex A72 and 1.104 GHz for the Cortex A53, the cpufreq driver allows us to set the higher frequency of 1.6 GHz and 1.2 GHz. The SCFW seems to correctly ignore the higher frequencies but this leads to a missmatch between cpufreq and the actual clock rate: root@apalis-imx8-15556460:~# cat /sys/bus/cpu/devices/cpu4/cpufreq/scaling_cur_freq 1596000 root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep a72 a72_clk 0 0 0 1296000000 0 0 50000 Y cpu4 no_connection_id root@apalis-imx8-15556460:~# cat /sys/bus/cpu/devices/cpu0/cpufreq/scaling_cur_freq 1200000 root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep a53 a53_clk 0 0 0 1104000000 0 0 50000 Y cpu0 We would expect that this is either solved by a special cpufreq driver or then by a fdt fixup in U-Boot. However, I can't find any of this solutions in the BSP. Can you confirm that this is currently not implemented? A second clocking issue affects the GPU, even though according to the datasheet the GPU should only run at 625 MHz it runs at 800MHz: root@apalis-imx8-15556460:~# cat /sys/kernel/debug/gc/clk gpu0 mc clock: 797983833 HZ. gpu0 sh clock: 996002801 HZ. gpu1 mc clock: 798002539 HZ. gpu1 sh clock: 995989749 HZ. root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep gpu gpu_shader1_clk 0 0 0 996000000 0 0 50000 Y 54100000.gpu shader gpu_core1_clk 0 0 0 798000000 0 0 50000 Y 54100000.gpu core gpu_shader0_clk 0 0 0 996000000 0 0 50000 Y 53100000.gpu shader gpu_core0_clk 0 0 0 798000000 0 0 50000 Y 53100000.gpu Here the SCFW does not limit the clock, which seems to be a violation of what is written in the datasheet. My expectation would also be here that there is a fdt fixup in U-Boot to address this but I could not find it. Can you confirm that this is currently not implemented? The version of the SCFW, ATF and U-Boot should be recent enough to properly support the i.MX8QM with the 1.3 GHz limitation: U-Boot 2024.04-34984-g64f00b21ff8 (Dec 04 2024 - 14:42:45 +0100) CPU: NXP i.MX8QM RevB A53 at 1104 MHz at 33C DRAM: 4 GiB Core: 203 devices, 24 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: Toradex 0091 Apalis iMX8QM 4GB WB IT V1.1A Serial#: 15556460 Boot: MMC0 Reset cause: POR BuildInfo: - SCFW 83624b99, SECO-FW c9de51c0, IMX-MKIMAGE ca5d6b2d, ATF 616a458 - U-Boot 2024.04-34984-g64f00b21ff8 Best regards, Stefan i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Re: Industrial i.MX8QM clock frequencies current bsp is based on nxp mek board, don't find specific bsp for industrial, you can change the bsp by yourself Re: Industrial i.MX8QM clock frequencies Hi @joanxie  Thanks for the update. Can you point me to the right BSP for the industrial version of the i.MX8? Thanks and best regards Stefan Re: Industrial i.MX8QM clock frequencies the bsp you used isn't for industrial, so the A72 core define 1596000000 as max, you can remove this from a72_opp_table: opp-table-1 linux-imx/arch/arm64/boot/dts/freescale/imx8qm.dtsi at lf-6.6.y · nxp-imx/linux-imx · GitHub you also can refer to this workaround, for the 1.3G imx8qm  [OUTDATED] Workaround for de-rating i.MX 8QM/QP parts before SCFW 1.16.0 releases - NXP Community Re: Industrial i.MX8QM clock frequencies Hi @joanxie  The following versions are used: SCFW: 1.17.0 (83624b99) U-Boot: lf_v2022.04 https://github.com/nxp-imx/uboot-imx/tree/lf_v2024.04 Linux: lf-6.6.y https://github.com/nxp-imx/linux-imx/tree/lf-6.6.y Regards, Stefan Re: Industrial i.MX8QM clock frequencies what bsp version and SCFW version do you test? let me double check it

SBC FS26 state Flow Hello, its a bit difficult to understand the Simplified functional state diagram given in the datasheet of FS26 as somethings are not mentioned Detailly, is there any Documented or Video kind of thing where this is Explained detailly, if not Can someone Explain it in the Post. Re: SBC FS26 state Flow Hello @JozefKozon , I have the Eval-Board RDK358BMU, and facing some issue with FS26 w.r.t Standby mode and wakeup.  could you please send me the same document ? would also appriciate if you send me an example, considering Eval-Board RDK358BMU. B.T.W , my company has already a valid NDA. thanks in advance BR Abdullah Re: SBC FS26 state Flow @JozefKozon Please send me this file. It has already been established that there is a valid NDA agreement. Thank you. Re: SBC FS26 state Flow @JozefKozon Could you do me a favor and send me an email with the requested FS26 diagram. I would appreciate it very much. Re: SBC FS26 state Flow Hi Djuric, thank you for creating the case. I see it already in our inbox. We will support you via the case. For your company name, yes I have entered incorrect name. I have read your company name from your email address, but this is not correct one. In the case you created I see your company name in the description and for this, yes there is a valid NDA in our database. With Best Regards, Jozef Re: SBC FS26 state Flow I opened a new ticket. The only problem I can think of is that you entered the wrong name of the company I work for. If you contact me by private message, I will send you the exact name of the company as well as the tag from the NDA contract. This whole process is very slow and unnecessarily complex... Re: SBC FS26 state Flow Dear Djuric, I apologize for a late reply. I have checked our NDA database and unfortunately I couldn't find your company listed there. If the NDA was signed only recently, it is possible that it wasn't entered into our system yet. Please create a new case here and we will support you via the case. I apologize for inconvenience and thank you for your understanding.  With Best Regards, Jozef Re: SBC FS26 state Flow @JozefKozon I would appreciate it if you could send me the same FS26 diagram you mentioned in the previous comment. The company I work for has a signed NDA agreement with NXP, which I also uploaded via the NXP website. Thank you. Re: SBC FS26 state Flow @JozefKozon Can you send me the same document? My company has a valid NDA agreement with NXP. Thank you. Re: SBC FS26 state Flow Hello @JozefKozon  Can you please send me this file as well, please? Re: SBC FS26 state Flow Hi Jozef, Yeah, Just gone through the Application Note, things are somewhat clear in this. Thank you for the Document. Re: SBC FS26 state Flow I am using FS26 Safety system basis chip with low power for ASIL D/ASIL B (ds616040-FS26) Datasheet, isn't it the same ? Re: SBC FS26 state Flow Hi Naveen,  I have sent you an email. With Best Regards, Jozef

Configuring memory protection unit (MPU) in i.MX RT1040 Hello, I am trying to enable the MPU for RT1040 and configure a couple of sections of the RAM as non-executable. I am unable to find the relevant document / example code to be able to configure the MPU for this chip. From this link https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/TEE-for-ARM-Cortex-M7-based-MCU/td-p/1753242, I got information about the “tee_fault” example in “SDK_2_16_000_MIMXRT1160-EVK” and learned about the McuXpresso Config TEE tool. But this tool is not supported for RT1040. So, my questions are: How do I configure the MPU for RT1040 processor? Are there any example code / documentation which I can refer to? Thanks Re: Configuring memory protection unit (MPU) in i.MX RT1040 Thank you. I think I can proceed with these references. Re: Configuring memory protection unit (MPU) in i.MX RT1040 Hi @rd24  - Firstly, I would like to share the dedicated application note about the cache system that includes the L1 cache, memory types, attributes and MPU (Memory Protection Unit) https://www.nxp.com/docs/en/application-note/AN12042.pdf - There are no any dedictaed examples about MPU feature, but you can understand from below sample code in many examples. https://github.com/nxp-mcuxpresso/mcux-sdk-examples/blob/52b428258efda7d5bd8a2ace2195ca828356743a/evkmimxrt1040/demo_apps/hello_world_virtual_com/hello_world.c#L85  MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); /* Enable MPU */ ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); Re: Configuring memory protection unit (MPU) in i.MX RT1040 Hi @Sam_Gao, Thanks for your quick reply. I have checked the BOARD_ConfigMPU() function from the hello_world example and understood the MPU configurations. I understand that after configuring and enabling the MPU, if an access is made to a region without the right permissions a MemManage fault is raised. Is there a handler for the MemManage fault? Is there an example code which demonstrates this scenario? Thanks Re: Configuring memory protection unit (MPU) in i.MX RT1040 Hi @rd24  1. About SDK of I.MX RT1040, please download from https://mcuxpresso.nxp.com/en/builder?hw=MIMXRT1040-EVK which supports our nxp.com/i.mxrt EVK board for reference. 2. About MPU configuration, you can refer anyone of examples (e.g, helloworld) in source/xx.c reference code like below, `BOARD_ConfigMPU` function is for configration when doing init board hardware. int main(void) { char ch; /* Init board hardware. */ BOARD_ConfigMPU(); BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitDebugConsole(); /* Just enable the trace clock, leave coresight initialization to IDE debugger */ SystemCoreClockUpdate(); CLOCK_EnableClock(kCLOCK_Trace); PRINTF("hello world\r\n");

ioctl_cmds.h The document iMX8MP_CAMERA_DISPLAY_GUIDE.pdf mentions: Interface header file: mediacontrol/include_api/ioctl_cmds.h This header file is referenced by a number of Vivante header files but doesn't get built into the Yocto SDK (I am currently using Scarthgap with the Toradex 7.0.0 BSP). Sometimes this file is built in the /build/tmp/work directory but not with Toradex BSPs. I have to go find this file in a build from a different BSP and add it directly to my Qt project when I update Yocto. Is it possible to force this file to be created and added to the SDK? Thanks i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Multimedia Yocto Project 回复：ioctl_cmds.h 谢谢你！这有效。 回复：ioctl_cmds.h 该文件内置于isp-imx SDK中，您可以构建独立的isp-imx包，步骤如下： $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/isp-imx-xxx.bin $ chmod +x isp-imx-xxx.bin $ ./isp-imx-xxx.bin $ cd isp-imx-xxx $ ./build-all-isp.sh 发布部分

imx93evk rebuild kernel image and replace ! This is the command i build for the imx93evk $ mkdir imx-yocto-bsp $ cd imx-yocto-bsp $ repo init -u https://github.com/nxp-imx/imx-manifest -b imx-linux-scarthgap -m imx-6.6.36-2.1.0.xml $ repo sync $ mkdir -p downloads $ cd downloads $ mkdir linux-imx; cd linux-imx $ git clone https://github.com/nxp-imx/linux-imx.git $ cd ../.. $ export BSPDIR=$(pwd) $ DISTRO=fsl-imx-wayland MACHINE=imx93-11x11-lpddr4x-evk source imx-setup-release.sh -b buildwayland $ bitbake imx-image-multimedia after building finish, the directory imx-yocto-bsp/buildwayland/tmp/sysroots-components/imx93_11x11_lpddr4x_evk/imx-boot/boot will contain imx-boot-imx93-11x11-lpddr4x-evk-sd.bin-flash_singleboot ! is using $ sudo ./uuu -b emmc_all imx-boot-imx93-11x11-lpddr4x-evk-sd.bin-flash_singleboot ! a correct way to update the image that reflect the kernel changes i made in the linux-imx? ! what is the recommended way to only build the linux kernel and replace the kernel only, is it $ cd linux-imx $ make imx93_11x11_evk_defconfig $ make ! and which image should i burn specifically for replacing the kernel? BR, Colin         Re: imx93evk rebuild kernel image and replace When you finish rebuild you can use the scp commend to copy the kernel images to your board Re: imx93evk rebuild kernel image and replace Yes, could you provide the steps that we can follow? Re: imx93evk rebuild kernel image and replace Here do you just need to rebuilt and update the kernel on the board?

IMX93EVK no uart log Bought imx93evk, power it up and connect the USB DBG to my pc and open up the tty to check the log with 115200, but failed to see any log, after flashing with sudo ./uuu LF_v6.6.52-2.2.0_images_IMX93EVK.zip, still can not see usrt log, what do i miss? Re: IMX93EVK no uart log i found out there are actually multiple port being open and i was only targeting the first, which ends up no output, thanks Re: IMX93EVK no uart log HI lykaios1203 The i.MX 93 Applications Processor has six independent UART ports (UART1 – UART6). On the MCIMX93-EVK board, UART1 is used for Cortex-A55 core, and UART2 is used for Cortex-M33 core. A single chip USB to dual UART, JTAG, and I2C is used for UART debug and remote debug. The part number is FT4232H. The developers can download the driver from FTDIwebsite. After the driver for FT4232H is installed, the PC will enumerate four COM ports when the USB cable is plugged into the J1401 connector, the third port is used for A55 and fourth for M33 system debugging.  Regards Daniel Re: IMX93EVK no uart log pin attached

[i.MX6] 我如何知道 CK 和 ADDR/CMD 之间的 i.MX6 输出时序？ 大家好， 我如何知道 CK 和 ADDR/CMD 之间的 i.MX6 输出时序？ 对于 DQ 或 DQS，我发现了有关读取校准或写入校准的信息，但我看不到有关 CK 和 ADDR/CMD 的信息。 我需要这些参数来进行 SI 模拟。 在此先感谢您的帮助！ 回复：[i.MX6] 我如何知道 CK 和 ADDR/CMD 之间的 i.MX6 输出时序？ 好的，我会检查一下。很抱歉错过了 回复：[i.MX6] 我如何知道 CK 和 ADDR/CMD 之间的 i.MX6 输出时序？ 如果使用 LPDDR2，CA-Bus 延迟显示在寄存器 WRCADL 中。 对于 DDR3，没有寄存器，因为 JEDEC 没有对其进行培训。 CK到CA的延迟由路由规则控制。您可以在 HDG 中找到它。 回复：[i.MX6] 我如何知道 CK 和 ADDR/CMD 之间的 i.MX6 输出时序？ 您需要做什么 SI 仿真，对于 DDR 部分，我们为其配置了脚本和压力测试工具。 回复：[i.MX6] 我如何知道 CK 和 ADDR/CMD 之间的 i.MX6 输出时序？ 由于此文件补充了我们的问题，请确认。

Calibration features Hello,  I wonder if FreeMaster is capable of being used as a calibration tool. For example, calibrate a thermistor with a NXP board.  Another question on top of this: is it possible to apply a function to a raw signal before it is displayed on a graph in FreeMaster? Thanks  Re: Calibration features Hi @Vast-Horizon, Yes, you can use FreeMASTER as calibration tool. Here's an example of how it could be used in such scenario: Implement the algorithm in the embedded application Store algorithm parameters in global volatile variables Use FreeMASTER to read algorithm parameters at runtime Use FreeMASTER to update parameter values to fine tune the algorithm You can also apply transformation functions on the variables before those are displayed. This option is available in the Variable menu (Project -> Variables -> Edit): Note: transformations are applicable only to REAL values (top right option) Hope it helps, Iulian

PP4/PW4 pin Hello newbie here, I'm looking at a mc9s12gc (52 pin) on HVAC board and noticed that a Thermostat(Basically a potentiometer) what I would think should be tied to an input pin is wired to the PP4/PW4 pin. Can the PW4 pin be configured as an input? Everything I've read says it is a Pulse width modulated waveform output. I know most thermostats are just open/closed contacts but this one is not. Thanks Re: PP4/PW4 pin Hi @P0zburn, This is not an ATD (ADC) pin, it can be a digital input only. Best regards, Daniel Re: PP4/PW4 pin Thanks for the response.  I have a follow up question. Once it is configured as an input, can it be used as a analog input? Re: PP4/PW4 pin Hello @P0zburn, The PP4/PW4 pin is a GPIO. The direction is configurable in the DDRP register.

MC9S12C64MFA IOC4 question Hi All, MC9S12C64, Code Warrior 5.9.0, coding in assembler. I've been wrestling with a problem I am having getting the input capture function to work for well over a week now with no success. It's time to swallow my pride and beg for help. I have all the other timer functions working well, but the IC has me stumped, both IOC4 and IOC5. I put together an absolute minimum test code (attached). If anyone can offer suggestions I'd really appreciate it. Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Daniel, Update. After trying just about every combination of everything I could think of I finally got the test program to work. I think the key issue was the way I was clearing the flags. As for the IRQ, I didn't notice that the pullups for Port E are set after reset. I used an external pullup in my other program so that kind of messed me up. I've attached my latest test program. Now I have to see if I can get them to work in my main program, but at least I have this working for an example.  Thanks so much for all your help. I doubt that I could have solved this without it. Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Daniel, Thanks for the clarification on IRQ and XIRQ. I think I understand it now. I have experimented with use of the pullup but I still can't get it, or IOC4 or IOC5 to trigger their respective ISRs. PARTIDH is $31, PARTIDL is $03. What does that tell you? Regards, Robert  Re: MC9S12C64MFA IOC4 question Hi Robert, I believe this is well explained here: https://www.nxp.com/docs/en/data-sheet/MC9S12C128V1.pdf Can you double-check the part ID in the PARTIDH and PARTIDL registers? Thank you Re: MC9S12C64MFA IOC4 question Hi Daniel, Thanks for that link. I studied it and think I have made the correct changes to my program (attached). Unfortunately I still can't get either IOC channel or IRQ to trigger their respective ISRs. I'm still not quite clear on the IRQ channels. It is my understanding that IRQ (PE1) is set to falling edge capture only if IRQCR, IRQE is set to 1. To enable PE1 does IRQCR, IRQEN have to be set to 1 as well? I tried that and still didn't get it to work. Is PE0 a separate IRQ channel and if so what triggers it, Falling edge, Rising edge or Hi or Lo level? The manual doesn't give me much information on this, or at least I can't find it if it does. Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Robert, There is one issue in the code I overlooked. It is the BSET instruction used to clear the flags. BSET does read-modify-write operation at the register, which clears every flag that is set in the register. It is explained here: https://www.nxp.com/docs/en/application-note/AN2554.pdf Can you test it? Thank you, Daniel Re: MC9S12C64MFA IOC4 question Hi Daniel, I tried running another larger program I am working on that uses IOC5. It gets a pulsed 5 volt signal to the main board where it is inverted. IOC5 has a pullup and the pulse pulls IOC5 low. I have confirmed this with a scope. With this signal I can also use jumpers to test IOC4 , PE0 (XIRQ) and PE1 (IRQ). I have confirmed continuity of the input pins on the board to the pins on the processor. Even though I have a good signal at the board I'm not able to read it in the ports on the debugger, stopped or running. PTT and PTIT read the same, %11100000. This makes sense because pins 7 and 6 are initialized high and not changed in the program. Pin 5 has a pullup.  A change in IOC4 or IOC5 is not indicated with a pulsed input. When I read PORT E, it is always %00001111. So PE0 and PE1 are always high, no matter what the signal to the board pin is. This indicates to me that there could be an internal problem in the processor, but it seems odd that it should affect these four pins. All the other timer functions work fine, as well as the ITR and ADC channels. Is there any other way I can confirm if these pins are damaged or not? Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Daniel, I'm not fluent in "C" but I believe the MC9S12C64 IRQ is on Port E1 and XIRQ is on Port E0, not Port B, as your attachment indicates. I didn't bring out PE0 on my board so I am just trying to get the IRQ pin working. I wrote a new test program to test the IRQ, IOC4 and IOC5 (attached). It is about as brief as I could make it. I have the ITR toggle PTM5 every 100mS. I use this as a trigger to test the input capture ISRs. I have checked the signal at the ISR inputs with a scope and it is a nice clean 5 volt square wave. When I read PTIT is just shows pins 7 and 6 high which is legitimate as they are commanded high in the timer set up. At no point do they indicate high for IOC4 or IOC5. When I put a break point in any of the ISRs the program doesn't get there which indicates to me that the ISRs have not been triggered. Can you offer any suggestions as to what I am doing wrong? Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Robert, I'm sorry, it is PTIT. IRQ/XIRQ example attached Re: MC9S12C64MFA IOC4 question Hi Daniel, I'm a bit confused about the PWM and TIM functions and which pins they are assigned to. Should I be checking the PTIP register, the PTIT register or both. At this point it looks like IOC4 is not generating an interrupt but it definitely has a 5 volt square wave signal to the IOC4 pin. I discovered this by placing a break point in the ISR with the debugger, but the program never got there. On another matter, I could use the IRQ, or XIRQ pin to monitor my external signal but I'm not clear on how to set it up. Could you advise me on this please? Regards, Robert Robert Re: MC9S12C64MFA IOC4 question Hi Daniel, The fact that my set up looks good is very encouraging. You've made some very good troubleshooting suggestions and I give them all a try. Thanks again. Regards, Robert Re: MC9S12C64MFA IOC4 question Hi @roberthiebert, I have gone through the project but I haven't spotted anything wrong in the configuration. Can you double check all the registers in the debugger's register view? And instead of just checking the PTM4, read the interrupt flag of the TIM_4 channel. Also, The PTIP register will give you the state of the pin in any mode. Re: MC9S12C64MFA IOC4 question That doesn't appear to be the problem. I tried applying a 5 volt 100mS square wave to PT4 and PTM4 is still not toggling. Have I got my set up correct? Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Daniel, Thanks so much for your prompt response. What you say makes sense to me. I'll modify my board and let you know the results. Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Robert, Can you please first make sure there is an edge at the pin? Removing the 5V from the pin does not mean there is 0V. Regards, Daniel

SRAM and SDRAM can interface together with imxrt1062 in one design Hello  I'm designing a new product using the IMXRT1062 controller. I've already interfaced with SRAM and verified that it's working. I'm now planning to interface with SDRAM as well, so that I can access both SRAM and SDRAM as needed. Is it possible to interface with both SRAM and SDRAM using the IMXRT1062? i.MXRT 106x Re: SRAM and SDRAM can interface together with imxrt1062 in one design Hi @VishalAvg , Thanks for your interest in NXP MIMXRT series! Yes, this can be done with SEMC. The SEMC is a multi-standard memory controller optimized for both high-performance and low pin-count. It can support multiple external memories in the same application with shared address and data pins. The interfaces supported include SDRAM, NOR Flash, SRAM, NAND Flash, and 8080 display interface. Best regards, Gavin

s32g3 VR5510 standby mode entry Hi, I am trying to control the VR5510 into standby mode, my base project is the RTD4.0 example ‘Pmic_Configuration_Autosar_Example_S32G399A_M7’ My revision points are the following: 1. Modify the target mode of the structure Pmic_VR55XX_ModeConfigPB_0_0,base value is PMIC_NORMAL_MODE(Is it possible to change only the target mode?) 2. Modify the power mode name of the structure Power_Ip_aModeConfigPB,base value is POWER_IP_RUN_MODE 3. Modify the I2C address to 0x21 4. Add the following code to the main function,write 0x20 to address 0x19，use Pmic_SetMode and Power_Ip_SetMode This post referenced：https://community.nxp.com/t5/Power-Management/VR5510-Standby-mode-entry/m-p/1536237 Finally, use the S32 Debug Probe to simulate Am I going into Standby the right way please? note:Before adding the command sent by I2C, running the program will keep starting again and again, after adding it it doesn't happen, how should I test that the chip is in standby mode My environments: S32G-VNP-RBD3, S32DS 3.5 ,RTD4.0 VR5510 S32G-VNP-RDB3  Re: s32g3 VR5510 standby mode entry Hello, @chenyin_h :     I see that there is a section about entering and exiting Standby in the S32G3 RM documentation. So if I enter Standby, do I need to configure not only VR5510 but also S32G3?Is there any simple example for me to refer to? Re: s32g3 VR5510 standby mode entry Hello, @jiajun  Thanks for the post and sorry for the delay. From my opinion, your modification may not be enough, since some hardware configurations must be done before entering Standby mode. you may reference the AN12880 for details. For standby mode, maybe the following information is useful for your detailed reference. https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/nxp-designs%40tkb/700/1/S32G_Standby_Demo_V4-20221116-Eng.pdf I hope it will help. BR Chenyin

i.MX93 Linux OCRAMを共有メモリとして こんにちは 私はimx93、非セキュアで作業しています。 これが私の問題です:私はlinux a55とm33の間の共有メモリとしてocramを使用したいと思います。 私はLinuxユーザースペーステストプログラムとm33テストプログラムの両方を持っていますが、どちらもocramにアクセスできますが、最初の96KB(20480000 - 20497ff)だけです。もっと手に入れることはできますか?フル640KB? Linux テストプログラムは 0x20480000 で mmap を使用します。バスが0x20498000以上になるとバスエラーが発生します。 注:私はetosuやrpmsgをまったく使用しません。 Linuxはocramをどのように使用しますか?96KBを640KBに増やすことはできますか? 感謝 クリス

i.MX93 Linux OCRAM as shared memory Hello I'm working with an imx93, non-secure. Here's my problem: I want to use ocram as shared memory between the linux a55 and the m33. I have a linux user space test program and an m33 test program that can both access the ocram, but only the first 96KB (20480000 - 20497fff). Can I get more of it? The full 640KB? The linux test program uses mmap at 0x20480000. It gives a bus error if it goes at or above 0x20498000. Note: I won't be using the ethosu or rpmsg at all. How does linux use ocram? Can I increase the 96KB to 640KB? Thanks Chris Re: i.MX93 Linux OCRAM as shared memory Hi You can try to modify ocram permission settings in ATF:plat/imx/imx93/trdc_config.h Add more memory blocks in trdc_n_mbc, 0-5 means six memory blocks(6*16KB=96KB), you need add more. Best Regards Zhiming

Access to the new version of UGS32G-VNP-RDB3-Ethernet-Enablement-Guide Dear NXP fellows, I have access to the Ethernet Enablement Guide for the S32G-VNP-RDB3 through this page: https://www.nxp.com/design/design-center/development-boards-and-designs/s32g3-vehicle-networking-reference-design:S32G-VNP-RDB3 This guide is a valuable resource that helped me to bypass some obstacles. However, this guide is targeting BSP33, which is a bit older. I am currently using BSP39+. So, for example, in following U-boot setting command (page 25), the s32ccgmac is already obsolete: U-boot simply returns: Unknown command 's32ccgmac' - try 'help' Besides, the pfeng_mode is also not useful anymore for U-boot 2022.4. So, my question is: Is there any updated version of this document? If yes, where can I get it? If not, how should I correct my U-boot configuration for the recent versions of the BSP? Thank you very much, Guilherme Re: Access to the new version of UGS32G-VNP-RDB3-Ethernet-Enablement-Guide Hi, @GuilhermeS32G3 : Thanks for your guidance, I have found the file in the picture Re: Access to the new version of UGS32G-VNP-RDB3-Ethernet-Enablement-Guide Hello @jiajun_cheng , As far as I know, the file UGS32G-VNP-RDB3-Ethernet-Enablement-Guide.pdf Rev 1.0 is the latest available version of the document. And I don't know if there are plans to release an updated version. Regarding the figure used by @chenyin_h , it is from the S32G3_Linux_BSP_XX.X_User_Manual.pdf. You can download it by logging in into your NXP account at nxp.com. Then, select "My NXP Account > Apps and Services": Then select "Software Licensing and Support": From the Product List, select "Automotive SW - S32G Reference Software" Then, from the Product Information select "Automotive SW - S32G - Linux BSP (Cortex-A53)": Select the version corresponding to your BSP and board: Accept the Software Terms and Conditions. Finally, download the User Manual: You may find a similar table on page 51: Best regards, Guilherme Re: Access to the new version of UGS32G-VNP-RDB3-Ethernet-Enablement-Guide Hi, @chenyin_h @GuilhermeS32G3 : Hi, I am debugging the Ethernet functionality of RDB3 using BSP 42.0. I noticed that the S32G-VNP-RDB2 Ethernet Enablement Guide is for BSP28, so is there a manual for the newer BSP? My goal is to test the configuration of RDB3Also, can you tell me which file the configuration in this picture comes from? Thank you very much! Re: Access to the new version of UGS32G-VNP-RDB3-Ethernet-Enablement-Guide Hello, @GuilhermeS32G3  Thanks for your reply. I have a few suggestions below: 1. After setting the hwconfig, just reset the board to make it effective, then booting to the kernel. 2. From BSP40UM, the combination (mode0&1) need the following modifications at least: 3. If you want to use the example6 on newer BSPs, then there may be at least changes(DTS) that like what are shown in the ethernet enablement guide, also since big changes between BSP33 and BSP40/41, there would be possiblely other code changes made to make it effective,(would be a new feature to the BSP), but such custom changes is not fully supported through this channel.  I do apologize. BR Chenyin Re: Access to the new version of UGS32G-VNP-RDB3-Ethernet-Enablement-Guide Hello, @chenyin_h  Thanks again for your reply. I updated the BSP to version 41.0 and checked the configuration you kindly provided. Attached are the two boot logs, before (using the configuration of Example 6) and after (using this new configuration). It seems that the main issue may lie in the device tree configuration. As the Net Phy driver is not the default hardware, I am having issues configuring the address of the device. Can you help me to point some suggestions of how to debug this issue and try to enable the PFE interfaces? Best regards, Guilherme Re: Access to the new version of UGS32G-VNP-RDB3-Ethernet-Enablement-Guide Hello, @GuilhermeS32G3  Thank for your feedback. From the requirements from your side, seems you need to set both serdes to mode 1 if GMAC as the SGMII (like example 6) or mode0 for serdes0 and mode1 for serdes1. For the first combination, seems it is not directly supported in current BSP, but for the second one, it seems supported from BSP40 with the following configuration under u-boot: setenv hwconfig "serdes0:mode=pcie,clock=ext;pcie0:mode=rc;serdes1:mode=pcie&xpcs0,clock=ext,fmhz=100;pcie1:mode=rc;xpcs1_0:speed=1G,an=0" I hope it will help. BR Chenyin Re: Access to the new version of UGS32G-VNP-RDB3-Ethernet-Enablement-Guide Hello, @chenyin_h  Thanks for your reply. My concern for the document version is mostly due to the U-boot variations from version 2020.04 (BSP33) and 2022.04 (BSP39). Yes, the idea is to reproduce the Example 6. However, here we are working with a custom design that is based on the S32G399A-RDB3. In this design, we aim to use: PFE_MAC0 in SGMII mode; PFE_MAC1 in RGMII mode; PFE_MAC2 in RGMII mode; GMAC0 may be either disabled or as SGMII. In this case, is there a configuration that may fulfill the design? Best regards, Guilherme Re: Access to the new version of UGS32G-VNP-RDB3-Ethernet-Enablement-Guide Hello, @GuilhermeS32G3  Thanks for your post. The document you mentioned is released at 2022/08, which is relatively early, so that is based on early version software packages. We feel sorry that there seems not an updated version. we apologize. For the command you mentioned, may I know if you want to reproduce the example 6 by using BSP39? From the BSP39UM, seems this combination is not supported: BR Chenyin

如何在imx7d evm上配置emmc设备树 嗨，专家们 我正在尝试通过在 imx7d sabresd evm 上安装 emmc 进行测试。 为了启用 emmc，我在设备树中添加了 usdhc3 status="okay" 并使用 pinctrl_usdhc3 作为 pinctrl 设置 但是，没有MX7D_PAD_SD3_RESET_B_SD3_RESET的引脚描述 在原理图上，emmc 重置 ping 连接到 GPIO_SD3_RESET_B。我是否需要使用 rst-gpios 在 ushdc3 设备树中进行设置？ 真诚感谢 i.MX7 双核 回复：如何在 imx7d evm 上配置 emmc 设备树 你好 是的，你需要使用重置密码 此致 志明

S32G3 GMAC0 and PFE_MAC1 SGMII mode Hello, If I configure GMAC0 and PFE_MAC1 to use SGMII (1G), does that mean both interfaces will utilize SerDes pins for external communication, allowing their respective dedicated pins (e.g., gmac_tx0, gmac_tx1, etc.) to be reassigned to other interfaces? Additionally, if GMAC0 is configured for SGMII, can I still use the GMAC_PPS pin for PPS output? Similarly, if PFE_MAC1 is set to SGMII, can I still connect its PPS pin to another module? Thanks, XD Re: S32G3 GMAC0 and PFE_MAC1 SGMII mode Thank you for the explanation, Celeste! Thanks, XD  Re: S32G3 GMAC0 and PFE_MAC1 SGMII mode Hi @XD , Thank you for your answer. As per your questions: [Q1]: If I configure GMAC0 and PFE_MAC1 to use SGMII (1G), does that mean both interfaces will utilize SerDes pins for external communication, allowing their respective dedicated pins (e.g., gmac_tx0, gmac_tx1, etc.) to be reassigned to other interfaces? [A1]:Given that you are designing a customized board, I recommend you refer to the document "User guide S32G3 Hardware Design Guidelines". S32G3 has two SerDes instances, each SerDes instance has a mux option between PCIe and SGMII. The following mux option can be chosen on the SerDes channels. In addition, I have checked the S32G3 IOMUX Sheet. Regarding your question, I believe it is correct. [Q2]: Additionally, if GMAC0 is configured for SGMII, can I still use the GMAC_PPS pin for PPS output? Similarly, if PFE_MAC1 is set to SGMII, can I still connect its PPS pin to another module? [A2]: Likewise, the answer is yes. For more details, you can refer to Chapter 53 SerDes Subsystem of the S32G3 Reference Manual. The S32G3 SerDes Subsystem Reference Manual is also recommended. I hope the above answers can solve your confusion. Best regards, Celeste Re: S32G3 GMAC0 and PFE_MAC1 SGMII mode Hi Celeste, Thank you for your response. We are designing our own board, using the RDB3 reference design as a reference. Our plan is to configure both GMAC0 and PFE_MAC1 to operate in SGMII mode. Thanks, XD Re: S32G3 GMAC0 and PFE_MAC1 SGMII mode Dear @XD , I apologize for the late response. I would like to know whether you are using the reference board or a customized board. The answers to your questions may vary depending on this. Best regards, Celeste

ADC Notification not getting called in S32K144 MCU In ADC peripheral for S32K1xx MCU's, there are ADC Status and Control Register 1 (SC1A - aSC1P). Onto which ADC channel number and its conversion complete status is represented by bits ADCH and COCO. Now COCO bit is set 1, when ADC conversion of channel reprsented by ADCH bits is completed. And COCO bit is set to 0, only when respective Result register of channel ADCH is read( Registers RA-RP) or when respective SC1n register is written. But, in my demo. ADC channel COCO bits does get set and ADC IRQ is invoked, but when i step into my IRQ handler to debug it. My COCO bit is getting cleared on its own. Why is it sooo??? You can see below figure: IRQ is hit and COCO bit is 1 But as i step into Interrupt, COCO bit gets cleared automatically. Without reading any Result register or I have not performed any write operation on SC1n register. As a result IRQ does not callback notification function at line 1103. Because IRQ checks the COCO bit of SC1n registers to check which channel is interrupted. COCO bit of SC1n register of ADC peripheral is getting cleared onb its own without reading any result register or performing any write operation on SC1n registers. Why is it soo??? Is their something wrong mentioned in datasheet? or somerthing wrong in ADC IRQ handler?? Re: ADC Notification not getting called in S32K144 MCU Okay great, though i was not reading any result register. But i was reading multiple variables and have set inbetween breakpoints.  But when i remove those breakpoints and variables, its starts working as expected. But have got one more dout. I want to use PDB Channel Delay feature. /but am not able to get from where to enable ADC Delay Next PDB, in GUI. I checked on ADC UM manual of S32K1xx, this feature is supported on it. But i cant find from where to enable this feature. Re: ADC Notification not getting called in S32K144 MCU Hi, this can be caused by displaying Result registers so debugger is reading them. Try to do not display result registers or other ADC registers as well. BR, Petr

S32K396 NXP RTOS Missing files Hello, I am trying to create NXP RTOS firmware using Design Studio for S32K396. On creating the firmware (example RTOS_example_S32K396_SC2),I get following error on compilation - ../RTOS_S32K396/include/Os_prop_autosar_api.h:47:17: fatal error: Os_prop.h: No such file or directory Building file: ../board/dcf_config.c 47 | #include "Os_prop.h" /* OS Properties */ | ^~~~~~~~~~~ I checked the installation, the mentioned file `Os_prop.h` is not available.  Is there any other package required which provides this file? Best regards, Nandan Chaturbhuj Re: S32K396 NXP RTOS Missing files Hello, I spend some time to build the example, and looks like you were not reading instruction in description.txt carefully and forget to add RTOS configuration in OS plugin. Such will generate all os required files like c and h into project folder. Best regards, Peter Re: S32K396 NXP RTOS Missing files Following are the packages installed - 1. S32K396_M7_NXP_RTOS_4_7_183_RTM_1_1_0_D2501_DesignStudio_updatesite.zip 2. SW32K3_S32M27x_RTD_R21-11_5.0.0_D2410_DesignStudio_updatesite.zip But the file mentioned is still missing. I checked in the Design studio installation folder as well. The file "Os_prop.h" file is not there as well. Can you share the location you have this file installed or generated ? Re: S32K396 NXP RTOS Missing files Hello, First, make sure tour SW version match the requirements. Could you please list the packages you have used? Like RTD, S3DS versions etc... ? Please respect the version of RTD and S32DS which is required to buide the demo, otherwise you wont be able to compile it: You will find demo requirements description in the demo project: Best regards, Peter