S32K3X4EVB-T172 Unable to Program using OpenSDA I have a fresh-out-the-box S32K3X4EVB-T172 Eval board. The S32 processor seems to be running some factory default code, but when I try to debug/reprogram using the on-board debugger (connected to my computer using USB) both the S32 and the on-board debugger go into reset. I am using the correct Power On/Plug in procedure as described by the S32K3X4EVB-T172 quick start guide. I also have installed the software and addons described there as well. Tried same process with a co-worker's S32K3X4EVB-Q172 and it worked just fine.\ Thanks in advance, -Tobiah Re: S32K3X4EVB-T172 Unable to Program using OpenSDA 1. Please refer to the discussion: PEmicro Connection Assistant Issue on S32K3X4EVB-T172. Do the red LEDs D15(RST_OSDA) and D3(RESET_K3) remain lit, or do they flash periodically? Is your board experiencing the same issue as this customer?   2. Is FS26(U12) hot? 3. Did you follow the steps "3.2 Plug in the Power Supply" and then "3.3 Connect the Debugger Cable"? 4. Plug in the J40 micro-USB cable and observe the D14STATUS OSDA LED. If the D14 orange LED does not light up: Check whether the USB cable is a data cable, verify if the PC enumerates the OpenSDA device, and ensure the USB port and drivers are functioning correctly. Connecting the USB cable to the PC via a USB hub is not recommended. 5. The onboard debugger is provided by PEMicro, it is recommended to download the latest "USB Multilink Resources Installer" from the "Support & Downloads" category of the "Multilink Debug Probes". After installation, open PEFirmwareConfig.exe located in C:\PEMicro\Multilink_Resources to check the firmware version. My onboard debugger's firmware version is 10.98. What version is your board? If the version is too old, it is recommended to update. If the update fails, it is recommended to contact PEMicro technical support. check the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.pngcheck the version of firmware on S32K3X4EVB-T172.png 6. Please use a multimeter in voltage mode or an oscilloscope to observe the voltage of P3V3_SDA (J34). S32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.pngS32K3X4EVB-T172_PackRevB2_Schematic P3V3_SDA J34.png 7. The SDA_RST_TGTMCU is controlled by the output of the onboard debugger K26. If the SDA_RST_TGTMCU outputs a low level, both red LEDs D15 and D3 will light up. Please observe the SDA_RST_TGTMCU (J36) level using an oscilloscope. Is it always low, or is it periodically pulled low? Normally, when downloading a program or resetting the S32K3 via the onboard debugger, a 10ms low level should be observed in the SDA_RST_TGTMCU, causing red LEDs D15 and D3 to light up briefly. 8. Is it possible to debug the onboard S32K3 chip after connecting via J12 using an external debugger? Best Regards, Robin Re: S32K3X4EVB-T172 Unable to Program using OpenSDA I am not sure which version of the RTD Port_Example_S32K344 you are currently testing. However, I suggest setting J31 to positions 2-3 and trying again. Re: S32K3X4EVB-T172 Unable to Program using OpenSDA After some more testing: 5. I was able to update the onboard debugger firmware using the PEFirmwareConfig exe.  The behavior remains the same though when I try to debug/program. 6. J34 voltage is at 3.25V when USB is plugged in. 7. J36 is high until I try to debug/program. At which point it goes low and stays low until the micro USB is disconnected. Still waiting on an adapter for point 8.  It should arrive today. Thank you, -Tobiah Re: S32K3X4EVB-T172 Unable to Program using OpenSDA How can I determine what the version of the example project is? I switched J31 to 2-3. Same behavior. Thanks, -Tobiah Re: S32K3X4EVB-T172 Unable to Program using OpenSDA Please take a photo of the S32K3X4EVB-T172 board after connecting the external 12V power supply to J14 and plugging in the USB cable; the image must be clear enough to show the jumper settings and which LEDs are lit. Please record a video of the S32DS interface, starting from when you click the debug button and continuing until the error screen appears. This will allow me to see exactly what is happening and help troubleshoot the issue quickly. If you cannot record a video of the operations performed in S32DS on the screen, could you take a few screenshots to show the error? Re: S32K3X4EVB-T172 Unable to Program using OpenSDA Hello Robin, 1. Once I attempt to debug/program, both LEDs (D15 and and D3) remain lit. They do not flash.  I believe my board is experiencing the same issue as the customer in https://community.nxp.com/t5/S32K/PEmicro-Connection-Assistant-Issue-on-S32K3X4EVB-T172/m-p/2252525, but it seems he bypassed his issue by purchasing another EVB, which is unfortunate. 2. no 3. yes 4. D14 does light up when I plug in the micro-USB cable.  Device Manager shows "OpenSDA - CDC Serial Port (http://www.pemicro.com/opensda)".  There is no USB hub in the system, and my PC+cable can program other S32K344 EVBs using S32DS.  The issue seems tied specifically to this board. 5-7.  Give me some time to run these down.  I will respond shortly. 8. I have yet to try to JTAG directly as I am waiting on an adapter so I can interface with J12. Thank you for your detailed response, -Tobiah Re: S32K3X4EVB-T172 Unable to Program using OpenSDA Please check whether the jumper settings match those described in "3.1 Set Up Jumpers in the S32K3X4EVB-T172 Evaluation Board." Is the input voltage for J14 12V? Which project did you debug? Would it be possible for you to record a video of the debugging process and share it with me? Re: S32K3X4EVB-T172 Unable to Program using OpenSDA The jumper settings do match. J16 is showing 12V (seemed easier than measuring the jack directly). I am using the project Port_Example_S32K344 as recommended in the quick start guide.  I don't think I will be able to video. -Tobiah Re: S32K3X4EVB-T172 Unable to Program using OpenSDA Finally got a JTAG adapter that works for J12. I can debug the S32K344 chip using an external debugger. OpenSDA still doesn't work. Re: S32K3X4EVB-T172 Unable to Program using OpenSDA Good morning, 00_evb.jpg  ^ Initial state of board after power on and connection of USB 00_dashboard.png  ^ Example project dashboard 03_debug3.png 01_debug1.png 02_debug2.png    ^Debug configuration 04_error1.png  ^ first error after debug 04_evb.jpg  ^ EVB after attempted debug (happens at the same time as the above error) 05_error2.png  ^ error after clicking abort  

ハイサイドセンシングを備えたカスタムハードウェア向けにMCSPTR2AK396リファレンスファームウェア（AMMCLIB/FreeMASTER）を適応させる こんにちは、NXPコミュニティの皆さん、 現在、 S32K396 MCU を使ってモーター制御アプリケーションを開発し、 FreeMASTER / AMMCLIBを通じてテストしています。まず手始めに、 MCSPTR2AK396評価キットに付属のリファレンスファームウェアを使用します。 しかし、私のカスタムハードウェア設計は、主に3つの点でリファレンスEVKボードと大きく異なります。 電流検出トポロジー： EVKボード：ローサイド電流検出。 カスタムデザイン: ハイサイド電流検出。 ゲートドライバー構成: EVKボード: シングルプリドライバー(GD3000 / MC33937タイプ)。 カスタム設計: 3つの独立したゲートドライバ(各相に1つの専用ドライバ)を持ち、直接のアクティブハイ制御入力を備えています。 PWM極性： EVKボード：ハイサイドPWM入力はアクティブロー（反転）です。 カスタム設計: ハイサイドPWM入力はアクティブハイ(反逆なし)です。 これらのハードウェアの不一致により、オリジナルのMCSPTR2AK396ファームウェアをそのまま実行すると、不具合や位相動作の誤りが発生します。 EVK設計からカスタムアーキテクチャへの移行に成功させるために、S32K396初期化、PWM/eMIOS設定、ADCトリガータイミング、AMMCLIBソフトウェア層の変更に関する最適な方法やチェックリストを教えていただけませんか? 何かアドバイスやコードスニペット、設定のヒントがあれば大変ありがたいです。 ありがとう！ よろしくお願いいたします。 エサッキ Re: Adapting MCSPTR2AK396 reference firmware (AMMCLIB/FreeMASTER) for custom hardware with high-side こんにちは、 あなたが述べた変更点(ハイサイド電流検出、異なるゲートドライバアーキテクチャ、PWM極性の変更、そしてそれに伴うモータ制御ソフトウェアの適応)は、MCSPTR2AK396のリファレンス・デザインからの大きな変化を示しており、リファレンスソリューションに大幅な修正が必要です。 本作業はプロジェクト固有の性質と複雑さのため、標準サポートチャネルを通じて完全な移行ガイドを提供することはできません。 カスタムハードウェアにリファレンスソフトウェアを適応させるための専用サポートをご希望の方は、ぜひNXPプロフェッショナルエンジニアリングサービスにご相談ください。 NXPエンジニアリング・サービス よろしくお願いします、 ペトル

EtherCAT and 100Base T1 AtomDeng_0-1790068593516.jpeg AtomDeng_1-1790068718278.png It can be seen from this photo that it supports 100BASE-T1, but the actual situation is that the development board does not have this T1 interface. Board Design MCXC Re: EtherCAT and 100Base T1 Hi @AtomDeng , Thanks for your interest in NXP MIMXRT series! The diagram is an application-level system block diagram, not the hardware block diagram of the MIMXRT1180-EVK. It shows that the i.MX RT1180 Ethernet/EtherCAT interfaces can be connected to external TJA1103 PHYs to implement 100BASE-T1. The MIMXRT1180-EVK itself does not populate TJA1103 PHYs or 100BASE-T1 connectors. Its five onboard Ethernet ports use standard 10/100BASE-TX or 10/100/1000BASE-T PHYs with RJ45 connectors. Please check this diagram in <UM12021 MIMXRT1180-EVK Board User Manual >: Gavin_Jia_0-1790127234062.png Best regards, Gavin Re: EtherCAT and 100Base T1 "While the reference photo or documentation indicates support for 100BASE-T1, the physical connector is likely omitted on this specific board variant. This is common in development hardware where the underlying PHY chip or circuit traces may be present on the PCB, but the physical automotive connector is unpopulated to reduce costs, or the signals are routed to standard pin headers instead." 

EtherCAT and 100Base T1 AtomDeng_0-1790068593516.jpeg AtomDeng_1-1790068718278.png It can be seen from this photo that it supports 100BASE-T1, but the actual situation is that the development board does not have this T1 interface. Board Design MCXC Re: EtherCAT and 100Base T1 你好@AtomDeng ， 感谢您对 NXP MIMXRT 系列产品的关注！ 该图是应用级系统框图，而不是 MIMXRT1180-EVK 的硬件框图。它表明 i.MX RT1180 以太网/EtherCAT 接口可以连接到外部 TJA1103 PHY 以实现 100BASE-T1。 MIMXRT1180-EVK 本身不包含 TJA1103 PHY 或 100BASE-T1 连接器。其五个板载以太网端口采用标准的 10/100BASE-TX 或 10/100/1000BASE-T PHY，并带有 RJ45 连接器。 请查看《 UM12021 MIMXRT1180-EVK 开发板用户手册》中的这张图表： Gavin_Jia_0-1790127234062.png 此致， 加文 Re: EtherCAT and 100Base T1 “虽然参考照片或文档表明支持 100BASE-T1，但此特定电路板版本可能省略了物理连接器。”这在开发硬件中很常见，底层PHY芯片或电路走线可能已经位于PCB上，但为了降低成本，物理汽车连接器可能没有安装元件，或者信号被路由到标准针座上。

对 FRDM-i.MX95 上的 IW612 Zigbee DualPAN 主机软件包 (ZBOSS / zb_mux) 的访问请求 您好，NXP社区与支持团队， 我们正在开发一款基于 NXP FRDM-i.MX95 评估板的商用网关产品，该评估板配备了板载 IW612 三频收发器。我们的主机环境是Linux ARM64。 我们的架构需要通过 SPI (/dev/spidev0.0) 使用 DualPAN 架构的 IW612 802.15.4 无线电同时进行线程 (Matter) 和 Zigbee 协调器操作。 虽然 OpenThread / OTBR 方面有完善的文档和可访问的说明，但 IW612 DualPAN 设置所需的 Zigbee 协调器主机组件和多路复用器是 nxp.com / Secure Files 上的受限交付物。 我们公司（Roth Elektronik GmbH）是 NXP 的直接客户，我们已签署有效的保密协议，并且我们的 NXP 用户帐户配置文件已显示 Zigbee 授权的“已授予”状态。但是，这些下载包在我们的安全文件控制面板中不可见/无法访问。 我们提交了支持案例编号：01004667，但被转接到了当地代理商。由于我们直接从 NXP 采购芯片和电路板，并且我们的企业帐户已经获得了 NDA 和 Zigbee 访问权限，因此需要由 NXP 软件授权/产品线团队直接进行配置。 恩智浦代表或管理员能否协助将案件编号 01004667 上报至公司内部，以便为我们的账户启用以下交付成果？ 1. NXP-ZBOSS-HOST-版本-*.zip（适用于 Linux ARM64 的 ZBOSS 主机堆栈二进制文件/头文件，协调器示例，例如 dualpan_zc / simple_gw） 2. zigbee-rcp-sdk-IW612-*.tar 3. IW612 SPI 的 zb_mux 主机守护进程/多路复用器二进制文件和文档 感谢您提前给予的支持。 此致， 迈克·特施克 罗斯电子有限公司 产品：WiFi IW6XX 协议：Zigbee Re: Access request for IW612 Zigbee DualPAN Host packages (ZBOSS / zb_mux) on FRDM-i.MX95 你好， 希望你一切都好。对于受“安全文件”保护的文件：安全访问权限 | NXP 半导体 请您按照以下步骤操作好吗？ 我建议您查看恩智浦半导体 (NXP Semiconductors) 的“安全访问权限常见问题解答”。 如果您仍有疑问，我建议您联系我们代理商网络|NXP中的一位代理商，他们可以帮助您解决您的问题。 此外，如果您与任何模块制作商合作，他们可以帮助您获得针对其模块的特定支持。 顺祝商祺！ 里卡多

S32K144振荡器跨导问题 你好： 在我的应用设计中，使用了一个 8MHz 晶振，并将 SCG_SOSCCFG[RANGE] 设置为 2b11，因此 gmXOSC 的最小值应为 16mA/V，最大值应为 47mA/V。 Stanley_Xu_0-1790056309153.png 我按照公式 gm_crit = 4 * (ESR + RS) * (2πF)^2 * (C0 + CL)^2 计算并比较了 5*gm_crit 与数据表值。我应该使用 16mA/V 还是 47mA/V？ 我不知道 16 ~47mA/V 是否意味着零件间的差异。如果是这样，从 WCCA 的角度来看，我认为我应该保证 5*gm_crit < 16mA/V。然而，让我感到困惑的是文档 AN5426 第 11 页。给出的计算示例使用 47mA/V 作为标准。 Stanley_Xu_1-1790056639984.png 请问有人能帮我解释一下吗？谢谢你！ Re: Oscillator transconductance question of S32K144 你好@Stanley_Xu ， 严格来说，对于 WCCA，使用最小 gmXOSC = 16 mA/V。16–47 mA/V 的范围反映了工艺（部件之间）、电压和温度的综合变化——任何给定的部件都会在该范围内提供 gmXOSC。数据表标准 gmXOSC > 5 × gm_crit 保证了正确的振荡启动，5x gm_crit 可以被认为是非常安全的，而 3x gm_crit 仍然是安全的。 关于 AN5426：该示例使用 47 mA/V（最大值）进行说明，而不是作为 WCCA。 另一方面，数据手册还指出：“应仔细选择 RS，使其具有合适的振荡幅度，既能保护晶体或谐振器器件，又能满足适当的振荡启动条件。” 此致， 丹尼尔

S32K144の発振器相互コンダクタンスに関する質問 こんにちは： 私のアプリケーション設計では8MHzのクリスタルを使用し、SCG_SOSCCFG[範囲]は2b11に設定されているため、gmXOSCは最低16mA/V、最大47mA/Vとしています Stanley_Xu_0-1790056309153.png そして、gm_crit = 4 * (ESR + RS) * (2πF)^2 * (C0 + CL)^2 という式に従って、5*gm_crit を計算し、データシートの値と比較しました。16mA/Vを使うべきか、それとも47mA/Vを使うべきか？ 16～47mA/Vというのは、部品ごとのばらつきを意味するのかどうか分かりません。もしそうなら、WCCAの視点からは5星gm_crit <16mA/Vを保証しようと思います。しかし、私を混乱させたのは、文書AN5426の11ページです。提示された計算例では、基準値として47mA/Vを使用しています。 Stanley_Xu_1-1790056639984.png どなたか説明を手伝ってもらえますか?ありがとう！ Re: Oscillator transconductance question of S32K144 こんにちは、 @Stanley_Xu さん。 WCCAに限っては、最小gmXOSC = 16 mA/Vを使用してください。16～47 mA/Vの範囲は、製造プロセス（部品間）、電圧、温度の変動を総合的に反映したものであり、どの部品もこの範囲内のgmXOSC値を示す。データシートのクライテリオンGMXOSC > 5× gm_critは適切な発振起動を保証しており、5倍gm_critは非常に安全とみなせますが、3x gm_critも安全です。 AN5426に関して：この例では、WCCAとしてではなく、説明のために47 mA/V（最大）を使用しています。 一方、データシートには「RSは、水晶発振器や共振器デバイスを保護し、適切な発振開始条件を満たすために、適切な発振振幅を持つように慎重に選択する必要がある」とも記載されている。 よろしくお願いいたします。 ダニエル

8MPLUSLPD4-PEVK – 当前 eMMC 和 QSPI 内存配置 你好， 我想确认一下目前出货的 8MPLUSLPD4-PEVK 的内存配置。 NXP 当前的产品页面明确指出： 6 GB LPDDR4 16 GB eMMC 64 MB QSPI 然而，NXP 的 PEVK 快速入门指南明确指出： 6 GB LPDDR4 32 GB eMMC 32 MB QSPI NXP 在线聊天支持建议产品页面可能代表当前的硬件版本，而快速入门指南可能指的是早期版本，但建议与 i.MX 技术团队确认这一点。 NXP 的相关人员能否确认一下当前 8MPLUSLPD4-PEVK 硬件版本的 eMMC 和 QSPI 容量？ 谢谢！ Re: 8MPLUSLPD4-PEVK – current eMMC and QSPI memory configuration 您好， 感谢您对恩智浦半导体产品的关注， 我已经用我桌上的 8MPLUSLPD4-PEVK 确认过，其配置为 32GB eMMC 和 32MB QSPI。经审查最新原理图修订版，所有版本均未对内存进行重新配置，订购时应收到相同的内存。 我们的团队会审核产品页面，感谢您的分享。 此致

8MPLUSLPD4-PEVK – 現在のeMMCおよびQSPIメモリ構成 こんにちは、 現在出荷されている8MPLUSLPD4-PEVKのメモリ構成を確認させていただきたい。 現在のNXP製品ページには次のように記載されています: 6 GB LPDDR4 16GB eMMC 64 MB QSPI しかし、NXPのPEVKクイックスタートガイドには次のように記載されています。 6 GB LPDDR4 32GB eMMC 32 MB QSPI NXPのライブチャットサポートは、製品ページが現在のハードウェアリビジョンを表している可能性が高く、クイックスタートガイドは以前のバージョンを指している可能性があると示唆しましたが、i.MX 技術チームに確認することを勧めました。 NXPの方が現行の8MPLUSLPD4-PEVKハードウェアリビジョンのeMMCおよびQSPI容量を確認できますか? よろしくお願いします。 Re: 8MPLUSLPD4-PEVK – current eMMC and QSPI memory configuration こんにちは、 NXP Semiconductors製品にご関心いただきありがとうございます。 手元にある8MPLUSLPD4-PEVKで確認したところ、構成は32GBのeMMCと32MBのQSPIでした。最新の回路図リビジョンを確認したところ、どのリビジョンでもメモリの再構成は行われておらず、注文時に同じメモリが届くはずです。 私たちのチームが製品ページをレビューします。共有してくださりありがとうございます。 よろしくお願いします。

Ara Vision Examples Multi-Stream YOLOv8 Object Detection  This post shows a walkthrough of the ARA2 Vision Examples demo and its multi-stream YOLOv8 object detection application. The ara2-vision-examples demo provides vision AI examples for NXP i.MX platforms using Ara240 DNPU acceleration. It demonstrates real-time video processing with AI/ML inference capabilities such as object detection, classification, pose estimation, and semantic segmentation. This walkthrough focuses on the Go Point launch of the application, which uses GStreamer to process up to eight simultaneous video streams, run YOLOv8 object detection on each stream, and display the results in a single mosaic view.   Key Features Multi-stream video processing from 1 to 8 streams YOLOv8 object detection accelerated by Ara240 DNPU Support for YOLOv8n, YOLOv8s, YOLOv8m, YOLOv8l, and YOLOv8x models GStreamer-based video pipeline Mosaic display output with bounding boxes Runtime options for stream count, model selection, synchronization, and endpoint selection FPS and IPS performance overlay per stream   Running the Demo Run the application with the default settings: multistream_yolov8 Run with a specific number of streams: multistream_yolov8 -s 4 Select a different YOLOv8 model: multistream_yolov8 -s 4 --model yolov8s Run eight streams for maximum throughput: multistream_yolov8 -s 8 --sync false Enable synchronized playback: multistream_yolov8 -s 4 --sync true   Walkthrough Video In the attached video, it is shown how to launch the application from GoPoint, configure the number of streams, select different YOLOv8 models, and view the object detection results in the mosaic display.  This video is currently being processed. Please try again in a few minutes. (view in My Videos) Summary Ara-Vision-Examples is the reference application showcasing edge vision AI on the Ara240 Discrete NPU (DNPU). It runs real-time object detection, classification, pose estimation and semantic segmentation over single or multiple (up to eight) video streams, rendering bounding boxes, labels and confidence scores. Links ARA2 Vision Examples repository: https://github.com/nxp-imx-support/ara2-vision-examples Multi-stream YOLOv8 README: https://github.com/nxp-imx-support/ara2-vision-examples/blob/main/tasks/object-detection/yolov8n/multistream-gstreamer/README.md ARA2-M2-16G-GT ARA240 Hands-On Training

2-CH CAN HAT with FRDM-IMX93 Enabling a 2-Channel CAN HAT (MCP2515) on the NXP i.MX93 FRDM Board This article documents the process of adding hardware support for a 2-Channel CAN HAT from WaveShare using dual Microchip MCP2515 controllers over SPI on the NXP i.MX93 FRDM evaluation board. By default, the board exposes native FlexCAN interfaces, but utilizing a popular Raspberry Pi-compatible CAN HAT requires customizing the Linux device tree and kernel configuration. Prerequisites Hardware: NXP i.MX93 FRDM board, 2-Channel CAN HAT. Software: NXP Linux BSP (Tested in 6.18.y). Toolchain: Toolchain obtained from Yocto (Refer to the 4.5.12 How to build U-Boot and Kernel in standalone environment from i.MX Linux User's Guide). Step 1: Modify the Device Tree We need to edit the main board device tree file  arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts  to configure the SPI master, add the dual MCP2515 nodes, assign interrupt pins, and disable conflicting native interfaces. The key changes: Power Regulators: Ensured the expansion connectors ( VEXP_3V3 and VEXP_5V ) correctly pull up and preserve state using pinctrl-assert-gpios . Fixed Clock: Defined an external 16MHz clock element required by the MCP2515 crystal oscillators. FlexCAN Deactivation: Disabled conflicting native flexcan2 nodes sharing pins. LPSPI3 Configuration: Replaced the default spidev dummy node with two microchip,mcp2515 nodes, adding two distinct Chip Select (CS) pins ( GPIO2_IO08 and GPIO2_IO07 ) and mapping the respective hardware interrupts ( GPIO2_IO23 and GPIO2_IO25 ). Device Tree Git Diff: diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts index 18afe964e020..7b3af73f144f 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts @@ -134,6 +134,7 @@ reg_vexp_3v3: regulator-vexp-3v3 { compatible = "regulator-fixed"; regulator-name = "VEXP_3V3"; gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&pcal6524 2 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; @@ -144,6 +145,7 @@ reg_vexp_5v: regulator-vexp-5v { compatible = "regulator-fixed"; regulator-name = "VEXP_5V"; gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&pcal6524 8 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; @@ -269,6 +271,15 @@ K3: user_btn2 { interrupts = <6 IRQ_TYPE_EDGE_FALLING>; }; }; + + clocks { + clk16m: clk16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "clk16m"; + }; + }; }; &adc1 { @@ -292,7 +303,7 @@ &flexcan2 { pinctrl-0 = <&pinctrl_flexcan2>; pinctrl-1 = <&pinctrl_flexcan2_sleep>; xceiver-supply = <&reg_can2_stby>; - status = "okay"; + status = "disabled"; }; &mu1 { @@ -620,15 +631,29 @@ typec1_dr_sw: endpoint { &lpspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpspi3>; - cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; - pinctrl-assert-gpios = <&pcal6408 0 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>; + pinctrl-assert-gpios = <&pcal6408 0 GPIO_ACTIVE_LOW>; status = "okay"; - spidev0: spi@0 { + can0: can@0 { + compatible = "microchip,mcp2515"; reg = <0>; - compatible = "lwn,bk4"; - spi-max-frequency = <1000000>; + clocks = <&clk16m>; + interrupt-parent = <&gpio2>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; }; + + can1: can@1 { + compatible = "microchip,mcp2515"; + reg = <1>; + clocks = <&clk16m>; + interrupt-parent = <&gpio2>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + }; + + }; &lpuart1 { /* console */ @@ -894,9 +919,12 @@ MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e pinctrl_lpspi3: lpspi3grp { fsl,pins = < MX93_PAD_GPIO_IO08__GPIO2_IO08 0x39e + MX93_PAD_GPIO_IO07__GPIO2_IO07 0x39e MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x39e MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x39e MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x39e + MX93_PAD_GPIO_IO23__GPIO2_IO23 0x39e + MX93_PAD_GPIO_IO25__GPIO2_IO25 0x39e >; }; After modifying the file, compile your device tree blobs (.dtb) and deploy them to your target boot partition. You can refer to the below post to know the process: How to compile Linux Kernel Image and device tree using Yocto SDK. Step 2: Enable Kernel Driver Support The MCP251x driver must be enabled within the Linux kernel configuration framework. Run the configuration tool: user@host:~/linux-imx$ make menuconfig Navigate through the menu to enable the driver either statically ( [*] ) or as a module ( [M] 😞 [*] Networking support <*> CAN bus subsystem support <*> Raw CAN Protocol (raw access with CAN-ID filtering)   <*> Broadcast Manager CAN Protocol (with content filtering) <*> CAN Gateway/Router (with netlink configuration) And: Device Drivers [*] Network device support <*> CAN Device Drivers CAN SPI interfaces <*> Microchip MCP251x and MCP25625 SPI CAN controllers <*> Microchip MCP251xFD SPI CAN controllers Save your configuration and compile your kernel/modules. Step 3: Initialize and Test Interfaces Once the board boots with the new device tree and kernel, you should see two new network interfaces listed under ip link show ( can0 and can1 ). Manuel_Salas_0-1790114307590.png Now, you can setup the CAN interfaces: $ sudo ip link set can0 up type can bitrate 1000000 $ sudo ip link set can1 up type can bitrate 1000000 $ sudo ifconfig can0 txqueuelen 65536 $ sudo ifconfig can1 txqueuelen 65536 Connect the HAT in loopback: Manuel_Salas_5-1790114793732.png From Interface can0: candump can0 From interface can1: cansend can1 000#11.22.33.44 Manuel_Salas_1-1790114548204.png Manuel_Salas_2-1790114560757.png Manuel_Salas_3-1790114583087.png Hope this can be helpful. Best regards, Salas. i.MX93

Smart Device Gateway Smart Device Gateway In this post, I want to share a quick walkthrough of Smart Device Gateway, a FastAPI-based demo server that allows connected devices to use local GenAI capabilities accelerated by the Ara240 DNPU. The idea behind this demo is to centralize AI intelligence in one gateway instead of adding powerful AI hardware to every device. A connected device only needs a microphone, speaker, and network connection to become a voice-enabled assistant.   What It Does Smart Device Gateway enables devices such as appliances or embedded clients to send audio to a local server, process the request using speech recognition, RAG, an LLM running on Ara240 DNPU, and text-to-speech, then stream the spoken response back to the client. The current demo showcases intelligent device assistants for a generic oven and coffee machine/barista use case, using device manuals as the knowledge base for contextual responses.   Architecture Overview The Smart Device Gateway receives audio from a client over WebSocket, converts speech to text, retrieves relevant context from a device knowledge base, sends the prompt to the LLM through the eIQ AAF Connector, converts the generated response back to speech, and streams the audio response to the client. At a high level, the flow is: Audio Input → STT → RAG → eIQ AAF Connector / LLM → TTS → Audio Output The LLM runs on the Ara240 DNPU, while the server runs on the FRDM i.MX platform.   Run the Server from Command Line Start the server: run_server_only --host 0.0.0.0 --port 8080 The server expects the eIQ AAF Connector to already be running on 0.0.0.0:8000 with Qwen2.5-7B-Instruct properly configured. Alternatively, the demo can start the server together with the connector: run_server --host 0.0.0.0 --port 8080   Host PC Client Example The demo includes a push_to_talk client that can run on a host PC. After copying the push_to_talk folder, run: python -m uv run push_to_talk.py --server_ip --port --device oven You can also use: python -m uv run push_to_talk.py --server_ip --port --device barista If no device name is provided, the RAG knowledge base is not used and the response is generated from the LLM’s general knowledge.   Walkthrough Video In the attached video, I show how to start the Smart Device Gateway server, connect a client, select a device profile such as oven or barista, ask a voice question, and receive a spoken response generated locally using Ara240 DNPU acceleration. This video is currently being processed. Please try again in a few minutes. (view in My Videos)   Summary Smart Device Gateway demonstrates how everyday devices can become voice-enabled assistants by connecting to a local AI gateway. By combining STT, RAG, LLM inference on Ara240 DNPU, and TTS, the demo provides a practical reference for building local, privacy-focused GenAI experiences on NXP i.MX platforms.   Link Smart Device Gateway repository ARA2-M2-16G-GT ARA240 Hands-On Training

VLM Edge Studio VLM Edge Studio In this post, I want to share a quick walkthrough of VLM Edge Studio, an NXP launcher application designed to interact with supported Vision-Language Models running locally on FRDM i.MX platforms with Ara240 DNPU acceleration. VLM Edge Studio provides a Qt/QML-based GUI for model selection, prompt input, and visual interaction with locally running VLMs at the edge. It communicates with the Ara240 Runtime SDK through the eIQ AAF Connector using a REST-based interface and streaming token responses.   Key Features Local Vision-Language Model inference on supported i.MX platforms Ara240 DNPU acceleration GUI-based model selection and prompt input Streaming token output Integration with eIQ AAF Connector and Ara240 Runtime SDK Support for camera-based visual input using a USB-C HD camera   Supported Model Qwen2.5-VL-7B-Instruct-Ara240 This model is provided as an Ara240-compatible model.dvm file and is intended for local execution on the target platform.   Running VLM Edge Studio Start the application with: run_vlm_edge_studio Before launching, make sure the Ara240 runtime service is running: systemctl status rt-sdk-ara2.service --no-pager -l Once the GUI appears, click LOAD to load the model. After the model is ready, enter a prompt and submit it to interact with the VLM locally on the i.MX platform.   Walkthrough Video In the attached video, I show how to launch VLM Edge Studio from GoPoint, load the supported Vision-Language Model, submit a prompt, and interact with the model running locally with Ara240 DNPU acceleration. (function() { var wrapper = document.getElementById('lia-vid-6405413539112w960h540r760'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos) Summary VLM Edge Studio is a useful tool for evaluating local Vision-Language Model inference on NXP i.MX platforms using Ara240 DNPU acceleration. It provides a simple workflow for loading the model, entering prompts, and interacting with visual-language AI directly at the edge.   Link VLM Edge Studio repository ARA2-M2-16G-GT ARA240 Hands-On Training

LLM Edge Studio LLM Edge Studio In this post, I want to share a quick walkthrough of LLM Edge Studio, an NXP launcher application designed to test supported Large Language Models running locally on i.MX platforms with Ara240 DNPU acceleration. LLM Edge Studio provides a simple GUI to select a model, load it, enter prompts, and interact with an LLM directly at the edge. It communicates with the Ara240 Runtime SDK through the eIQ AAF Connector, using a REST-based interface for prompt submission and streaming token responses.   Key Features Local LLM inference on supported i.MX platforms Ara240 DNPU acceleration GUI-based model selection and prompt input Streaming token output Integration with eIQ AAF Connector and Ara240 Runtime SDK   Supported Models Qwen2.5-coder-1.5B Qwen2.5-7B-Instruct These models are provided as Ara240-compatible model.dvm files and are intended for local execution on the target platform.   Running LLM Edge Studio Start the application with: run_llm_edge_studio Before launching, make sure the Ara240 runtime service is running: systemctl status rt-sdk-ara2.service --no-pager -l Once the GUI appears, click LOAD to load the selected model. After the model is ready, enter a prompt and submit it to start interacting with the LLM.   Walkthrough Video In the attached video, I show how to launch LLM Edge Studio from GoPoint, load a supported model, submit a prompt, and view the generated response running locally on the i.MX platform with Ara240 DNPU acceleration. (function() { var wrapper = document.getElementById('lia-vid-6405411704112w960h540r491'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos)   Summary LLM Edge Studio is a useful tool for quickly evaluating local LLM inference on NXP i.MX platforms using Ara240 DNPU acceleration. It provides a simple workflow for model loading, prompt testing, and observing token streaming directly at the edge. Link LLM Edge Studio repository: https://github.com/nxp-imx-support/llm-edge-studio ARA2-M2-16G-GT ARA240 Hands-On Training

EIQ Connector eIQ AAF Connector In this post, I want to share a quick walkthrough of eIQ AAF Connector, a REST-based server that enables LLM and VLM inference on NXP i.MX platforms using the Ara240 DNPU. The connector provides a simple HTTP interface for client applications to send prompts and receive streaming token responses from models running locally on Ara240. It is also the communication layer used by applications such as LLM Edge Studio and VLM Edge Studio.   Key Features REST API server for Ara240-accelerated model inference Chat Completions-style HTTP endpoint Streaming token responses Support for text LLMs and Qwen2.5-VL models Model configuration through server_config.json Optional tool calling and guided generation support for compatible text models Optional semantic prompt caching for text models OpenAPI documentation available through the /docs endpoint   How It Works The eIQ AAF Connector runs on the i.MX host and exposes a REST API. Client applications send prompts to the connector, which communicates with the Ara240 Runtime SDK and the loaded model.dvm running on the Ara240 DNPU. The response is returned as generated tokens, with support for streaming output.   Basic Setup Activate the connector's virtual environment: source /usr/share/eiq/aaf-connector/venv/bin/activate Run the connector: connector By default, the server starts on: 127.0.0.1:8000 To allow access from another device, start it with: connector --host 0.0.0.0   Configuration The connector uses a JSON configuration file named server_config.json to define server settings and available models. This includes model paths, tokenizer paths, model type, prompt size, tool calling support, and whether the model should be loaded at startup. { "log_level": "INFO", "model_config_path": "/usr/share/llm/{}/", "model_tokenizer_path": "/usr/share/llm/{}/tokenizer", "available_models": [ { "name": "qwen2_5-7b", "description": "Qwen2.5 7B instance", "type": "text", "tool_calling": "native", "max_prompt_size": 2047, "enabled": true } ] }   Sending a Test Request Once the server is running, a basic request can be sent to the chat completions endpoint: curl -H 'Content-Type: application/json' \ -d '{ "model": "Qwen2.5-7B-Instruct", "messages": [ { "role": "user", "content": "Who are you?" } ] }' \ -X POST 0.0.0.0:8000/v1/chat/completions The API can also be tested from the OpenAPI UI at: http://0.0.0.0:8000/docs   Walkthrough Video In the attached video, I show how to start the eIQ AAF Connector, verify the server is running, configure a model, and send a sample request to the /v1/chat/completions endpoint. (function() { var wrapper = document.getElementById('lia-vid-6405412604112w960h540r179'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos)   Summary The eIQ AAF Connector provides the REST API layer for running edge AI models on NXP i.MX platforms with Ara240 DNPU acceleration. It allows applications to send prompts, receive generated responses, and integrate local LLM or VLM inference into demos, prototypes, and edge AI workflows.   Link eIQ AAF Connector repository   ARA2-M2-16G-GT ARA240 Hands-On Training

Compatibility of Camera module with OX05B1S Sensor and in-built ISP with i.MX95 FRDM Hi All, Want to know if camera module with ox05b1s sensor and in-built ISP (similar to 5MP RGB-IR Global Shutter GMSL2 Camera for NVIDIA Jetson AGX Orin would be compatible with i.MX95 FRDM board). I do understand that i.MX95 only have MIPI_CSI2 port hence I need to find GMSL2 to MIPI_CSI2 converter, however my question is specifically related to compatibility of existing driver that is part of NXP Linux BSP. Will driver Camera driver of NXP Linux release directly work with this camera module? Do I need to make modification in dtb file? Any other modifications would or additional work that I need to plan for? Re: Compatibility of Camera module with OX05B1S Sensor and in-built ISP with i.MX95 FRDM Hello, The camera will not work directly with the i.MX95 BSP driver. The OX05B1S sensor driver may be reusable, but the GMSL2 setup adds another layer that needs integration. You will likely need DTB changes for the SerDes configuration (GMSL2 bridge, I2C routing, GPIOs, CSI-2 link) and possibly driver modifications for the GMSL2 serializer/deserializer. It’s not a plug-and-play Maxim Time Clock setup, so plan for some BSP customization and validation work. Re: Compatibility of Camera module with OX05B1S Sensor and in-built ISP with i.MX95 FRDM Hi @sarve043swaray  Thank you for the response. Could you please provide some guidance on how to modify dtb file also any idea on where to (file/folder) integrate serializer/de-serializer i2c command? Regards Re: Compatibility of Camera module with OX05B1S Sensor and in-built ISP with i.MX95 FRDM is this your similar topic? you can refer to this,  https://community.nxp.com/t5/i-MX-Processors/OX05B1S-GMSL2-camera-with-MAX96717-MAX96724-on-i-MX95/td-p/2403429 this is about imx95 camera porting guide, you also can refer to this to get to know the basic porting steps on the imx95 https://docs.nxp.com/bundle/UG10215/page/topics/imx95_applications_processor_camera_software_archi.html you also can refer to the 7.3.10.3 Camera modules of user guide, currently imx95 supports  X-MX95MBDESER01 (MAX96724 deserializer) + 4 modules X-MX95MBCAM10001 (Omnivision OX03C10 camera + MAX96717 serializer, if your requirement is similar, you can develop based on this dts, you can find all of device tree files as below, find the chapter 7.3.10.3  https://www.nxp.com/docs/en/user-guide/UG10163.pdf

i.MX RT1176 – FlexIO2 并行接收：可实现的最大时钟移位是多少？仅达到约 48 MSPS iMXR1176 SDK 25.09.00 清单 3.15.0 目标 我正在从 i.MX RT1176 上的 LTC2164 16 位 ADC 获取数据。数据路径为： LTC2164（全速率CMOS输出）→ FlexIO2（并行接收）→ eDMA → 外部同步动态随机存取存储器(SDRAM) 硬件设置 LTC2164 配置为全速率 CMOS 输出模式，由外部 100 MHz 振荡器提供时钟信号（即 100 MSPS，16 位并行）。 ADC 数据输出 D0–D15 连接到 GPIO_AD_00 … GPIO_AD_15。 ADC CLKOUT+ 连接到 GPIO_AD_30，用作 FlexIO 定时器时钟（外部引脚时钟源）。 软件设置 FlexIO2 配置为并行接收器，数据锁存到移位器 7；移位器 7->0 串联起来，以便在 DMA 请求钳位之前缓冲 32 字节。 eDMA 由 kDmaRequestMuxFlexIO2Request0Request1 触发，使用两个 TCD 以乒乓（分散/聚集）模式运行。每次主循环完成时都会引发中断，即每 16384 个样本一次。 FlexIO2 功能时钟：120 MHz。 总线时钟（eDMA / SEMC 侧）：240 MHz。 问题 在 100 MSPS 下，采集 16384 个样本需要163.84 µs 。通过测量两个连续 DMA 中断之间的时间（GPIO 切换 + 示波器），我始终得到338 µs ，即 ~2.06 倍。 这相当于大约48 MSPS的有效持续速率，这表明瓶颈在于 FlexIO 端，而不是 ADC 或 SDRAM。 问题 RT1176 上 FlexIO 在并行接收模式下是否有记录在案的最大移位时钟频率？我在参考手册或数据表中都找不到这样的数据。 当定时器时钟源为外部引脚时，FlexIO 功能时钟与外部移位时钟之间所需的比率是多少？我的 FlexIO 时钟 (120 MHz) 只是输入 100 MHz 时钟的 1.2 倍——这足够吗？还是输入同步逻辑需要 2 倍或 4 倍？ 鉴于我观察到的几乎精确的 ×2 比率，这是否可能是由于 FlexIO 定时器在时钟的两个边沿递减（TIMCMP 约定）造成的，这意味着我的定时器比较值实际上将吞吐量减半？ 任何关于 FlexIO + eDMA 在此部分上的最大实际持续吞吐量的指导都将非常有帮助，因为这决定了我是否需要迁移到不同的外设或外部 FIFO。 先行致谢。 通信与控制（I3C | I2C | SPI | FlexCAN | 以太网 | FlexIO） Re: i.MX RT1176 – FlexIO2 parallel receive: maximum achievable shift clock? Only ~48 MSPS reached 您好，谢谢您的回复。我确实达到了预期的性能，但这仅仅是通过超过 Flexio 外设的最大推荐时钟频率来实现的；具体来说，要达到 100 MSps 的采集速率，需要将时钟频率配置为 200 MHz 以上，而不是 120 MHz，而 120 MHz 的配置会导致时钟边沿丢失。问题是，即使它在 200 MHz 下工作（尽管参考手册规定最大频率为 120 MHz），我也无法保证在不同的温度条件下或不同生产批次之间可靠运行。 Re: i.MX RT1176 – FlexIO2 parallel receive: maximum achievable shift clock? Only ~48 MSPS reached 你好@azed38 ， 请注意，当使用外部引脚作为时钟源时，会引入较小的同步延迟。根据 RM 第 67.3.3.2 节，此延迟范围为 0.5 至 1.5 个 FlexIO 时钟周期： Habib_MS_1-1788818202534.pngHabib_MS_1-1788818202534.pngHabib_MS_1-1788818202534.png 关于 FlexIO 和 DMA 可达到的最大吞吐量，目前还没有针对 FlexIO 和 DMA 的性能测试。不过，您可能会发现AN12686很有用，因为它演示了使用 FlexIO 和 DMA 的并行通信实现，这可能会为您的用例提供相关指导。 BR 哈比卜 Re: i.MX RT1176 – FlexIO2 parallel receive: maximum achievable shift clock? Only ~48 MSPS reached 你好@azed38 ， 我注意到您已经通过其他渠道获得了关于此主题的支持，因此我们将继续通过该渠道提供支持，以保持所有沟通的集中化。我只想补充一点，如果 FlexIO 的运行频率超过其最大规格，可能会导致意外行为，从而影响您的最终应用程序。根据 RM 表 15-4“时钟根”中提供的信息，我建议使用最大频率 120 MHz。 BR 哈比卜 Re: i.MX RT1176 – FlexIO2 parallel receive: maximum achievable shift clock? Only ~48 MSPS reached 您好， 这个问题很可能是由于第 67.3.3.2 节中描述的引脚同步延迟造成的。参考手册中的“引脚同步”部分。 考虑到前面提到的设置，问题的根本原因是输入数据频率与 FlexIO 上的工作时钟频率之间的比率，这是由于该模块前面提到的引脚同步延迟造成的。 例如，由于存在引脚同步延迟，FlexIO 模拟外设（如 SPI 主控）只能以 FlexIO 工作时钟频率的四分之一的最大波特率运行。如 RM 第 67.4.3 节所述：“由于同步延迟，串行输入数据的建立时间为 1.5 个 FlexIO 时钟周期，因此最大波特率除以 FlexIO 时钟频率的 4。” 在这种情况下，吞吐量预计会降低，而且由于引脚同步延迟是 FlexIO 模块固有的特性，因此没有解决办法。 因此，为了确保正常运行，FlexIO 模块的最大工作频率为 120MHz，RT1170 无法达到预期的 100MSPS。 BR 哈比卜

S32DS S32K358 Project Inquiry wj_kwak_0-1789777426372.pngwj_kwak_0-1789777426372.png I have a question about creating the S32K358 project. I am curious why two projects, M7_0 and M7_2, are being created. I want to know the function of the Inherit boot core toolchain button.. My teammate says that the reference documentation states M7_0 is the bootloader area and M7_2 is the application area, but I haven't been able to verify this in the documentation. I would like to confirm this. Re: S32DS S32K358 Project Inquiry Hi @wj_kwak  For S32K358, S32DS creates two independent projects by default, one for M7_0 and one for M7_2. These projects correspond to the two processing cores. They do not represent a bootloader area and an application area. The S32DS project creation wizard does not normally create a single project containing the application for both cores. If such a project structure is required, it has to be created/configured manually. However, in most cases there is no need to do this and the typical approach is to use two independent projects, one for each core. The "Inherit boot core toolchain" option can be used to inherit the toolchain configuration from the boot-core project when creating the project for the other core. If it is enabled, you can select the toolchain only for Cortex-M7_0_0. The toolchain selection for Cortex-M7_0_2 will be greyed-out because the configuration from the Cortex-M7_0_0 will apply. You can also refer to the multicore examples and documentation provided here: community.nxp.com/t5/S32K/S32K324-Multi-Core-Example-Project-based-on-Whiteboard/m-p/1547771 The package demonstrates both approaches: independent projects for each core and a single project for both cores compiled into a single ELF file. So, M7_0 and M7_2 should not be understood as bootloader and application projects. They are simply the projects associated with the respective cores. Best regards, Lukas

カメラモジュールの互換性OX05B1S センサーおよび内蔵ISPとi.MX95 FRDM対応 こんにちは、皆さん。 ox05b1sセンサーと内蔵ISPを搭載したカメラモジュール(NVIDIA Jetson AGX Orin用の5MP RGB-IR Global Shutter GMSL2カメラに似たもの)がi.MX95 FRDMボードに対応しているか知りたいです。 i.MX95はポートがMIPI_CSI2しかないので、GMSL2からMIPI_CSI2コンバータを探す必要があるのは理解していますが、私の質問はNXP Linux BSPに含まれる既存ドライバの互換性に関するものです。NXP Linuxリリースのドライバ カメラドライバーはこのカメラモジュールと直接動作しますか? dtbファイルに変更を加える必要はありますか？他に何か変更点や追加作業が必要で、計画しておくべきことはありますか？ Re: Compatibility of Camera module with OX05B1S Sensor and in-built ISP with i.MX95 FRDM これはあなたの似たテーマですか?これを参照してください。 https://community.nxp.com/t5/i-MX-Processors/OX05B1S-GMSL2-camera-with-MAX96717-MAX96724-on-i-MX95/td-p/2403429 これはIMX95カメラのポーティングガイドについての内容で、IMX95の基本的なポーティング手順を知るためにも参考にしてください https://docs.nxp.com/bundle/UG10215/page/topics/imx95_applications_processor_camera_software_archi.html また、7.3.10.3も参照できます。ユーザーガイドのカメラモジュール、現在IMX95に対応しています X-MX95MBDESER01(MAX96724デシリアライザー)+4モジュールX-MX95MBCAM10001(Omnivision OX03C10カメラ+MAX96717シリアライザー)。もし要件が似ているなら、このDTSを基に開発できます。以下のすべてのデバイスツリーファイルは見つかります。7.3.10.3章を参照してください。 https://www.nxp.com/docs/en/user-guide/UG10163.pdf Re: Compatibility of Camera module with OX05B1S Sensor and in-built ISP with i.MX95 FRDM こんにちは、 @sarve043swaray さん。 ご回答ありがとうございます。dtbファイルの修正方法や、シリアライザー/シリアライザー解除のi2cコマンドをどこに(ファイルやフォルダで)統合すればよいか、何かアドバイスをいただけますか? よろしくお願いします。 Re: Compatibility of Camera module with OX05B1S Sensor and in-built ISP with i.MX95 FRDM こんにちは、 カメラはi.MX95 BSPドライバとは直接接続できません。OX05B1Sセンサードライバーは再利用可能かもしれませんが、GMSL2のセットアップは統合が必要な別のレイヤーを追加します。SerDes構成(GMSL2ブリッジ、I2Cルーティング、GPIO、CSI-2リンク)にはDTBの変更が必要になる可能性が高く、GMSL2シリアライザー/デシリアライザーのドライバ改造も必要になるかもしれません。プラグアンドプレイのMaximタイムクロック構成ではないので、BSPのカスタマイズや検証作業を計画してください。

S32K3 FXOSC の問題 NXPのエキスパートの方、こんにちは。S32K3 FXOSCについて2つ質問があります。 1. S32K3のFXOSC水晶発振器に対する許容誤差要件は何ですか？データシートからこのデータを入手できません。 2. データシートによると、K3チップの内部FXOSCにはフィードバック抵抗がないと記載されています。そこで、内部に1MΩのフィードバック抵抗があるかどうか確認したいと思います。 Chenxu1_0-1777256809741.pngChenxu1_0-1777256809741.png ありがとう Re: S32K3 FXOSC问题 助けてくれてありがとう。 2つ目の質問についてですが、FXOSCに外部フィードバック抵抗を追加することを一般的に推奨しますか？「S32K344-WB-DESIGN-FILES」にはFXOSCに1MΩのフィードバック抵抗があると記載されていますが、「S32K3xx - Hardware Design Guidelines -- Rev_D」には記載されていません。 もう一つ質問があります。PLLロックアウトのしきい値についてです。±5、±9、±17、±33の単位は何ですか？1msタスク内で量子化した場合、それぞれ時間サイクルにどのような影響がありますか？VCOが960MHzのS32K312チップの場合です。 Chenxu1_0-1777275442814.pngChenxu1_0-1777275442814.png Re: S32K3 FXOSC问题 ハイ A1.これはお客様の最終的な用途によって異なると考えます。 例えば、アプリケーションで高精度のクロックが必要な場合は、低いPPM（1分あたりの回転数）が必要になります。 例えば、顧客がCAN通信を必要とする場合など。そして、CANのクロックソースとして、PLL（水晶発振器）によって生成されたAIPS_PLAT_CLKを選択します。 PLLはソースクロック（ここでは水晶発振器クロック）の精度を維持するため、PLLをCANプロトコルクロックとして使用しても問題ありません。PLLのジッターは多少の誤差を生じさせますが、一般的なCANビットタイミングにおける水晶発振器の精度と比較すると、その誤差はx倍小さくなります。 A2。S32K3のデータシートには、FXOSCには内部フィードバック抵抗があると記載されていますが、その値は明記されていません。 「安定した発振を確保するため、FXOSCはフィードバック抵抗を内部に組み込んでいます。」 よろしくお願いします、 ロビン ------------------------------------------------------------------------------- 注記： この投稿があなたの質問への回答になっている場合は、「解決策として承認」ボタンをクリックしてください。ありがとう！ - 最後の投稿から7週間はスレッドをフォローしますが、それ以降の返信は無視されます。 後日、関連する質問がある場合は、新しいスレッドを作成し、閉じられたスレッドを参照してください。 ------------------------------------------------------------------------------- Re: S32K3 FXOSC问题 「S32K344-WB-DESIGN-FILES」内のフィードバック抵抗R168はDNPとマークされているため、実際にははんだ付けされていません。 PLLCAL2[ULKCTL]に関する詳細情報については、AEチームに相談するまでお待ちください。 Re: S32K3 FXOSC问题 外部の1MΩ抵抗器を内部の帰還抵抗器と並列に接続することで、等価帰還抵抗を低減します。 帰還抵抗Rfはアンプのループゲインに影響を与え、Rfが低いほどループゲインは低下します。 これにより、特に低温/高温、低電圧、大きな水晶ESR、負荷容量の変動などの境界条件下では、発振マージンが低下する可能性があるため、起動時間、EXTAL/XTAL振幅、PLLロック、およびクロック安定性を検証する必要があります。 Re: S32K3 FXOSC问题 こんにちは、ロビン K3水晶発振器にはフィードバックバイアス抵抗が内蔵されていますが、水晶発振器の外部で1MΩの抵抗を入出力端子に並列接続した場合、何か影響はありますか？