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提供内容:S32DS用PFEプラグインの完全実装、LWIP統合、およびtcpip/LLCEの修正 NXPチームとS32Gコミュニティの皆様、こんにちは。 私はS32 Design Studio(S32DS)/S32設定ツール用の完全なPFEプラグインを開発しました。以前は、PFEの設定サポートはEB Tresosのみで利用可能でした。新しいプラグインには以下が含まれます。 S32DS環境内での完全なネイティブ統合 NXP公式tcpipプラグインとのシームレスな統合によるLWIPスタックサポート 完全なTSNトラフィックシェーパー構成(TASおよびCBS) LWIPおよびLLCEを用いた徹底的なテスト(オフロードシナリオを含む) その過程で、公式のtcpipおよびLLCEプラグインに存在するいくつかのバグも特定し、解決しました。 この強化により、S32Gプラットフォーム上で高度なイーサネットおよびTSNアプリケーションの開発がよりスムーズに可能となります。 プラグイン全体、統合コンポーネント、バグ修正、ドキュメント、テスト結果をNXPに提供したいと考えています。これは将来のRTDやS32構成ツールのリリースに統合されるか、コミュニティの公式参考資料として共有される可能性があります。 NXPチームへの質問: この貢献を正式に提出する際の推奨プロセス(例:技術サポートCASEやその他のチャネルを通じて)はどのようなものですか? ドキュメント、梱包、契約(NDAなど)に関して特別な要件はありますか? プラグインファイル、インストール・統合ガイド、詳細な変更履歴、検証結果を含む包括的なパッケージを用意しました。私は喜んでプライベートで共有し、技術的なレビューや議論もサポートします。 ご指導をよろしくお願いいたします。ご意見をお待ちしております。 よろしくお願いします、 アルサル・イマーム SDVアーキテクト @ GK Automobiltechnologie (Disrupt) ゴールドVIP Re: Offering Contribution: Complete PFE Plugin for S32DS, LWIP Integration & tcpip/LLCE Fixes こんにちは、アルサリマム まず、この素晴らしい成果を共有していただき、またNXPに貢献してくださる意思を示していただき、ありがとうございます。 あなたが説明した機能、例えばネイティブのS32 Design Studio統合、LWIP/tcpip連携、TSNトラフィックシェーピングサポート(TAS/CBS)、LLCE検証、関連するバグ修正などは、S32GイーサネットおよびTSN開発にとって非常に価値があるようです。 この段階では、既存のNXPツールへのソフトウェアコンポーネント、プラグイン、修正の提供は、関連製品およびソフトウェアチームによるレビューが必要です。受入プロセスには、技術的な評価だけでなく、知的財産権や法的側面に関する検討も含まれる場合がある。 カスタマーサポートシステムを通じて資料を共有することができます: https://support.nxp.com S32Gソフトウェアエコシステムの改善に尽力し、ご関心を持ってくださったことに感謝いたします。 BR ジョーイ
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S32DS许可证已过期。 您好,客服人员, 请帮忙延长已过期的许可证: FF6A-EDA4-CDF0-7186 。 此致, 马库斯 激活 | 安装 | 许可 | 安装程序下载 Re: S32DS License Expired. 我认为延长许可证是不可能的。或许你需要购买许可证。 Re: S32DS License Expired. 您好, 这是为 S32DS for ARM 2018.R1 准备的。请协助延长许可证期限。 此致, 马库斯 Re: S32DS License Expired. 嗨,马库斯, 您的S32DS许可证已延期。请使用您之前的激活码重新激活S32DS。 Re: S32DS License Expired. 谢谢你,Jiri!
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Yocto wrynose build failure for 'imx-car-navigation' Hi, trying to build 'imx-image-full' for an FRDM-IMX93 on the latest 6.18.20-2.0.0 BSP fails like this: ERROR: imx-car-navigation-1.0-r0 do_compile: Execution of '/media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/build-imx93-frdm/tmp/work/armv8-2a-poky-linux/imx-car-navigation/1.0/temp/run.do_compile.1753043' failed with exit code 1 ERROR: Logfile of failure stored in: /media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/build-imx93-frdm/tmp/work/armv8-2a-poky-linux/imx-car-navigation/1.0/temp/log.do_compile.1753043 Log data follows: | DEBUG: Executing shell function do_compile | Cloning into '/media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/build-imx93-frdm/tmp/work/armv8-2a-poky-linux/imx-car-navigation/1.0/sources/imx-car-navigation-1.0/CANopenNode'... | fatal: unable to access 'https://github.com/CANopenNode/CANopenNode.git/': Could not resolve host: github.com | fatal: clone of 'https://github.com/CANopenNode/CANopenNode.git' into submodule path '/media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/build-imx93-frdm/tmp/work/armv8-2a-poky-linux/imx-car-navigation/1.0/sources/imx-car-navigation-1.0/CANopenNode' failed | Failed to clone 'CANopenNode'. Retry scheduled | Cloning into '/media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/build-imx93-frdm/tmp/work/armv8-2a-poky-linux/imx-car-navigation/1.0/sources/imx-car-navigation-1.0/CANopenNode'... | fatal: unable to access 'https://github.com/CANopenNode/CANopenNode.git/': Could not resolve host: github.com | fatal: clone of 'https://github.com/CANopenNode/CANopenNode.git' into submodule path '/media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/build-imx93-frdm/tmp/work/armv8-2a-poky-linux/imx-car-navigation/1.0/sources/imx-car-navigation-1.0/CANopenNode' failed | Failed to clone 'CANopenNode' a second time, aborting | WARNING: exit code 1 from a shell command. ERROR: Task (/media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/sources/meta-nxp-demo-experience/recipes-examples/imx-car-navigation/imx-car-navigation.bb:do_compile) failed with exit code '1' Note that this is 100% reproducible - it always fails here.  Please also note that a download of a repository fails, even though bitbake is executing a "compile" step.  Currently, I think it may be related that downloads should not be done in compilation steps and maybe bitbake now limits network functionality to the download step?  Did anyone test this recipe recently? Re: Yocto wrynose build failure for 'imx-car-navigation' It seems my gut feeling was right.  The following patch solves the problem for me: --- sources/meta-nxp-demo-experience/recipes-examples/imx-car-navigation/imx-car-navigation.bb.ORIG 2026-07-13 16:02:28.733344421 +0200 +++ sources/meta-nxp-demo-experience/recipes-examples/imx-car-navigation/imx-car-navigation.bb 2026-07-13 16:02:11.178539144 +0200 @@ -14,6 +14,7 @@ do_configure[noexec] = "1" +do_compile[network] = "1" do_compile() { cd ${S} But note that this is just a workaround.  There is a reason why this is not allowed by default - the compile step should not do any network access.
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New Project Wizard fAiL: no freeRTOS port added automatically Hello all, I'm trying to create a freeRTOS based project for LPC5536 using MCUXpresso IDE V24.12. The "Create a new C/C++ project" wizard (available from Quickstart Panel) seems to offer a simple means to add freeRTOS support to a project (see markup in screenshot below): danielholala_0-1750771156912.png As you can see, the "New Project Wizard" offers a checkbox to add freeRTOS as "operating system". When checking this box, the wizard automatically adds another crucial part of freeRTOS, the memory manager (see marked checkboxes below): danielholala_1-1750771498221.png However, the wizard fails to add the most important part of freeRTOS, the MCU-specific  code (see markup in screenshot below): danielholala_2-1750771652430.png If you don't select this component by yourself, the generated project throws compilation errors. I believe that the New Project Wizard should always result in a compilable project. Further the MCUXpresso IDE manual clearly states:"Also, selecting a component automatically selects any dependencies." (section 5.1.1. SDK New Project WIzard). In my opinion, this is a bug, at least a UX bug.  I'd like to see this fixed in the next SDK / MCUXpresso version. Thanks. Daniel Re: New Project Wizard fAiL: no freeRTOS port added automatically Tried it with MCUXpresso IDE v25.6 (current as of writing) with SDK for LPC5536 (version 25.06, manifest 3.15) and the dependency between FreeRTOS kernel and the cm33 port is still missing and needs to be selected manually.  Re: New Project Wizard fAiL: no freeRTOS port added automatically Hello @EdwinHz , I appreciate your prompt support. Thank you. Daniel Re: New Project Wizard fAiL: no freeRTOS port added automatically Hi @danielholala, I was able to replicate this issue, and it is definitely a bug, since the project wizard should automatically select all of the dependencies. I will report this issue to the IDE team so they can correct it in a future version of MCUXpresso's project wizard. Thanks for reporting this issue. BR, Edwin.
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Connectivity issue in SJA1110 Dear NXP members, This ticket may be related to the following topics: SJA-1110-Configuration-of-Qbv  SJA1110-Qbv-AdminBaseTime-Configuration  During the configuration of Qbv on the SJA1110 switch present in the S32G-VNP-RDB3 board, I have been using the SJA1110 SDK for S32G from NXP for setting the gPTP/Qbv parameters, compiling the new sja1110_uc.bin file, and deploying it on the firmware folder of the A-core Linux BSP. Initially, I have been using the PFE0 interface (SJA1110 switch Port 4) as the gPTP grandmaster, with ADMINBASETIME set to 0. I performed some tests and validations and everything indicates that it behaves as expected. However, during the course of the project, I had to reassign the roles so that now the gPTP grandmaster would come from an external device which is connected to the Port 3. From the moment I would connect this external device, the Qbv performance would behave quite erratically. I did some tests starting with large cycle values, for instance: Cycle = 1 sec -> 125000000 CycleExt (12.5%) = 15625000 segment 1 = 0.25 sec TCs 0 and 1 GATESTATUS 1 and 0 segment 2 = 0.25 sec TCs 2 and 3 GATESTATUS 6 and 7 segment 3 = 0.25 sec TCs 4 and 5 GATESTATUS 2 and 3 segment 4 = 0.25 sec TCs 6 and 7 GATESTATUS 4 and 5 port 3: TRIGGER_TIME = 1250000 (2x625000) port 4: TRIGGER_TIME = 3125000 (4x781250) ports 5...: TRIGGER_TIME = 125000 For testing, I send UDP packets from the client (S32G PFE0 interface) to another Linux device connected on the same network acting as server. I capture the packets using the tcpdump tool on the server side, and analyze the results. In this case, the transmission would start after a few seconds, but once started, it would behave correctly (1 second cycle, 25% for the given traffic priority): Screenshot 2026-07-08 084413.png  Then, I used the GATESTATUS division into four segments, but reduced the cycle time to 200 ms: Cycle = 200ms -> 25000000 CycleExt = 3125000 segment 1 = 50 ms TCs 0 and 1 GATESTATUS 1 and 0 segment 2 = 50 ms TCs 2 and 3 GATESTATUS 6 and 7 segment 3 = 50 ms TCs 4 and 5 GATESTATUS 2 and 3 segment 4 = 50 ms TCs 6 and 7 GATESTATUS 4 and 5 port 3: TRIGGER_TIME = 250000 port 4: TRIGGER_TIME = 625000 ports 5...: TRIGGER_TIME = 25000 It would work, but I needed to start between 30 seconds and 2 minutes for the transmission of the packets start. Screenshot 2026-07-08 085025.png   In the subsequent tests, I observed the same pattern: When the cycle time was reduced to 100 ms, I would have to wait between 2 and 4 minutes before transmission started; When the cycle time was reduced to 50 ms, I would have to wait between 5 and 6 minutes before transmission started. And so on. So, the shorter the cycle length, the larger the wait time before Qbv effectively started. Until then, the traffic was blocked. But there is another weird behavior observed when I did the following configuration: Cycle = 0.5 ms -> 62500 CycleExt = 7812 segment 1 = 30 μsec TCs 0, 1, 2, 4, 5, and 7: GATESTATUS 0, 1, 2, 3, 5, 6, and 7 segment 2 = 300 μsec TC 6: GATESTATUS 4 segment 3 = 170 μsec TCs 0, 1, 2, 4, 5, and 7: GATESTATUS 0, 1, 2, 3, 5, 6, and 7 In this case, all of the traffic would pass except TC6. When I invert the configuration: Cycle = 0.5 ms -> 62500 CycleExt = 7812 segment 1 = 30 μsec TC 6: GATESTATUS 4 segment 2 = 170 μsec TCs 0, 1, 2, 4, 5, and 7: GATESTATUS 0, 1, 2, 3, 5, 6, and 7 segment 3 = 300 μsec TC 6: GATESTATUS 4 in this case, only the TC6 traffic would be transmitted while the other TCs would be blocked. From my opinion, it points in the direction of the time synchronization issue. Here is how I have configured gPTP on the S32DS: Screenshot 2026-07-08 090805.png   Screenshot 2026-07-08 091033.png   It is also worth mentioning that this external gPTP Grandmaster provides Sync timestamps based on the current Unix epoch:   Screenshot 2026-07-01 110153.png While when the PFE0 was used as the Grandmaster, it would provide Sync timestamps starting with 0: Screenshot 2026-07-08 091440.png   What would explain this behavior? Thank you for your support! Best regards, Guilherme Re: Connectivity issue in SJA1110 Hello @GuilhermeS32G , Yes, please wait to get access. Besides NDA, Automotive Ethernet belongs to export control policy. In my opinion, the ECT tool is a great source of code related to switch's dynamic reconfiguration. Yes, split the Unix epoch gPTP timestamp into ADMINBASETIME[0:31] and ADMINBASETIME[32:63] is the right way. Best regards, Pavel Re: Connectivity issue in SJA1110 Hi @PavelL , Thank you for your response. Indeed, this ECT tool seems to be the right way to go. However, I still have no access for downloading it. It says: "SJA11XX Standard Software - Your Request form has been received". I may need to wait for some time to see if I can get access. In the meanwhile, just to clarify, let's say the current Unix epoch (with nanoseconds) is: 1784013205012345678 Which represents, in UTC: Tuesday, July 14, 2026 at 7:13:25 AM What is the correct way to split this timestamp into ADMINBASETIME[0:31] and ADMINBASETIME[32:63]? Best regards, Guilherme Re: Connectivity issue in SJA1110 Hello @GuilhermeS32G , Thank you for creating a follow up thread - it help us to keep clarity on cases. Thank you for sharing all the details and test results at once. I checked provided data and your gPTP configuration appears to be correct.   Based on your observations, the behavior strongly suggests that the issue is related to the Qbv schedule activation time rather than to the gate list entries themselves. If the ADMINBASETIME being configured as 0 while the external gPTP Grandmaster provides an epoch-based PTP time value, ADMINBASETIME = 0 is far in the past relative to the current synchronized gPTP time domain and the switch needs to resolve the Qbv change/start time based on that value. This may lead to unexpected schedule activation behavior compared with a setup where the PTP time starts close to zero, and it is therefore safer to program ADMINBASETIME as a future value in the currently synchronized PTP time domain.   Therefore, for this use case, I would recommend configuring ADMINBASETIME dynamically based on the current synchronized PTP/gPTP time (and still using a fixed value of 0 in the static configuration). A typical sequence would be: 1. Start gPTP and wait until the switch is synchronized to the external Grandmaster. 2. Read the current PTP clock from the switch. 3. Set ADMINBASETIME to a future time value, for example current PTP time + sufficient safety margin. 4. Write the TAS/Qbv administrative parameters. 5. Trigger the TAS/Qbv configuration change. You may use the ECT server implementation as a reference. In particular, please check file udp_traffic.c ; routine udpReceiveCallback() . It doesn't matter if you use SDK or RTD version of ECT server. PavelL_0-1783939380327.png In the TAS configuration handling, the ECT server (SDK version) reads the current PTP time using SWITCH_DRV_GetPtpClk(), assigns this value to the TAS baseTime, adds a margin of 2 seconds, and then calls SWITCH_DRV_WriteTasAdminParameters() followed by SWITCH_DRV_ChangeTasConfig().   This approach avoids using ADMINBASETIME = 0 and aligns the Qbv schedule activation with the actual synchronized PTP time domain. Best regards, Pavel
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S32DS License Expired. Hi Support, Please help extend the license: FF6A-EDA4-CDF0-7186 that has expired. Regards, Marcus Activation | Installation | Licensing | Installer Download Re: S32DS License Expired. I don't think extend the license is possible. Maybe you need to purchase the license Re: S32DS License Expired. Hi Marcus,  your S32DS license has been extended. Please activate S32DS again with your old code.  Re: S32DS License Expired. Hi, This is meant for S32DS for ARM 2018.R1.  Please assist to extend the license. Regards, Marcus Re: S32DS License Expired. Thank you Jiri !
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SJA1110のコネクティビティ問題 NXPメンバーの皆様へ このチケットは以下のトピックに関連する場合があります: SJA-1110-Qbvの構成 SJA1110-Qbv-AdminBaseTime-Configuration S32G-VNP-RDB3ボードにあるSJA1110スイッチでQbvの設定中、NXPのS32GのSJA1110 SDKを使ってgPTP/Qbvパラメータの設定、新しい sja1110_uc.bin ファイルのコンパイル、そしてAコアLinux BSPのファームウェアフォルダにデプロイしています。 最初は、PFE0インターフェース(SJA1110スイッチポート4)をgPTPグランドマスターとして使い、ADMINBASETIMEを0に設定していました。いくつかのテストや検証を行いましたが、すべて期待通りに動作しています。 しかし、プロジェクトの進行中に役割を再割り当てし、gPTPグランドマスターはポート3に接続された外部デバイスから出力されるようになりました。 この外部デバイスを接続した瞬間から、Qbvのパフォーマンスが非常に不安定になった。 例えば、大きなサイクル値から始めていくつかのテストを行いました。 Cycle = 1 sec -> 125000000 CycleExt (12.5%) = 15625000 segment 1 = 0.25 sec TCs 0 and 1 GATESTATUS 1 and 0 segment 2 = 0.25 sec TCs 2 and 3 GATESTATUS 6 and 7 segment 3 = 0.25 sec TCs 4 and 5 GATESTATUS 2 and 3 segment 4 = 0.25 sec TCs 6 and 7 GATESTATUS 4 and 5 port 3: TRIGGER_TIME = 1250000 (2x625000) port 4: TRIGGER_TIME = 3125000 (4x781250) ports 5...: TRIGGER_TIME = 125000 テストのために、クライアント(S32G PFE0インターフェース)から同じネットワークにコネクテッドされた別のLinuxデバイスへUDPパケットを送信しています。 サーバー側でtcpdumpツールを使用してパケットをキャプチャし、結果を分析します。 この場合、送信は数秒後に開始されますが、一度開始すると正しく振る舞います(1秒サイクル、指定されたトラフィック優先度の25%)。 Screenshot 2026-07-08 084413.png 次に、GATESTATUSを4つのセグメントに分割しましたが、サイクルタイムを200msに短縮しました。 Cycle = 200ms -> 25000000 CycleExt = 3125000 segment 1 = 50 ms TCs 0 and 1 GATESTATUS 1 and 0 segment 2 = 50 ms TCs 2 and 3 GATESTATUS 6 and 7 segment 3 = 50 ms TCs 4 and 5 GATESTATUS 2 and 3 segment 4 = 50 ms TCs 6 and 7 GATESTATUS 4 and 5 port 3: TRIGGER_TIME = 250000 port 4: TRIGGER_TIME = 625000 ports 5...: TRIGGER_TIME = 25000 うまくいくはずだったが、パケットの送信開始まで30秒から2分の間に開始する必要があった。 Screenshot 2026-07-08 085025.png   その後のテストでも、同じパターンが観察された。 サイクルタイムを100ミリ秒に短縮すると、送信が開始されるまでに2分から4分待たなければなりませんでした。 サイクルタイムが50ミリ秒に短縮された場合、送信が開始されるまでに5分から6分待たなければなりませんでした。 などなど。したがって、 サイクルの長さが短いほど、Qbvが実質的に始まるまでの待ち時間が長くなります。それまで、交通は遮断されていた。 しかし、以下の設定を行った際に、別の奇妙な動作が観察されました。 Cycle = 0.5 ms -> 62500 CycleExt = 7812 segment 1 = 30 μsec TCs 0, 1, 2, 4, 5, and 7: GATESTATUS 0, 1, 2, 3, 5, 6, and 7 segment 2 = 300 μsec TC 6: GATESTATUS 4 segment 3 = 170 μsec TCs 0, 1, 2, 4, 5, and 7: GATESTATUS 0, 1, 2, 3, 5, 6, and 7 この場合、TC6以外のすべてのトラフィックは通過します。 設定を反転すると: Cycle = 0.5 ms -> 62500 CycleExt = 7812 segment 1 = 30 μsec TC 6: GATESTATUS 4 segment 2 = 170 μsec TCs 0, 1, 2, 4, 5, and 7: GATESTATUS 0, 1, 2, 3, 5, 6, and 7 segment 3 = 300 μsec TC 6: GATESTATUS 4 この場合、TC6のトラフィックのみが送信され、他のTCはブロックされます。 私の見解では、これは時刻同期の問題を示唆している。 S32DSでgPTPを設定した方法を以下に示します。 Screenshot 2026-07-08 090805.png   Screenshot 2026-07-08 091033.png   また、この外部gPTPグランドマスターは、現在のUnixエポックに基づいた同期タイムスタンプを提供する点も特筆すべきである。   Screenshot 2026-07-01 110153.png PFE0がグランドマスターとして使用された場合、同期タイムスタンプは0から始まる。 Screenshot 2026-07-08 091440.png   この行動を説明できるものは何だろうか? サポートありがとうございます! よろしくお願いいたします。 ギレルメ Re: Connectivity issue in SJA1110 こんにちは、 @GuilhermeS32G さん、 はい、アクセスを待ってください。NDAに加えて、自動車用イーサネットは輸出管理政策に属しています。 私の意見では、ECTツールはスイッチの動的再構成に関連する優れたコードソースです。 はい、UnixエポックgPTPタイムスタンプをADMINBASETIME[0:31]とADMINBASETIME[32:63]に分割するのが正しい方法です。 よろしくお願いいたします。 パベル Re: Connectivity issue in SJA1110 こんにちは、 @PavelL さん。 ご返信ありがとうございます。 確かに、このECTツールは正しい方向性のように思えます。 しかし、まだダウンロードのアクセス権はありません。そこには「標準ソフトウェアSJA11XX - リクエストフォームが受領されました」と表示されます。アクセスできるかどうか、しばらく待つ必要があるかもしれません。 念のため、現在のUnixエポック(ナノ秒単位)を以下のように定義します。 1784013205012345678 これはUTCで表すと次のようになります。 2026年7月14日(火)午前7時13分25秒 このタイムスタンプをADMINBASETIME[0:31]とADMINBASETIME[32:63]に分割する正しい方法は何ですか? よろしくお願いいたします。 ギレルメ Re: Connectivity issue in SJA1110 こんにちは、 @GuilhermeS32G さん、 フォローアップスレッドを作ってくださりありがとうございます。CASEの明確さを保つ助けになりました。 詳細情報と検査結果を一度に共有していただき、ありがとうございます。 ご提供いただいたデータを確認したところ、gPTPの設定は正しいようです。   あなたの観察から判断すると、この挙動はゲートリストのエントリ自体よりもQbvのスケジュール有効化時間に関連していることを強く示唆しています。 ADMINBASETIMEが0に設定されている一方で、外部gPTPグランドマスターがエポックベースのPTP時間値を提供する場合、ADMINBASETIME = 0は現在の同期gPTP時間領域に比べてかなり過去のことであり、スイッチはその値に基づいてQbvの変更/開始時間を解決する必要があります。これにより、PTP時間がほぼゼロから始まるセットアップと比べて予期しないスケジュール起動動作が生じる可能性があるため、現在同期されたPTP時間領域においてADMINBASETIMEを将来の価値としてプログラムする方が安全です。   したがって、このユースケースでは、現在の同期PTP/gPTP時間に基づいて動的にADMINBASETIMEを設定することをおすすめします(静的設定では固定値の0を使い続けます)。 典型的な手順は次のとおりです。 1. gPTPを起動し、スイッチが外部グランドマスターと同期するまで待ちます。 2. スイッチから現在のPTPクロックを読み取る。 3. ADMINBASETIMEを将来の時間値に設定します。例えば、現在のPTP時間+十分なセーフティマージン。 4. TAS/Qbvの管理パラメータを記述します。 5. TAS/Qbvの設定変更をトリガーします。 ECTサーバーの実装を参考にしても構いません。特に、ファイルudp_traffic.cを確認してください; routine udpReceiveCallback() .SDK版でもRTD版でも、ECTサーバーのどちらを使っても関係ありません。 PavelL_0-1783939380327.png TASの設定処理では、ECTサーバー(SDKバージョン)が現在のPTP時間をSWITCH_DRV_GetPtpClk()で読み取り、この値をTASのbaseTimeに割り当て、2秒の余裕を加えてからSWITCH_DRV_WriteTasAdminParameters()を呼び出し、続いてSWITCH_DRV_ChangeTasConfig()。   このアプローチでは、ADMINBASETIME = 0 の使用を回避し、Qbv スケジュールの有効化を実際の同期された PTP タイムドメインに合わせます。 よろしくお願いいたします。 パベル
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S32K144EVB-Q100 Rev D 原理图 你好。我正在寻找S32K144EVB-Q100 Rev D的原理图。我似乎无法让该板发送任何CAN消息。是否有可用于在该板上通过 CAN 0 发送消息的示例代码?我使用 SPI 确认了 CAN 收发器处于强制正常模式,因此 CAN 应该可以正常工作。 Re: S32K144EVB-Q100 Rev D Schematic 您可以查看 S32DS 中针对S32K144EVB 的示例代码……如果您有相关代码,请分享一下,因为我找不到…… Re: S32K144EVB-Q100 Rev D Schematic 你好@db16122 , 如果您还需要 S32K144EVB Rev. D 的设计文件,请告诉我。 此致, 朱利安 Re: S32K144EVB-Q100 Rev D Schematic 你好@rosejp03 , 关于设计文件,我已经通过社区私信联系你了。 关于 CAN 功能,Rev. C(我目前使用的电路板)和 Rev. D 具有完全相同的 CAN 设计和收发器 (UJA1169): S32K144EVB-Q100 Rev. DS32K144EVB-Q100 修订版 D S32K144EVB Rev. C1S32K144EVB 修订版 C1 你使用的是现有示例吗?是AN5413: S32K1xx 系列食谱,还是 RTD 软件包中包含的食谱? 你使用的是12V电源插孔吗?将J107 位置改为 1-2,并用 12V 电源为电路板供电。 你们是如何测试CAN通信的?您使用的是其他 EVB、CAN 分析仪还是其他设备?你能尝试用示波器探测一下总线吗? 此致, 朱利安
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SJA1110 的连接问题 尊敬的恩智浦半导体成员们: 此工单可能与以下主题相关: SJA-1110-Qbv配置 SJA1110-Qbv-AdminBaseTime-Configuration 在配置 S32G-VNP-RDB3 板上的 SJA1110 交换机的 Qbv 时,我一直使用 NXP 的 S32G SJA1110 SDK 来设置 gPTP/Qbv 参数,编译新的sja1110_uc.bin文件,并将其部署到 A-core Linux 电路板支持包 的固件文件夹中。 最初,我使用 PFE0 接口(SJA1110 交换机端口 4)作为 gPTP 主服务器,并将 ADMINBASETIME 设置为 0。我进行了一些测试和验证,一切迹象都表明它的行为符合预期。 然而,在项目进行过程中,我不得不重新分配角色,以便现在 gPTP 主控节点将来自连接到端口 3 的外部设备。 从我连接这个外部设备的那一刻起,Qbv 的性能就会变得非常不稳定。 我进行了一些测试,例如从较大的循环值开始: Cycle = 1 sec -> 125000000 CycleExt (12.5%) = 15625000 segment 1 = 0.25 sec TCs 0 and 1 GATESTATUS 1 and 0 segment 2 = 0.25 sec TCs 2 and 3 GATESTATUS 6 and 7 segment 3 = 0.25 sec TCs 4 and 5 GATESTATUS 2 and 3 segment 4 = 0.25 sec TCs 6 and 7 GATESTATUS 4 and 5 port 3: TRIGGER_TIME = 1250000 (2x625000) port 4: TRIGGER_TIME = 3125000 (4x781250) ports 5...: TRIGGER_TIME = 125000 为了进行测试,我从客户端(S32G PFE0 接口)向连接在同一网络上的另一个 Linux 设备(作为服务器)发送 UDP 数据包。 我在服务器端使用 tcpdump 工具捕获数据包,并分析结果。 在这种情况下,传输会在几秒钟后开始,但一旦开始,它就会正常工作(1 秒周期,给定流量优先级的 25%): Screenshot 2026-07-08 084413.png 然后,我将 GATESTATUS 分成四个段,但将周期时间缩短至 200 毫秒: Cycle = 200ms -> 25000000 CycleExt = 3125000 segment 1 = 50 ms TCs 0 and 1 GATESTATUS 1 and 0 segment 2 = 50 ms TCs 2 and 3 GATESTATUS 6 and 7 segment 3 = 50 ms TCs 4 and 5 GATESTATUS 2 and 3 segment 4 = 50 ms TCs 6 and 7 GATESTATUS 4 and 5 port 3: TRIGGER_TIME = 250000 port 4: TRIGGER_TIME = 625000 ports 5...: TRIGGER_TIME = 25000 这样做是可行的,但我需要等待 30 秒到 2 分钟才能开始传输数据包。 Screenshot 2026-07-08 085025.png   在随后的测试中,我观察到了同样的模式: 当循环时间缩短至 100 毫秒时,我需要等待 2 到 4 分钟才能开始传输; 当循环时间缩短到 50 毫秒时,我需要等待 5 到 6 分钟才能开始传输。 等等。因此,周期长度越短,Qbv 实际开始前的等待时间就越长。在此之前,交通一直处于阻塞状态。 但是,当我进行以下配置时,观察到了另一种奇怪的现象: Cycle = 0.5 ms -> 62500 CycleExt = 7812 segment 1 = 30 μsec TCs 0, 1, 2, 4, 5, and 7: GATESTATUS 0, 1, 2, 3, 5, 6, and 7 segment 2 = 300 μsec TC 6: GATESTATUS 4 segment 3 = 170 μsec TCs 0, 1, 2, 4, 5, and 7: GATESTATUS 0, 1, 2, 3, 5, 6, and 7 在这种情况下,除了TC6之外,所有交通流量都将通过。 当我反转配置时: Cycle = 0.5 ms -> 62500 CycleExt = 7812 segment 1 = 30 μsec TC 6: GATESTATUS 4 segment 2 = 170 μsec TCs 0, 1, 2, 4, 5, and 7: GATESTATUS 0, 1, 2, 3, 5, 6, and 7 segment 3 = 300 μsec TC 6: GATESTATUS 4 在这种情况下,只有 TC6 的流量会被传输,而其他 TC 的流量将被阻止。 我认为,这指向了时间同步问题。 以下是我在S32DS上配置gPTP的方法: Screenshot 2026-07-08 090805.png   Screenshot 2026-07-08 091033.png   值得一提的是,这个外部 gPTP 主服务器提供的同步时间戳基于当前的 Unix 纪元:   Screenshot 2026-07-01 110153.png 当 PFE0 用作主控时,它会提供从 0 开始的同步时间戳: Screenshot 2026-07-08 091440.png   这种行为该如何解释? 感谢您的支持! 顺祝商祺! 吉列尔梅 Re: Connectivity issue in SJA1110 你好@GuilhermeS32G , 是的,请稍候,您将获得访问权限。除了保密协议外,汽车以太网还属于出口管制政策的范畴。 我认为,ECT 工具是交换机动态重配置相关代码的绝佳来源。 是的,将 Unix epoch gPTP时间戳拆分为 ADMINBASETIME[0:31] 和 ADMINBASETIME[32:63] 是正确的方法。 顺祝商祺! 帕维尔 Re: Connectivity issue in SJA1110 嗨@PavelL , 感谢您的反馈, 确实,这种ECT工具似乎是正确的选择。 但是,我仍然无法下载它。上面写着:“SJA11XX 标准软件 - 您的申请表已收到”。我可能需要等待一段时间才能获得访问权限。 同时,为了更清楚地说明,我们假设当前的 Unix 时间戳(精确到纳秒)是: 1784013205012345678 这在世界协调时 (UTC) 代表: 2026年7月14日星期二上午7:13:25 如何正确地将此时间戳拆分为 ADMINBASETIME[0:31] 和 ADMINBASETIME[32:63]? 顺祝商祺! 吉列尔梅 Re: Connectivity issue in SJA1110 你好@GuilhermeS32G , 感谢您创建后续讨论帖——这有助于我们了解案件的最新进展。 感谢您一次性分享所有细节和测试结果。 我已检查所提供的数据,您的 gPTP 配置似乎是正确的。   根据您的观察,该行为强烈表明问题与 Qbv 调度激活时间有关,而非门控列表条目本身。如果外部 gPTP 主时钟提供基于纪元的 PTP 时间值,而 ADMINBASETIME 配置为 0,则 ADMINBASETIME = 0 相对于当前同步的 gPTP 时域而言非常遥远,交换机需要基于该值解析 Qbv 更改/启动时间。与 PTP 时间接近零的设置相比,这可能会导致意外的调度激活行为。因此,将 ADMINBASETIME 设置为当前同步的 PTP 时域中的未来值更为安全。   因此,对于此用例,我建议根据当前同步的 PTP/gPTP 时间动态配置 ADMINBASETIME(并在静态配置中仍然使用固定值 0)。 典型的序列如下: 1. 启动 gPTP 并等待交换机与外部主控交换机同步。 2. 从交换机读取当前的 PTP 时钟。 3. 将 ADMINBASETIME 设置为未来的时间值,例如当前 PTP 时间 + 足够的安全裕度。 4. 编写 TAS/Qbv 管理参数。 5. 触发 TAS/Qbv 配置更改。 您可以参考 ECT 服务器的实现。特别是请查看udp_traffic.c文件中的 udpReceiveCallback() 函数。无论您使用的是 ECT 服务器的 SDK 版本还是 RTD 版本,都无关紧要。 PavelL_0-1783939380327.png 在 TAS 配置处理中,ECT 服务器(SDK 版本)使用 SWITCH_DRV_GetPtpClk() 读取当前 PTP 时间,将此值赋给 TAS 基准时间,加上 2 秒的裕量,然后调用 SWITCH_DRV_WriteTasAdminParameters(),再调用 SWITCH_DRV_ChangeTasConfig()。   这种方法避免使用 ADMINBASETIME = 0,并将 Qbv 调度激活与实际同步的 PTP 时间域对齐。 顺祝商祺! 帕维尔
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Yoctoのリリーノーズビルド失敗 imx-car-navigation こんにちは、 最新の6.18.20-2.0.0 BSP上でFRDM-IMX93用の「imx-image-full」をビルドしようとすると、次のように失敗します。 ERROR: imx-car-navigation-1.0-r0 do_compile: Execution of '/media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/build-imx93-frdm/tmp/work/armv8-2a-poky-linux/imx-car-navigation/1.0/temp/run.do_compile.1753043' failed with exit code 1 ERROR: Logfile of failure stored in: /media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/build-imx93-frdm/tmp/work/armv8-2a-poky-linux/imx-car-navigation/1.0/temp/log.do_compile.1753043 Log data follows: | DEBUG: Executing shell function do_compile | Cloning into '/media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/build-imx93-frdm/tmp/work/armv8-2a-poky-linux/imx-car-navigation/1.0/sources/imx-car-navigation-1.0/CANopenNode'... | fatal: unable to access 'https://github.com/CANopenNode/CANopenNode.git/': Could not resolve host: github.com | fatal: clone of 'https://github.com/CANopenNode/CANopenNode.git' into submodule path '/media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/build-imx93-frdm/tmp/work/armv8-2a-poky-linux/imx-car-navigation/1.0/sources/imx-car-navigation-1.0/CANopenNode' failed | Failed to clone 'CANopenNode'. Retry scheduled | Cloning into '/media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/build-imx93-frdm/tmp/work/armv8-2a-poky-linux/imx-car-navigation/1.0/sources/imx-car-navigation-1.0/CANopenNode'... | fatal: unable to access 'https://github.com/CANopenNode/CANopenNode.git/': Could not resolve host: github.com | fatal: clone of 'https://github.com/CANopenNode/CANopenNode.git' into submodule path '/media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/build-imx93-frdm/tmp/work/armv8-2a-poky-linux/imx-car-navigation/1.0/sources/imx-car-navigation-1.0/CANopenNode' failed | Failed to clone 'CANopenNode' a second time, aborting | WARNING: exit code 1 from a shell command. ERROR: Task (/media/dzu/hd01-xfs/nxp/imx-yocto-6.18.20-2.0.0/sources/meta-nxp-demo-experience/recipes-examples/imx-car-navigation/imx-car-navigation.bb:do_compile) failed with exit code '1' これは100%再現可能であり、必ずここで失敗します。また、bitbakeが「コンパイル」ステップを実行しているにもかかわらず、リポジトリのダウンロードが失敗する点にもご注意ください。現状では、コンパイルの段階でダウンロードを行うべきではないことと、Bitbakeがネットワーク機能をダウンロード段階に限定していることが関係しているのではないかと考えています。最近このレシピを試した人はいますか? Re: Yocto wrynose build failure for 'imx-car-navigation' 私の直感は正しかったようだ。以下のパッチを適用することで、私の場合は問題が解決しました。 --- sources/meta-nxp-demo-experience/recipes-examples/imx-car-navigation/imx-car-navigation.bb.ORIG 2026-07-13 16:02:28.733344421 +0200 +++ sources/meta-nxp-demo-experience/recipes-examples/imx-car-navigation/imx-car-navigation.bb 2026-07-13 16:02:11.178539144 +0200 @@ -14,6 +14,7 @@ do_configure[noexec] = "1" +do_compile[network] = "1" do_compile() { cd ${S} ただし、これはあくまで一時的な回避策であることに注意してください。これがデフォルトで許可されていない理由があります。コンパイルステップはネットワークアクセスを行わないはずです。
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新建项目向导失败:未自动添加 FreeRTOS 端口 大家好, 我正在尝试使用 MCUXpresso IDE V24.12 为 LPC5536 创建一个基于 freeRTOS 的项目。 “创建新的 C/C++ 项目”向导(可从快速入门面板获取)似乎提供了一种简单的方法,可以将 freeRTOS 支持添加到项目中(请参见下方屏幕截图中的标记): danielholala_0-1750771156912.png 如您所见,“新建项目向导”提供了一个复选框,用于添加 freeRTOS 作为“操作系统”。选中此复选框后,向导会自动添加 freeRTOS 的另一个关键部分——内存管理器(请参见下方标记的复选框): danielholala_1-1750771498221.png 然而,该向导未能添加freeRTOS 中最重要的部分,即 MCU 特定的代码(请参见下方屏幕截图中的标记): danielholala_2-1750771652430.png 如果您不自行选择此元器件,则生成的项目会抛出编译错误。我认为“新建项目向导”应该始终生成一个可编译的项目。此外,MCUXpresso IDE 手册明确指出:“同时,选择一个元器件会自动选择其所有依赖项。”(第 5.1.1 节)SDK 新建项目向导)。 我认为这至少是一个用户体验方面的缺陷。 我希望这个问题能在下一个 SDK / MCUXpresso 版本中得到修复。 谢谢。 丹尼尔 Re: New Project Wizard fAiL: no freeRTOS port added automatically 我使用 MCUXpresso IDE v25.6(撰写本文时的最新版本)和 LPC5536 SDK(版本 25.06,清单 3.15)进行了尝试,但 FreeRTOS 内核和 cm33 端口之间的依赖关系仍然缺失,需要手动选择。 Re: New Project Wizard fAiL: no freeRTOS port added automatically 你好@EdwinHz , 感谢您的及时支持。 谢谢。 丹尼尔 Re: New Project Wizard fAiL: no freeRTOS port added automatically 嗨@danielholala , 我重现了这个问题,这绝对是一个 bug,因为项目向导应该会自动选择所有依赖项。我会将此问题报告给 IDE 团队,以便他们可以在 MCUXpresso 项目向导的未来版本中进行修正。 感谢您报告此问题。 BR, 埃德温。
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i.MX8M PLUS) 交換部品互換性 LPDDR4 NXP様、 I.MX8PLUS EVBで使用されたLPDDR4部品である*Z2BMは生産終了です。 部品供給業者は、交換部品として**Z2BMと***Z42BMを推奨しています。 *Z2BM: MT53E1536M32D4DT-046 WT:A (EVB部品) **Z4BM: MT53E1536M32D4DE-046 WT:C (交換部品 1) ***Z42M: MT53E1G32D2FW-046 WT:BP (交換部品 2) これら2種類の交換部品を使用しても問題ないかどうかお伺いしたいのですが。 よろしくお願いします。 よろしくお願いいたします。 チョン・インホ Ace テクノロジ Re: i.MX8M PLUS) Replacement part compatibility LPDDR4 こんにちは、 @Inho さん。 上記の2種類のDRAMは問題なく使えます。 BR
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Offering Contribution: Complete PFE Plugin for S32DS, LWIP Integration & tcpip/LLCE Fixes Hello NXP Team and S32G Community, I have developed a complete PFE plugin for S32 Design Studio (S32DS) / S32 Configuration Tools. Previously, PFE configuration support was available only through EB Tresos. The new plugin includes: Full native integration within the S32DS environment Seamless integration with NXP’s official tcpip plugin for LWIP stack support Complete TSN traffic shaper configuration (TAS and CBS) Thorough testing with LWIP and LLCE, including offload scenarios In the process, I also identified and resolved several bugs in the official tcpip and LLCE plugins. This enhancement enables smoother development of advanced Ethernet and TSN applications on S32G platforms. I would like to contribute the full plugin, integration components, bug fixes, documentation, and test results to NXP. This could be integrated into future RTD or S32 Configuration Tools releases, or shared as an official reference for the community. Questions for the NXP Team: What is the recommended process to formally submit this contribution (e.g., via a technical support case or other channel)? Are there any particular requirements regarding documentation, packaging, or agreements (such as NDA)? I have prepared a comprehensive package including the plugin files, installation/integration guide, detailed changelog, and verification results. I am happy to share it privately and support any technical review or discussion. Thank you in advance for your guidance. I look forward to your feedback. Best regards, Arsal Imam SDV Architect @ GK Automobiltechnologie (Disrupt) GoldVIP Re: Offering Contribution: Complete PFE Plugin for S32DS, LWIP Integration & tcpip/LLCE Fixes Hi,arsalimam First of all, thank you for sharing this impressive work and for your willingness to contribute it to the NXP. The functionality you described—including native S32 Design Studio integration, LWIP/tcpip integration, TSN traffic shaping support (TAS/CBS), LLCE validation, and the related bug fixes—appears very valuable for S32G Ethernet and TSN development. At this stage, contributions of software components, plugins, and modifications to existing NXP tooling require review by the relevant product and software teams. As the acceptance process may involve technical evaluation as well as intellectual property and legal considerations. You can share your materials through our customer support system: https://support.nxp.com We appreciate your effort and your interest in improving the S32G software ecosystem. BR Joey
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i.MX8M PLUS)替换部件兼容性 LPDDR4 尊敬的恩智浦: *Z2BM 是 I.MX8PLUS EVB 中使用的 LPDDR4 元器件,现已停产。 零件供应商推荐使用 **Z2BM 和 ***Z42BM 作为替换零件。 *Z2BM:MT53E1536M32D4DT-046 WT:A(EVB部件) **Z4BM:MT53E1536M32D4DE-046 WT:C(替换零件 1) ***Z42M:MT53E1G32D2FW-046 WT:BP(替换零件 2) 我想咨询一下,使用这两种类型的替换零件是否可以。 谢谢! 顺祝商祺! 全仁浩 艾斯科技 Re: i.MX8M PLUS) Replacement part compatibility LPDDR4 嗨@Inho 您可以毫无问题地使用上述两种类型的动态随机存取存储器(DRAM)。 BR
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i.MX8M PLUS) Replacement part compatibility LPDDR4 Dear NXP,  The *Z2BM, an LPDDR4 component used in the I.MX8PLUS EVB, has been discontinued. The parts supplier has recommended the **Z2BM and ***Z42BM as replacement parts. *Z2BM: MT53E1536M32D4DT-046 WT:A (EVB Part) **Z4BM: MT53E1536M32D4DE-046 WT:C (Replacement Part 1) ***Z42M: MT53E1G32D2FW-046 WT:B P (Replacement Part 2) I would like to inquire if it is acceptable to use these two types of replacement parts. Thank you. Best Regards, Inho Jeon Ace Technologies Re: i.MX8M PLUS) Replacement part compatibility LPDDR4 Hi @Inho  You can use  two types of DRAM mentioned above without any problems. B.R
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Developing a Steering System with Model-Based Design Toolbox 1 Table of Contents • Introduction • Overview • Context • References • Conclusion 2 Introduction The steering system is an essential and safety-critical component of any vehicle, responsible for controlling the direction of wheel movement and guiding the vehicle along the intended path. In our Hello World with MBDT project, the Steering subsystem delivers this capability by driving a steering motor to a desired angle and direction, transmitting the resulting torque to the road wheels through the steering column and rack-and-pinion assembly. Demo Setup - Steering.png Figure 1. Hello World with MBDT Demo – Steering system This article series presents the Electric Power Steering (EPS) system in Electric Vehicle (EV) architecture and covers the hardware, software, code generation, and vehicle network integration needed to implement the system using a Model-Based Design (MBD) workflow with MathWorks tools and NXP hardware. 3 Overview 2.1. What will this series of articles cover? The articles in this series will present the Steering System within an EV architecture and cover the following topics: Software and Hardware Environment Overview of the MathWorks and NXP tools used to develop, test, and validate the EPS control system. Logic Control Description of the model architecture, signal interfaces, and core control algorithms implemented in the Steering System. Deployment on Real Hardware Integration with physical hardware, the stepper motor, and configuration of the NXP MCU peripherals required for motor control. CAN Integration Definition of the CAN communication interface, including database design and integration on the target NXP platform. System Validation Presentation of the final implementation results and validation of the complete system behavior. 2.2. What is the Electric Power Steering System? Electric Power Steering (EPS) eliminates the hydraulic pump found in conventional steering systems, instead relying on an electric motor driven by an Electronic Control Unit (ECU). Torque and position sensors mounted on the steering column feed real-time measurements to the ECU, which computes the required assist level and commands the motor accordingly. This on-demand assist approach improves energy efficiency, enables precise tuning of steering feel, and provides a programmable interface for Advanced Driver Assistance Systems (ADAS). Electric Steering Rack and Pinion.png Figure 2. Electric Steering Rack and Pinion EPS systems are classified based on where the electric motor is mounted on the steering mechanism. Column Assist Type (C-EPS) - The electric motor and control unit are mounted directly on the steering column inside the cabin. Pinion Assist Type (P-EPS) - The electric motor is attached to the pinion shaft within the steering gear box. Dual-Pinion Assist Type (DP-EPS) - This system separates the assist function from the steering mechanism. One pinion gear connects the steering wheel, while the electric motor applies assistance to a second, separate pinion gear directly on the steering rack. Rack Assist Type (R-EPS) - The electric motor is mounted directly onto the main steering rack, either via a concentric motor around the rack or a belt drive. Steer-by-Wire (SbW) - The mechanical connection (steering column and intermediate shaft) between the steering wheel and the wheels is entirely removed. Key Characteristics of Steer-by-Wire EPS: The wheel's movement is handled completely by electronic sensors, algorithms, and actuators It allows for completely customizable steering ratios Frees up interior cabin space Relies heavily on redundant electronics and fail-safes 2.3. Target Audience This series is intended for engineers and technical stakeholders involved in the development, integration, and evaluation of electric power steering systems, including the following audiences: Mechanical and Embedded Software Engineers Motor Control & Power Electronics Engineers System Architects & Vehicle Architecture Engineers Model-Based Design and Simulink Developers Academic and Research Communities 4 Context In the example vehicle architecture used throughout this series, the Steering System is located in the front zone of the vehicle. The Steering ECU is built around the NXP S32K312 microcontroller, which provides both CAN and LIN connectivity. Note: The NXP S32K312 microcontroller provides the processing performance, peripheral set, and communication interfaces (CAN, LIN) required for automotive steering control applications. The ECU drives the stepper motor to the commanded position and communicates desired angle and direction requests over CAN to the Zonal Controller, which coordinates these signals with the central vehicle control node. 5 References Steering column - Wikipedia Power steering - Wikipedia Electric Power Steering (EPS) System Parts Solutions | NXP Semiconductors Electric power steering system (EPS) Clemson Vehicular Electronics Laboratory: Electric Power-Assisted Steering Electric Steering Rack and Pinion 6 Conclusion This article introduced the Electric Power Steering system architecture, its core components, and its position within a modern EV platform. It outlined the Model-Based Design approach using MATLAB/Simulink and NXP hardware as the development foundation, from algorithm modeling through automatic code generation and hardware deployment. The next article will focus on the software and hardware environment required to develop, simulate, and deploy the EPS control system using MathWorks and NXP solutions.
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DOC_S32K3x1_S32K3x2_S32K3x4_eMCEM_DCM_Mapping_v1_0_SPD1.0.5_Unofficial Mapping between SPD eMCEM and DCM for S32K311, S32K312, S32K314, S32K322, S32K324, S32K341, S32K342, S32K344.
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PN7642 - ULPCD evaluation in NFC Cockpit This article describes how to evaluate ULPCD feature together with PN7642 EVK (OM27642EVK) and NFC Cockpit.  1// Disable DC-DC in EEPROM  OM27642EVK does not required any HW changes for ULPCD (**). User is only required to change the following settings in EEPROM  (disable DC-DC converter). Address: 0x0000 (Secure_Lib_Config) Value: 0x21  Reset the board after writing the value.  Tomas_Parizek_0-1745904468298.png **Note: To ensure an accurate and reliable ULPCD evaluation—particularly for ULPCD current measurements. We strongly recommend implementing the following hardware modifications on the OM27642EVK. PN7642_MB.png Note: New revision of the board already have R4=DNP, R8=0Ω. Kindly check this on your board. 2//Set required ULPCD settings in EEPROM  ULPCD VDDPA -> Typically 1.5V. If the HF attenuator is 0x00, increase e.g. to 1.8V. Since the detection range does not significantly depend on the power level, there is no need to set VDDPA above 2 V. Higher VDDPA results in increased current consumption in ULPCD, but does not significantly improve detection performance. RF On Guard time -> This value can be reduced to the minimum -> 5.2 us RSSI Guard time -> Recommended value is 25 RSSI Threshold -> Typically 4~6 Number of RSSI samples -> Typically -> 0 (4 rounds) PN7642_EEPROM_ULPCD.png 3// Perform "Reads HF Attenuator"  Once the required ULPCD settings is set (Guard times, Threshold....). Then User has to perform "Reads HF Attenuator". Make sure that the "HF Attenuator" option is checked.  As written above, the value must not be 0x00. If so, increase VDDPA. 4// Perform ULPCD Calibration and check RSSI Value  For OM27642EVK, the RSSI value for unloaded antenna is typically around 1400dec - 1600dec. 5//Enter ULPCD mode  User can enter the ULPCD mode. The board will again be connected once the load change is detected (e.g. NFC card or smartphone in the antenna proximity). 6// Typical detection performance for 65 mm x 65 mm Antenna tuned to 35Ω. Tomas_Parizek_0-1782466647959.png MIFARE DESFire EV3: Class 1 Antenna  ICODE SLIX: Class 1 Antenna  ICODE 3: Class 6 Antenna  NFC Controller Solutions
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Monitor the CPU loading using ebpf to reduce system call overhead A lightweight CPU utilization monitor built with eBPF + libbpf.   It hooks into the kernel scheduler (sched_switch tracepoint) to measure per-CPU active time with nanosecond precision — more accurate than polling-based tools like top, and with lower overhead at high process counts. How it works   Kernel (eBPF) User space (C + libbpf) ----------------------- ------------------------- sched_switch tracepoint poll BPF maps every 1 s -> record on-CPU time per core -> compute active % and idle % -> accumulate in BPF Array map print per-core + average   The sched_switch tracepoint context structure is defined manually in cpu_monitor_bpf.c. Output The monitor displays per-core active/idle percentages, with the idle column matching top's id field for easy comparison:   CPU Core   | Active %   | Idle % (=top id) ------------------------------------------- CPU 0      |     0.34%  |         99.66% CPU 1      |    21.89%  |         78.11% CPU 2      |     0.15%  |         99.85% CPU 3      |     0.03%  |         99.97% ------------------------------------------- TOTAL AVG  |     5.60%  |         94.40%   To compare with top, press 1 in top to show per-core stats, then compare the id column with the Idle % column above. Prerequisites Host (build machine) Package Purpose clang + llvm version 21 Compile BPF C source to BPF ELF bpftool Generate BFP skeleton headers aarch64 Poky Toolchain Corss-compile the user-space binary   Install on Ubuntu/Debian: wget https://apt.llvm.org/llvm.sh chmod +x llvm.sh ./llvm.sh 21 apt update apt install -y llvm-21 clang-21 lld-21 lldb-21 update-alternatives --install /usr/bin/llvm-link llvm-link /usr/bin/llvm-link-21 100 update-alternatives --install /usr/bin/clang clang /usr/bin/clang-21 100 update-alternatives --install /usr/bin/llc llc /usr/bin/llc-21 100 llvm-link --version clang --version # install bpftool apt install linux-tools-$(uname -r) Target board Tested Linux kernel == 6.18.20-2.0.0 Tested image == imx-image-full Most BPF configurations are enabled by default. In addition, you need CONFIG_FTRACE=y to enable tracepoint support (required for the sched_switch hook). Build Build the project on your host machine: TOOLCHAIN_PATH=/opt/fsl-imx-internal-wayland/6.18-whinlatter/environment-setup-armv8a-poky-linux ./build_and_deploy.sh   The script will: Source the Poky toolchain environment Run make clean && make all (compiles BPF object, generates skeleton, cross-compiles user-space binary) Install the binary to ./board_deploy/cpu_monitor Deploy and run   # Copy binary to the board scp board_deploy/cpu_monitor root@<board-ip>:/usr/bin/ # Run on the board (root required for eBPF) ssh root@<board-ip> ./cpu_monitor   Press Ctrl+C to exit.   Benchmarking: eBPF vs top A scheduler stress test script is included to compare monitoring overhead between cpu_monitor and top under high scheduling pressure. Run the stress test On the target board, open three terminals:   # Terminal 1: start scheduler pressure (200 threads, 30 seconds) ./stress_sched.sh -t 200 -d 30 # Terminal 2: measure eBPF monitoring overhead perf stat -e cpu-clock,task-clock,context-switches,cpu-migrations,instructions timeout -s KILL 10 ./cpu_monitor # Terminal 3: measure top monitoring overhead perf stat -e cpu-clock,task-clock,context-switches,cpu-migrations,instructions top -b -d 1 -n 10 Compare task-clock, instructions, and context-switches from perf stat output. Try different thread counts to observe scaling behavior:   ./stress_sched.sh -t 50 -d 30     # low pressure ./stress_sched.sh -t 200 -d 30    # medium pressure ./stress_sched.sh -t 500 -d 30    # high pressure Result Test environment: i.MX943 (4x Cortex-A55), Linux 6.18.20, 10-second measurement window. Comparison results in free system load: Indicator eBPF cpu_monitor top delta task-clock (CPU timing) 12.0 ms 263.9 ms 22x CPU usage 0.1% 2.8% 28x instructions 3.38M 197M 58x context-switches 12 17   sys time (kernel time) 5.0ms 199.5ms 40x user time 0 62.1ms     Comparison results in high scheduling pressure (200 threads): Indicator eBPF cpu_monitor top delta task-clock (CPU timing) 12.6ms 690ms 54x CPU usage 0.1% 6.1% 61x instructions 4.8M 538M 112x context-switches 122 9019 75x sys time (kernel time) 4ms 461ms 115x user time 0 206ms     Project structure ebpf_cpu_usage/ ├── cpu_monitor_bpf.c      # Kernel-side eBPF program (C, compiled to BPF) ├── cpu_monitor.c          # User-space program (C, cross-compiled to aarch64) ├── Makefile               # Build rules ├── build_and_deploy.sh    # One-shot build + package script ├── stress_sched.sh        # Scheduler stress test for benchmarking └── README.md   A lightweight CPU utilization monitor built with eBPF + libbpf.   It hooks into the kernel scheduler (sched_switch tracepoint) to measure per-CPU active time with nanosecond precision — more accurate than polling-based tools like top, and with lower overhead at high process counts. i.MX Processors
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lowlight opensource ai-isp test on imx95       There are many open-source low-light AI-ISP models. The table below is a comparison table provided by Copilot.  Algorithm GitHub Type i.MX95 NPU Suitability FPGA Suitability MSR (Retinex) jsrsinchana/.../MSR-algorithm Non-AI (ISP) Medium Very High Zero-DCE++ arnabroy734/low_light_enhancement Lightweight CNN + Curve Very High Very High RetinexNet weichen582/RetinexNet CNN (Retinex) Medium High EnlightenGAN VITA-Group/EnlightenGAN GAN (CNN) Very High (lite) Low FLOL cidautai/FLOL Lightweight CNN High Low SNR-aware JIA-Lab-research/SNR-Aware Transformer + CNN Low Low KinD zhangyhuaee/KinD Retinex + CNN Medium Medium RetinexNet-lite Derived Light CNN Medium High EnlightenGAN-lite Derived Small CNN Very High Low Fast LLIE CNN Various Small CNN High Medium We selected some open-source models and used UVC to perform performance tests on the exip-os08a20 module with no HDR mode. We found that SCI(GitHub - vis-opt-group/SCI: [CVPR 2022] This is the official code for the paper "Toward Fast, Flexible, and Robust Low-Light Image Enhancement". · GitHub) computation is relatively small, low-light performance is good in subjective evaluations, and it can basically run on the IMX95. The testing method involves copying the tflite file and test script to the /root/ directory of the IMX95 and running the following command: `python3 test_sci_cvpr_illu_imx95_int8.py --model sci_tpami_illu_imx95_int8.tflite`. The comparison interface shown below is displayed. Image (7).jfif
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