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LPC553x 参考手册:表 315 SCT0 信号错误 (SCTIMER) 你好, 我想报告 LPC553x 参考手册(修订版)中似乎存在的一个重大错误。4) 将表 315“SCT0 信号(输出)”与数据表表 3 进行比较,并询问哪个来源是权威的。 这是 LPC553x 参考手册,修订版 4,表 315“SCT0 信号(输出)”: 下表列出了 34 个外部引脚(如果我数得没错的话)。快速浏览 LPC553x 数据手册,发现它只有 31 个引脚。此外,表 315 列出了 PIO2_2、PIO2_9、PIO2_15、PIO2_30 和 PIO2_31 作为 SCT0 输出引脚。从数据手册来看,LPC553x 只实现了 PIO2_0 和 PIO2_1,所以该设备上不存在 Port-2 引脚。 现在,如果您仔细查阅数据手册中的表 3 并提取所有 SCT0_OUT 引脚,那么您最终会得到一个完全不同的表格: SCT0 信号(输出)连接至 SCT0_OUT0 PIO0_2、PIO0_17、PIO1_4、PIO1_23 SCT0_OUT1 PIO0_3、PIO0_18、PIO1_8、PIO1_24 SCT0_OUT2 PIO0_10、PIO0_15、PIO0_19、PIO1_9、PIO1_25 SCT0_OUT3 PIO0_22、PIO0_31、PIO1_10、PIO1_26 SCT0_OUT4 PIO0_23、PIO1_3、PIO1_17 SCT0_OUT5 PIO0_26、PIO1_18 SCT0_OUT6 PIO0_6、PIO0_27、PIO1_31 SCT0_OUT7 PIO0_21、PIO0_28、PIO1_19 SCT0_OUT8 PIO0_29,PIO1_13 SCT0_OUT9 PIO0_30 我的设计以数据手册表 3 为依据。 请, 确认数据手册(修订版 5.0)表 3 是 SCT0 输出引脚的权威来源, 确认参考手册中的表315有误。 请确认我上面的表格是否正确。 谢谢。 担 Re: LPC553x reference manual: Table 315 SCT0 Signals wrong (SCTIMER) 你好, 请使用参考手册中附带的“引脚功能表”来确定 SCT0_OUT 功能的可用引脚。 顺祝商祺!   Re: LPC553x reference manual: Table 315 SCT0 Signals wrong (SCTIMER) 你好, 目前,请参考引脚功能表。 我将信息传递给团队。 此致敬礼,路易斯 Re: LPC553x reference manual: Table 315 SCT0 Signals wrong (SCTIMER) 你好@luis_maravilla , 感谢您指出“引脚功能表”。我不知道参考手册里竟然隐藏着一个电子表格文件。 我快速浏览了一下“引脚功能表”,证实参考手册中表 315 “SCT0 信号(输出)”的信息不正确。 请将此信息转交给文档团队进行更正。 如果对引脚功能还有其他疑问,权威来源是数据手册还是引脚功能表? 谢谢。 此致, 丹尼尔
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i.MX93 Nitrogen93 SMARC: UUU script hangs at FB to FBK transition after launching Initramfs Context & Environment: Hardware: Nitrogen93 SMARC Development Board (i.MX93) UUU Version: 1.2.39 OS/Images: Loading the Linux kernel, .dtb and an initramfs via Fastboot to handle eMMC provisioning. USB Configuration: FunctionFS / ConfigFS USB gadget support is explicitly enabled in our kernel and initramfs configuration. The problem is: The UUU script hangs indefinitely right during the transition from the Fastboot (FB) stage to the Fastboot Kernel (FBK) stage. On the host PC terminal, UUU successfully executes the boot command and stalls: 1:9-0019B8127987>Start Cmd:FB: acmd booti ${loadaddr} ${initrd_addr} ${fdt_addr} 1:9-0019B8127987>Okay (0.001s) On the target serial console, the kernel boots and launches the initramfs environment, but it blocks and opens an interactive shell rather than handing control over to the UUU daemon: [ 3.087193] Run /init as init process /bin/sh: can't access tty; job control turned off ~ # [ 3.141909] mmc2: new ultra high speed SDR104 SDIO card at address 0001 Because the console drops straight into a standard shell (~ #), the script never acts on the subsequent FBK: flashing commands. Key Snippets of our  custom UUU Configuration We are defining the boot arguments and initiating the boot sequence as follows: FB: ucmd setenv bootargs "console=ttyLP0,115200 root=/dev/ram0 rw rdinit=/init mfg_mmcdev=${emmc_dev}" FB: acmd booti ${loadaddr} ${initrd_addr} ${fdt_addr} # Script hangs here; FBK commands below are never processed FBK: ucmd cmdline=`cat /proc/cmdline`; ... We are stuck at the transition between the Fastboot (FB) and Fastboot Kernel (FBK) stages in our custom UUU script. The target drops into an interactive shell, and the script hangs. How do we proceed from this point to get the UUU daemon talking to the host? Thanks
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LPC553x reference manual: Table 315 SCT0 Signals wrong (SCTIMER) Hello, I’d like to report what looks like a significant error in the LPC553x Reference Manual (Rev. 4), Table 315 “SCT0 signals (outputs)” when compared to the Data Sheet, Table 3, and ask which source is authoritative. This is LPC553x Reference Manual, Rev. 4, Table 315 "SCT0 signals (outputs)": There are 34 external pins listed in this table (if I counted correctly). A quick search through the LPC553x Data Sheet finds only 31 pins. Further, Table 315 lists PIO2_2, PIO2_9, PIO2_15, PIO2_30 and PIO2_31 as SCT0 output pins. As far as I can tell from the Data Sheet, the LPC553x only implements PIO2_0 and PIO2_1, so those Port-2 pins do not exist on this device.  Now, if you meticulously go through Table 3 of the data sheet and extract all SCT0_OUT pins, then  you end up with a completely different table: SCT0 signals (outputs) Connect to SCT0_OUT0 PIO0_2, PIO0_17, PIO1_4, PIO1_23 SCT0_OUT1 PIO0_3, PIO0_18, PIO1_8, PIO1_24 SCT0_OUT2 PIO0_10, PIO0_15, PIO0_19, PIO1_9, PIO1_25 SCT0_OUT3 PIO0_22, PIO0_31, PIO1_10, PIO1_26 SCT0_OUT4 PIO0_23, PIO1_3, PIO1_17 SCT0_OUT5 PIO0_26, PIO1_18 SCT0_OUT6 PIO0_6, PIO0_27, PIO1_31 SCT0_OUT7 PIO0_21, PIO0_28, PIO1_19 SCT0_OUT8 PIO0_29, PIO1_13 SCT0_OUT9 PIO0_30 For my design I am using the datasheet Table 3 as the source of truth. Please,  confirm that the Data Sheet (Rev 5.0) Table 3 is the authoritative source for SCT0 output pins, confirm that table 315 of Reference Manual is incorrect, confirm that my table above is correct.  Thanks. Dan Re: LPC553x reference manual: Table 315 SCT0 Signals wrong (SCTIMER) Hello, Please use the "Pin Function Table" attached in the Reference Manual to identify the available pins for SCT0_OUT functionality. Best Regards   Re: LPC553x reference manual: Table 315 SCT0 Signals wrong (SCTIMER) Hello, For now, please reference to Pin Function Table. I pass the information to the team. Best Regards, Luis Re: LPC553x reference manual: Table 315 SCT0 Signals wrong (SCTIMER) Hello @luis_maravilla , Thank you for pointing to the "Pin Function Table". I did not know that a spreadsheet file had been hidden inside the Reference Manual.  I had a quick glance at the "Pin Function Table" and it confirms that the information in Table 315 "SCT0 signals (outputs)" in the Reference Manual is incorrect. Could you please pass this information on to the documentation team for correction? In case there are further discrepancies regarding pin functions, what is the authoritative source, the Data Sheet or the Pin Function Table? Thanks. Best regards, Daniel
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How to enter in LPM mode of MSDI MC33CD1030 on S32K396BMS-EVB using NXP MBDT Hi,  I need some MBDT reference settings or ready model for entering LPM in CD1030 using S32K396BMS-EVB. Please support. Thanks
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Flashing a build onto a custom IMXRT106x board I designed and built a custom board utilizing the IMXRT1062 and have configured the device in zephyr and compiled the blinky program. From here how do I go about flashing this program onto the device over USB. I've tried the Secure Provision Tool, however the LED program doesn't seem to work. Is there I could view the flash setup and customize the configurations for the board? Any help would be appreciated.  Re: Flashing a build onto a custom IMXRT106x board I've switched over to MCUXpresso to perform the initial programming. Is there a guide on how to build a file in MCUXpresso and use it to flash with the MCU Secure Provision Tool. As I'm only able to upload images to the device over USB. Additionally where can I find documentation about configuring a custom SPI Flash chip in MCUXpresso? Re: Flashing a build onto a custom IMXRT106x board Hi @rocketcherry , Thanks for your interest in NXP MIMXRT series! The MCUXpresso Secure Provisioning Tool uses the device ROM serial downloader path over USB-HID/UART. It can program the external boot device, but the programmed image still needs to be a valid bootable i.MX RT image for your custom hardware. For an RT1062 booting from external QSPI/FlexSPI NOR, the boot header / Flash Configuration Block must match your actual flash device, FlexSPI pins, bus width, frequency, dummy cycles and flash size. If the board was cloned from the MIMXRT1060-EVK Zephyr board files, please do not assume the EVK flash configuration is valid for your custom board. We would suggest first validating the board port with a simple serial hello_world application using a debug probe, because a blinky failure can also be caused by an incorrect LED GPIO in the devicetree. Then check the generated build/zephyr/zephyr.dts, .config, and zephyr.map to confirm that the flash node, code partition, RAM region, console UART, and LED GPIO match your board. Secure Provisioning Tool can program the device over USB-HID, but if the LED application does not run after reset, the first things to verify are the custom Zephyr board port, the FlexSPI NOR boot header/FCB, boot mode settings, RAM/SDRAM configuration, and LED GPIO mapping. Best regards, Gavin Re: Flashing a build onto a custom IMXRT106x board It seems the steps are outlined for different processors on this page https://docs.nxp.com/bundle/MCUXSPTUG_26.03/page/06_processor_specific_workflow.html The build was fine it was the incorrect usage of the tool that was the problem
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Mac OS Tahoe 更新 LinkServer 未找到探测器 所以我升级到了 Tahoe 版本,但是在使用 LinkServer 时找不到探测器。所以我把 LinkServer 更新到了最新版本,但它只有在终端里进入目录并手动运行后才能工作。 ./LinkServer 探测 之后就能找到探针,我可以使用MCUXpresso了。这种情况似乎也发生在其他人身上。 https://community.nxp.com/t5/MCUXpresso-General/LPC-Link2-not-found/mp/2200131/highlight/true#M5741 这是 IDE 尝试使用 LinkServer 时出现的错误。 redlink> 探针列表 错误:未找到探针 我也在一家大公司工作,其他更新了操作系统的人也遇到了同样的问题,不得不采取同样的措施。 有没有人知道更好的解决方法? Re: Mac OS Tahoe update LinkServer No Probes found 嗨@davidinsulet , 遗憾的是,这是预装在最新版本 MCUXpresso IDE 中的 LinkServer 版本的当前限制。也就是说,这一限制已被发现并报告给 IDE 团队,以便他们可以在未来的版本中修正 LinkServer 版本。 与此同时,您分享的帖子中描述的解决方法是解决此问题(特别是针对 MCUXpresso IDE)的最有效方法。 或者,您也可以推荐使用MCUXpresso for VS Code ,这是我们最新的开发平台,目前没有像 IDE 那样的限制。 由此造成的不便,敬请谅解。 BR, 埃德温。
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NXH2004 评估套件:蓝牙® 5.3 AoBLE 认证板详情及数据手册 大家好, 分享 NXH2004 评估套件的详细信息:蓝牙® 5.3 AoBLE 认证板的详细信息和数据表,适用于助听器应用。 此致, SK Re: NXH2004 Evaluation Kit: Bluetooth® 5.3 AoBLE Certified Board details and datasheet 你好,Sumit, 请参阅产品页面: https://www.nxp.com/design/design-center/development-boards-and-designs/NXH2004SDK https://www.nxp.com/products/NXH2004 在特定条件下可以获取 WIFI 产品的文档。请让您的客户联系恩智浦内部的销售代表。他将直接协助他。谢谢。 祝你今天过得愉快。此致 帕夫拉
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将版本烧录到定制的 IMXRT106x 板上 我设计并制造了一块使用 IMXRT1062 的定制板,并在 zephyr 中配置了该设备,并编译了闪烁程序。接下来,我该如何通过 USB 将此程序刷入设备?我尝试过使用安全配置工具,但是 LED 程序似乎无法正常工作。我可以在哪里查看闪存设置并自定义电路板的配置?非常感谢您的帮助。 Re: Flashing a build onto a custom IMXRT106x board 我已经改用 MCUXpresso 进行初始编程。是否有关于如何在 MCUXpresso 中构建文件并使用 MCU Secure Provision Tool 进行配置的指南?因为我只能通过 USB 接口将图片上传到设备。另外,我可以在哪里找到有关在 MCUXpresso 中配置自定义 SPI Flash 芯片的文档? Re: Flashing a build onto a custom IMXRT106x board 嗨@rocketcherry , 感谢您对 NXP MIMXRT 系列产品的关注! MCUXpresso 安全配置工具使用 USB-HID/UART 上的设备 ROM 串行下载器路径。它可以对外部引导设备进行编程,但编程的映像仍然需要是适用于您的自定义硬件的有效可启动 i.MX RT 映像。对于从外部 QSPI/FlexSPI 或非 启动的 RT1062,启动头/闪存配置块必须与您的实际闪存设备、FlexSPI 引脚、总线宽度、频率、虚拟周期和闪存大小相匹配。如果电路板是从 MIMXRT1060-EVK Zephyr 电路板文件克隆的,请不要假设 EVK 闪存配置对您的自定义电路板有效。 我们建议首先使用调试探针通过简单的串行 hello_world 应用程序验证板端口,因为闪烁故障也可能是设备树中错误的 LED GPIO 引起的。然后检查生成的 build/zephyr/zephyr.dts、.config 文件,使用 zephyr.map 确认 flash 节点、代码分区、RAM 区域、控制台 UART 和 LED GPIO 与您的板子匹配。 安全配置工具可以通过 USB-HID 对设备进行编程,但如果 LED 应用程序在 RESET 后无法运行,则首先要验证的是自定义 Zephyr 板端口、FlexSPI 或非 启动头/FCB、启动模式设置、RAM/同步动态随机存取存储器(SDRAM) 配置和 LED GPIO 映射。 此致, 加文 Re: Flashing a build onto a custom IMXRT106x board 此页面似乎列出了不同处理器的具体步骤:https://docs.nxp.com/bundle/MCUXSPTUG_26.03/page/06_processor_specific_workflow.html 版本本身没有问题,问题出在工具的使用方法上。
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功能RESET后 RAM 数据保持功能失效 (S32K3xx) 大家好, 我们正在尝试在 S32K3xx 上进行 RESET 时保留一个变量,但它不起作用。 执行: 变量放置在自定义 RAM 部分: __attribute__ ((section(".int_sram_results"))) uint32_t retain_var; 在RESET之前更新该值(用于测试 retain_var= 0x11223344)。 RESET类型: 功能RESET(软件触发) 观察到的行为: 但该值始终为0(已清除) RAM 保留功能没有出现。 参考资料已核实: 我已经参考过这个讨论,并且尝试了建议的方法: https://community.nxp.com/t5/S32K/S32K311-noinit-ram/td-p/2123035 那里提供的例子在我们这里并不适用。 要求: 请提供一个可运行的示例或最小代码片段,说明如何在 S32K3xx 芯片上进行 RESET 后保留 RAM。 谢谢! Yusup S32K3 S32DS-ARM S32K31XEVB-Q100 Re: RAM retention not working across functional reset (S32K3xx) 你好@yusupkhan241 , 启动代码很可能在每次RESET后将整个 SRAM 初始化为零(用于 ECC 初始化)——我还没有看到你的具体启动代码。 如果RESET功能正常,您可以考虑跳过 ECC 初始化。 请参考此答案: https://community.nxp.com/t5/S32K/SRAM-ECC-Initialization-for-S32K344/mp/1764143 BR,丹尼尔 Re: RAM retention not working across functional reset (S32K3xx) 你好@yusupkhan241 , 你说的“不起作用”是什么意思? 您上传的文件似乎没有反映最新的更改。 能否单步执行启动代码,并观察功能 RESET 后 SRAM 中的变量?这样就能清楚地显示变量被覆盖的位置。 要在功能复位后附加调试器,可以在启动代码的开头添加一个简单的循环,例如: Loop: mov r0, #1 cmp r0, 0 /* Change r0 to 0 in register view */ bne Loop /* Capture after power-on reset */ 此致, 丹尼尔 Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction. Re: RAM retention not working across functional reset (S32K3xx) 嗨@danielmartynek 我简化了设置,以便隔离 RAM 保留行为。 我将变量放在专用的 SRAM 部分,并使用了一个最小的主函数,带有 LED 指示和看门狗触发的RESET。其理念是: 绿色 LED → RESET 后数值保持不变 红色 LED → 价值损失 以下是所使用的测试代码: C __attribute__ ((section(".int_sram_results"), used)) volatile uint32_t retain_var; int main(void) { Clock_Ip_Init(&Clock_Ip_aClockConfig[0]); DIO_Init(); WDT_Init(); 如果 (retain_var == 0xAABBCCDD) { Siul2_Dio_Ip_SetPins(LED_GREEN_PORT, (1UL << LED_GREEN_PIN)); Siul2_Dio_Ip_ClearPins(LED_RED_PORT, (1UL << LED_RED_PIN)); } else { Siul2_Dio_Ip_SetPins(LED_RED_PORT, (1UL << LED_RED_PIN)); Siul2_Dio_Ip_ClearPins(LED_GREEN_PORT, (1UL << LED_GREEN_PIN)); } retain_var = 0xAABBCCDD; while(1) { /* 看门狗 RESET */ } } 显示更少 观察: 使用调试器运行时,行为符合预期。 然而,上电复位后,没有 LED 指示,这表明代码可能没有按预期执行。 我已附上最新的链接器和启动文件供您参考。 如果您发现启动或重置处理方面有任何缺失,请告诉我。 S32DS-ARM S32K31XEVB-Q100 谢谢, 优素福 Re: RAM retention not working across functional reset (S32K3xx) 嗨@danielmartynek 我已将下面的启动指令替换为您分享的更改,但它仍然不起作用。 供您参考,我已经上传了相关文件。.s 和 .ld上传的文件带有 .c 后缀。扩大。请您审阅一下,如有任何其他疑问,请随时联系我。 RamInit: /* 初始化 SRAM ECC */ ldr r0,=__RAM_INIT cmp r0, 0 /* 如果未设置 __RAM_INIT,则跳过 */ beq SRAM_LOOP_END ldr r0,=MCRGM_DES ldr r1,[r0] ldr r2,=MCRGM_DES_F_POR 以及 r1、r1、r2 cmp r1,0 beq NO_INIT_STANDBY_REGION ldr r2, =__INT_SRAM_START ldr r3, =__INT_SRAM_END b ZERO_64B_RAM 以上说明已更新。 RamInit: /* Check MC_RGM DES register, if it's non-zero, jump to RAMInit_Start. (RAM init is needed if Destructive reset occurred) */ /* To make it work, customer should clear the MC_RGM DES register in application code. */ ldr r4, =MC_RGM_BASE_ADDR /* 0x4028C000 */ ldr r4, [r4, #0x0] cmp r4, #0x0 bne RamInit_Start /* Check MC_RGM FES register, if the F_EXR bit or ST_DONE bit is set, jump to RAMInit_Start. */ /* RAM init is needed if external reset occurred, or BIST Done functional reset occurred. */ /* To make it work, customer should clear the MC_RGM FES F_EXR register bit in application code. */ ldr r4, =MC_RGM_BASE_ADDR ldr r4, [r4, #0x8] ldr r5, =MC_RGM_FES_MASK_RAM_INIT and r4, r4, r5 cmp r4, #0x0 bne RamInit_Start b SRAM_LOOP_END RamInit_Start: /* Initialize SRAM ECC */ ldr r0, =__RAM_INIT cmp r0, 0 /* Skip if __SRAM_INIT is not set */ beq SRAM_LOOP_END ldr r1, =__INT_SRAM_START ldr r2, =__INT_SRAM_END 谢谢! 优素福 Re: RAM retention not working across functional reset (S32K3xx) 能否分享一下整个测试项目,以便我这边也能轻松测试? 谢谢! 丹尼尔 Re: RAM retention not working across functional reset (S32K3xx) 嗨@danielmartynek 以下是我们测试得出的观察结果:  调试模式行为: 上电复位(红色 LED 指示灯亮起): retain_var = 0x5AA55AA5 @ 0x20407B00 看门狗复位后(绿色 LED 指示灯亮起): 保留变量 = 0xAABBCCDD @ 0x20407B00 这证实了在调试器下运行时,功能 RESET 后的 RAM 数据保持功能正常。 但是,当以独立模式运行(不使用调试器)时: 上电复位后,LED指示灯不亮。 程序似乎没有执行,或者没有到达应用程序代码。 请问您能否帮忙找出导致这种行为的原因?此外,我们计划使用完整的.int_sram_results。用于在功能RESET时保留多个参数的部分。请提出是否需要进行任何其他更改以确保可靠的数据保留。 另外,请问是否有任何 API 或推荐的方法来触发功能性重置(除了看门狗机制之外) ? 作为参考,我已将启动文件和链接器文件中的更改包含在内,您可以在共享项目中验证这些更改。 启动文件(旧代码) RamInit: /* 初始化 SRAM ECC */ ldr r0,=__RAM_INIT cmp r0, 0 /* 如果未设置 __RAM_INIT,则跳过 */ beq SRAM_LOOP_END ldr r0,=MCRGM_DES ldr r1,[r0] ldr r2,=MCRGM_DES_F_POR 以及 r1、r1、r2 cmp r1,0 beq NO_INIT_STANDBY_REGION ldr r2, =__INT_SRAM_START ldr r3, =__INT_SRAM_END b ZERO_64B_RAM 启动文件(新代码) .equ MC_RGM_BASE_ADDR,0x4028C000 .equ MC_RGM_FES_MASK_RAM_INIT, 0xFFFFFFFF RamInit: /* 检查 MC_RGM DES 寄存器,如果它不为零,则跳转到 RAMInit_Start。(如果发生了破坏性重置,则需要进行 RAM 初始化) /* 要使其正常工作,客户应在应用程序代码中清除 MC_RGM DES 寄存器。*/ ldr r4, =MC_RGM_BASE_ADDR /* 0x4028C000 */ ldr r4, [r4, #0x0] cmp r4,#0x0 bne RamInit_Start /* 检查 MC_RGM FES 寄存器,如果 F_EXR 位或 ST_DONE 位已设置,则跳转到 RAMInit_Start。*/ /* 如果发生外部复位,或者发生 BIST 完成功能复位,则需要进行 RAM 初始化。*/ /* 要使其正常工作,客户应在应用程序代码中清除 MC_RGM FES F_EXR 寄存器位。*/ ldr r4,=MC_RGM_BASE_ADDR ldr r4, [r4, #0x8] ldr r5,=MC_RGM_FES_MASK_RAM_INIT 以及 r4、r4、r5 cmp r4,#0x0 bne RamInit_Start b SRAM_LOOP_END RamInit_Start: /* 初始化 SRAM ECC */ ldr r0,=__RAM_INIT cmp r0, 0 /* 如果未设置 __SRAM_INIT,则跳过 */ beq SRAM_LOOP_END ldr r1, =__INT_SRAM_START ldr r2, =__INT_SRAM_END b ZERO_64B_RAM 链接器文件更改 旧代码: .int_results(NOLOAD):     { 。= ALIGN(4); KEEP(*(.int_results)) 。+= 0x100; } > int_sram_results 新代码: .int_results(NOLOAD):     { 。= ALIGN(4); KEEP(*(.int_results)) } > int_sram_results S32K31XEVB-Q100 谢谢, 优素福 Re: RAM retention not working across functional reset (S32K3xx) 你好@yusupkhan241 , 我已经调试过,发现下面的代码有误。 它使用了 R1 和 R2 而不是 R2 和 R3: 我们需要R2和R3的原因如下: 你从哪里弄到这段启动代码的? 连接调试器后,调试器会初始化 SRAM ECC。 如果没有调试器,则在 0x20400090 处出现硬故障。 此致, 丹尼尔 Re: RAM retention not working across functional reset (S32K3xx) 嗨@danielmartynek 修复使用 R2/R3 的问题后,应用程序可以运行了。 但是,红色 LED 指示灯始终闪烁,绿色指示灯始终不亮,表明 RESET 后该值无法保留。 我已经应用了您分享链接中的启动更改,但数据保留功能仍然没有按预期工作。 S32K3 S32DS-ARM https://community.nxp.com/t5/S32K/SRAM-ECC-Initialization-for-S32K344/mp/1764143 谢谢, 优素福
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Mac OS Tahoe アップデート LinkServer プローブが見つかりません そこでTahoeにアップデートしましたが、LinkServerを使ってもプローブは見つかりませんでした。LinkServerを最新にアップデートしましたが、ターミナルでディレクトリに入って手動で実行しないと動作しません ./LinkServer プローブ その後プローブが見つかり、MCUXpressoを使えます。どうやらこれは他の人にも起こる現象のようだ。 https://community.nxp.com/t5/MCUXpresso-General/LPC-Link2-not-found/mp/2200131/highlight/true#M5741 これはIDEがLinkServerを使おうとしたときに表示されるエラーです redlink>プローブリスト エラー: プローブが見つかりませんでした 私もNXPについてで働いていますが、OSをアップデートした人たちも同じ問題を抱え、同じことをしなければならないと感じています。 もっと良い解決策をご存知の方はいらっしゃいますか? Re: Mac OS Tahoe update LinkServer No Probes found こんにちは、 @davidinsulet さん、 残念ながら、これは最新バージョンのMCUXpresso IDEにプリインストールされているLinkServerビルドの現在の制限です。とはいえ、この制限はIDEチームに特定され報告されており、将来のリリースでLinkServerのバージョンを修正できるようになっています。 その間に、あなたが共有した投稿で説明されている回避策が、MCUXpresso IDEに関してこの問題を回避する最も効果的な方法です。 あるいは、 MCUXpresso for VS Codeを使うこともおすすめします。これは私たちの最新開発プラットフォームで、IDEsのような制限はありません。 ご迷惑をおかけして申し訳ございません。 BR、 エドウィン。
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RAM retention not working across functional reset (S32K3xx) Hi Team, We are trying to retain a variable across functional reset on S32K3xx, but it is not working. Implementation: Variable placed in custom RAM section: __attribute__((section(".int_sram_results"))) uint32_t retain_var;               The value is being updated before reset (for testing retain_var= 0x11223344) . Reset type: Functional reset (software-triggered) Observed behaviour: But value is always 0 (cleared) RAM retention is not happening Reference checked: Already referred this discussion and tried the suggested approach: https://community.nxp.com/t5/S32K/S32K311-noinit-ram/td-p/2123035 The example provided there did not work in our case Request: Please share a working example or minimal snippet for retaining RAM across functional reset on S32K3xx Thanks, Yusup S32K3 S32DS-ARM S32K31XEVB-Q100  Re: RAM retention not working across functional reset (S32K3xx) Hi @yusupkhan241, The startup code most likely initializes the entire SRAM to zero (for ECC initialization) after every reset—I haven’t seen your specific startup code. You could consider skipping the ECC initialization when the reset is functional. Refer to this answer: https://community.nxp.com/t5/S32K/SRAM-ECC-Initialization-for-S32K344/m-p/1764143 BR, Daniel Re: RAM retention not working across functional reset (S32K3xx) Hi @yusupkhan241, What do you mean by “it does not work”? The files you posted do not seem to reflect the latest changes. Can you step through the startup code and observe the variable in SRAM after a functional reset? This should clearly show where the variable gets overwritten. To attach the debugger after the functional reset, you can add a simple loop at the beginning of the startup code, for example: Loop: mov r0, #1 cmp r0, 0 /* Change r0 to 0 in register view */ bne Loop /* Capture after power-on reset */ Regards, Daniel Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction. Re: RAM retention not working across functional reset (S32K3xx) Hi @danielmartynek I have simplified the setup to isolate the RAM retention behavior. I placed the variable in a dedicated SRAM section and used a minimal main function with LED indication and watchdog-triggered reset. The idea is: Green LED → value retained after reset Red LED → value lost Below is the test code being used: C __attribute__((section(".int_sram_results"), used)) volatile uint32_t retain_var; int main(void) { Clock_Ip_Init(&Clock_Ip_aClockConfig[0]); DIO_Init(); WDT_Init(); if (retain_var == 0xAABBCCDD) { Siul2_Dio_Ip_SetPins(LED_GREEN_PORT, (1UL << LED_GREEN_PIN)); Siul2_Dio_Ip_ClearPins(LED_RED_PORT, (1UL << LED_RED_PIN)); } else { Siul2_Dio_Ip_SetPins(LED_RED_PORT, (1UL << LED_RED_PIN)); Siul2_Dio_Ip_ClearPins(LED_GREEN_PORT, (1UL << LED_GREEN_PIN)); } retain_var = 0xAABBCCDD; while (1) { /* watchdog reset */ } } Show less Observation: When running with debugger, the behavior is as expected. However, after power-on reset, there is no LED indication, which suggests the code may not be executing as expected. I have attached the latest linker and startup files for reference. Please let me know if you see anything missing on the startup or reset handling side. S32DS-ARM S32K31XEVB-Q100  Thanks, Yusup Re: RAM retention not working across functional reset (S32K3xx) Hi @danielmartynek I replaced the startup instructions below with the changes you shared, but it did not work. For your reference, I have uploaded the relevant files. The .s and .ld files were uploaded with a .c extension. Please review them and let me know if you need any additional information. RamInit: /* Initialize SRAM ECC */ ldr r0, =__RAM_INIT cmp r0, 0 /* Skip if __RAM_INIT is not set */ beq SRAM_LOOP_END ldr r0, =MCRGM_DES ldr r1, [r0] ldr r2, =MCRGM_DES_F_POR and r1, r1, r2 cmp r1, 0 beq NO_INIT_STANDBY_REGION ldr r2, =__INT_SRAM_START ldr r3, =__INT_SRAM_END b ZERO_64B_RAM The above instructions updated with  RamInit: /* Check MC_RGM DES register, if it's non-zero, jump to RAMInit_Start. (RAM init is needed if Destructive reset occurred) */ /* To make it work, customer should clear the MC_RGM DES register in application code. */ ldr r4, =MC_RGM_BASE_ADDR /* 0x4028C000 */ ldr r4, [r4, #0x0] cmp r4, #0x0 bne RamInit_Start /* Check MC_RGM FES register, if the F_EXR bit or ST_DONE bit is set, jump to RAMInit_Start. */ /* RAM init is needed if external reset occurred, or BIST Done functional reset occurred. */ /* To make it work, customer should clear the MC_RGM FES F_EXR register bit in application code. */ ldr r4, =MC_RGM_BASE_ADDR ldr r4, [r4, #0x8] ldr r5, =MC_RGM_FES_MASK_RAM_INIT and r4, r4, r5 cmp r4, #0x0 bne RamInit_Start b SRAM_LOOP_END RamInit_Start: /* Initialize SRAM ECC */ ldr r0, =__RAM_INIT cmp r0, 0 /* Skip if __SRAM_INIT is not set */ beq SRAM_LOOP_END ldr r1, =__INT_SRAM_START ldr r2, =__INT_SRAM_END Thanks, Yusup Re: RAM retention not working across functional reset (S32K3xx) Can you share the whole test project so that I can easily test it on my side? Thank you, Daniel Re: RAM retention not working across functional reset (S32K3xx) Hi @danielmartynek Below are the observations from our testing:  Debug mode behaviour: Power-on reset (RED LED): retain_var = 0x5AA55AA5 @ 0x20407B00 After watchdog reset (GREEN LED): retain_var = 0xAABBCCDD @ 0x20407B00 This confirms that RAM retention across functional reset is working when running under debugger. However, when running standalone (without debugger): After power-on reset, there is no LED indication. It appears that the program is not executing or not reaching the application code. Could you please help identify what might be causing this behaviour? Also, we are planning to use the complete .int_sram_results section to retain multiple parameters across functional reset. Please suggest if any additional changes are required for reliable retention. Additionally, could you please suggest if there is any API or recommended method to trigger a functional reset (alternative to watchdog)? For reference, I have included the changes made in the startup and linker files, and the same can be verified in the shared project. startup file (old code) RamInit:     /* Initialize SRAM ECC */     ldr  r0, =__RAM_INIT     cmp  r0, 0     /* Skip if __RAM_INIT is not set */     beq SRAM_LOOP_END     ldr r0, =MCRGM_DES     ldr r1, [r0]     ldr r2, =MCRGM_DES_F_POR     and r1, r1, r2     cmp r1, 0     beq NO_INIT_STANDBY_REGION     ldr r2, =__INT_SRAM_START     ldr r3, =__INT_SRAM_END     b   ZERO_64B_RAM startup file (new code) .equ MC_RGM_BASE_ADDR, 0x4028C000 .equ MC_RGM_FES_MASK_RAM_INIT, 0xFFFFFFFF RamInit:                /* Check MC_RGM DES register, if it's non-zero, jump to RAMInit_Start. (RAM init is needed if Destructive reset occurred) */                /* To make it work, customer should clear the MC_RGM DES register in application code. */                ldr r4, =MC_RGM_BASE_ADDR   /* 0x4028C000 */                ldr r4, [r4, #0x0]                cmp r4, #0x0                bne RamInit_Start                /* Check MC_RGM FES register, if the F_EXR bit or ST_DONE bit is set, jump to RAMInit_Start. */                /* RAM init is needed if external reset occurred, or BIST Done functional reset occurred. */                /* To make it work, customer should clear the MC_RGM FES F_EXR register bit in application code. */                ldr r4, =MC_RGM_BASE_ADDR                ldr r4, [r4, #0x8]                ldr r5, =MC_RGM_FES_MASK_RAM_INIT                and r4, r4, r5                cmp r4, #0x0                bne RamInit_Start                b SRAM_LOOP_END                RamInit_Start:                /* Initialize SRAM ECC */                ldr r0, =__RAM_INIT                cmp r0, 0                /* Skip if __SRAM_INIT is not set */                beq SRAM_LOOP_END                ldr r1, =__INT_SRAM_START                ldr r2, =__INT_SRAM_END     b   ZERO_64B_RAM linker file changes old code:     .int_results (NOLOAD):     {         . = ALIGN(4);         KEEP(*(.int_results))         . += 0x100;     } > int_sram_results new code:                    .int_results (NOLOAD):     {         . = ALIGN(4);         KEEP(*(.int_results))     } > int_sram_results    S32K31XEVB-Q100  Thanks, Yusup Re: RAM retention not working across functional reset (S32K3xx) Hi @yusupkhan241, I have debugged it found that the code below was incorrect. It used R1 and R2 instead of R2 and R3: We need R2 and R3 because of this: Where did you get this startup code? With the debugger connected, the debugger initializes the SRAM ECC. Without the debugger, there was a Hardfault at 0x20400090. Regards, Daniel Re: RAM retention not working across functional reset (S32K3xx) Hi @danielmartynek  After fixing to use R2/R3, the application is running. However, RED LED always blinks and GREEN never turns ON, indicating the value is not retained after reset. I’ve applied the startup changes from your shared link, but retention is still not working as expected. S32K3 S32DS-ARM  https://community.nxp.com/t5/S32K/SRAM-ECC-Initialization-for-S32K344/m-p/1764143 Thanks, Yusup
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NXH2004 Evaluation Kit: Bluetooth® 5.3 AoBLE Certified Board details and datasheet Hi Team, Share the details for NXH2004 Evaluation Kit: Bluetooth® 5.3 AoBLE Certified Board details and datasheet for hearing Aid applications. Regards, SK Re: NXH2004 Evaluation Kit: Bluetooth® 5.3 AoBLE Certified Board details and datasheet Hello Sumit, please refer to product pages: https://www.nxp.com/design/design-center/development-boards-and-designs/NXH2004SDK https://www.nxp.com/products/NXH2004 Documentation for WIFI products is accessible under specific conditions. Please ask your customer to contact their sales representative inside NXP. He will assist him directly. Thank you. Have a nice day. Best regards Pavla
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用于处理 S32K144 闪存(P-Flash、FlexNVM、FlexRAM)中 ECC 错误的参考代码 NXP社区的各位朋友,大家好! 我正在S32K144上实现功能安全机制,需要不可纠正(双位)ECC 错误的参考代码,以及注入这些错误进行测试的方法。   1. 双位处理 我需要一些代码示例来捕获以下类型的双比特错误: P-Flash 和 FlexNVM: FlexRAM(EEE):检测后台复制过程中的故障。 异常处理程序:一个 BusFault 或 HardFault ISR 例程,用于隔离故障内存地址。   2. 错误注入 模拟闪存阵列中的双比特故障的推荐方法是什么?   任何代码片段都将不胜感激。 Re: Reference code to handle ECC errors in S32K144 Flash Memory (P-Flash, FlexNVM, FlexRAM) 您好@NJ_NXP , 1. 如果您使用的是RTD驱动器,请参阅S32K1/S32M24x FLS驱动器集成手册(RTD_FLS_IM.pdf),具体而言,是第 10.4.1 节——内部闪存上的 ECC 管理。 该文档位于 RTD 安装目录中,例如 RTD 3.0.0_QLP02 版本: SW32K1_S32M24x_RTD_4.4_3.0.0_QLP02\eclipse\plugins\Fls_TS_T40D2M30I0R0\doc\ 关于 FlexRAM,它没有实现 ECC。但是,如果在向下复制操作期间检测到双位错误,则 EEPROM 记录将被读取为全 1。 更多详情,请参阅应用笔记 AN11983 – 使用 S32K1xx EEPROM 功能: https://www.nxp.com/docs/en/application-note/AN11983.pdf 2. 可以通过设置 FERCNFG[FDFD] 位并执行闪存读取来模拟闪存控制器中的故障。 或者,也可以通过重新编程一个已编程的闪存短语并随后读取它来产生故障。 此致, 丹尼尔
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Reference code to handle ECC errors in S32K144 Flash Memory (P-Flash, FlexNVM, FlexRAM) Hello NXP Community, I am implementing safety mechanisms on the S32K144 and need reference code for non-correctable (double-bit) ECC errors, alongside a method to inject them for testing.   1. Double-Bit Handling I need code examples to catch double-bit faults across: P-Flash & FlexNVM: FlexRAM (EEE): Detecting faults during background copies. Exception Handlers: A BusFault or HardFault ISR routine to isolate the failing memory address.   2. Error Injection What is the recommended way to simulate a double-bit fault in the Flash memory arrays?    Any code snippets would be highly appreciated. Re: Reference code to handle ECC errors in S32K144 Flash Memory (P-Flash, FlexNVM, FlexRAM) Hi @NJ_NXP, 1. If you are using RTD drivers, refer to the Integration Manual for the S32K1/S32M24x FLS Driver (RTD_FLS_IM.pdf), specifically Section 10.4.1 – ECC Management on Internal Flash. The document can be found in the RTD installation directory, for example for RTD 3.0.0_QLP02: SW32K1_S32M24x_RTD_4.4_3.0.0_QLP02\eclipse\plugins\Fls_TS_T40D2M30I0R0\doc\ Regarding FlexRAM, it does not implement ECC. However, if a double-bit error is detected during a copy-down operation, the EEPROM record is read as all 1s. For more details, see application note AN11983 – Using the S32K1xx EEPROM Functionality: https://www.nxp.com/docs/en/application-note/AN11983.pdf 2. The fault can be emulated in the flash controller by setting the FERCNFG[FDFD] bit and then performing a flash read. Alternatively, the fault can be generated by reprogramming an already programmed flash phrase and subsequently reading it. Regards, Daniel
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What's wrong having your own authentication system? So as the title suggests. I have built an app that instead of using a third party authentication I've built my own based on well known libraries and tools (jwt, bcrypt etc etc). I didn't use passport because the only case I would use is the local solution. What's wrong with this? Why people suggest using a third party authentication solution than building one your own?
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DDR Stress Test on custom i.MX8MP board using J-Link Plus V10 Hello, I am bringing up a custom board based on the i.MX8M Plus (MIMX8ML8DVNLZAB) with Micron LPDDR4 memory (MT53E256M32D2FW-046 AIT). I generated the DDR settings with the Config Tools for i.MX and integrated the generated files into U-Boot. During boot I currently receive: U-Boot SPL 2024.04 DDRINFO: start DRAM init DDRINFO: DRAM rate 4000MTS Training FAILED I would like to perform DDR calibration and stress testing. However, my custom board does not have a USB OTG port available, so I cannot use the normal USB HID download method described in the DDR Tool User Guide. I do have: Segger J-Link Plus V10 JTAG access working correctly UART console available Connection to the Cortex-M7 through J-Link is successful In the MSCALE DDR Tool I can only select SERIAL as connection type. I do not see a JTAG option. My questions are: Is it possible to perform DDR calibration and stress testing on an i.MX8MP custom board using a Segger J-Link Plus V10? Is there a JTAG version of the DDR Stress Test Tool available for i.MX8MP? Can the DDR test image be loaded through J-Link instead of USB HID? Is there an alternative procedure recommended by NXP for custom boards without a USB download interface? Thank you for your support. Re: DDR Stress Test on custom i.MX8MP board using J-Link Plus V10 Hello, No we do not offer other kind of sollutions aside from serial download for DDR tunning, we highly recommend customer that for new designs in the initial development to have this interface available. This because for almost all our tools it is a hard requirement. Best regards/Saludos, Aldo.
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LPC553xリファレンスマニュアル:表315 SCT0 信号誤り(SCTIMER) こんにちは、 LPC553xリファレンスマニュアル(Rev.4) 表315「SCT0信号(出力)」をデータシートの表3と比較し、どちらの情報源が信頼できるか尋ねます。 これはLPC553xリファレンスマニュアル、Rev. 4、表315「SCT0信号(出力)」です: この表には、外部ピンが34個記載されています(私の数え方が正しければ)。LPC553xのデータシートをざっと検索しても、ピンは31本しか見つかりません。さらに、表315には、PIO2_2、PIO2_9、PIO2_15、PIO2_30、PIO2_31がSCT0の出力ピンとして記載されています。データシートを見る限り、LPC553xはPIO2_0とPIO2_1のみを実装しているので、このデバイスにはPort-2ピンは存在しません。 さて、データシートの表3を綿密に調べてすべてのSCT0_OUTピンを抽出すると、まったく異なる表が得られます。 SCT0信号(出力)接続先 SCT0_OUT0 PIO0_2、PIO0_17、PIO1_4、PIO1_23 SCT0_OUT1 PIO0_3、PIO0_18、PIO1_8、PIO1_24 SCT0_OUT2 PIO0_10、PIO0_15、PIO0_19、PIO1_9、PIO1_25 SCT0_OUT3 PIO0_22、PIO0_31、PIO1_10、PIO1_26 SCT0_OUT4 PIO0_23、PIO1_3、PIO1_17 SCT0_OUT5 PIO0_26、PIO1_18 SCT0_OUT6 PIO0_6、PIO0_27、PIO1_31 SCT0_OUT7 PIO0_21、PIO0_28、PIO1_19 SCT0_OUT8 PIO0_29、PIO1_13 SCT0_OUT9 PIO0_30 私のデザインでは、データシート表3を真実の情報源として使っています。 お願いします、 データシート(Rev 5.0)の表3がSCT0出力ピンに関する公式の情報源であることを確認してください。 リファレンス・マニュアルの表315が誤りであることを確認してください。 上記の表が正しいことを確認してください。 ありがとう。 ダン Re: LPC553x reference manual: Table 315 SCT0 Signals wrong (SCTIMER) こんにちは、 リファレンスマニュアルに添付されている「ピン機能表」を使って、SCT0_OUT機能に利用可能なピンを特定してください。 よろしくお願いいたします。   Re: LPC553x reference manual: Table 315 SCT0 Signals wrong (SCTIMER) こんにちは、 現時点では、ピン機能表をご参照ください。 私はその情報をチームに伝えます。 敬具、ルイス Re: LPC553x reference manual: Table 315 SCT0 Signals wrong (SCTIMER) こんにちは、 @luis_maravilla さん、 「ピン機能表」をご指摘いただきありがとうございます。リファレンス・マニュアルの中にスプレッドシートファイルが隠されているとは知りませんでした。 「ピン機能表」をざっと見たところ、リファレンスマニュアルの表315の「SCT0信号(出力)」の情報が誤っていることが確認されました。 この情報をドキュメントチームに渡して訂正してもらえますか? ピン機能に関してさらに不一致があるCASE、権威ある情報源はデータシートかピン機能表か教えてください。 ありがとう。 よろしくお願いします、 ダニエル
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哪里可以找到与 DEVKIT-MPC5744P Rev A 相关的资料? 你好, 我发现现有的 DEVKIT-MPC5744P 快速入门指南 (QSG) 似乎只与 Rev B 有关。 此外,目前网站上提供的文档似乎仅适用于 Rev B 版本。 请问能否提供 DEVKIT-MPC5744P Rev A 版本的硬件文档和快速入门指南? 谢谢! Re: Where can I find materials related to the DEVKIT-MPC5744P Rev A? 你好, 这已不再公开提供。所以我已在内部提出申请。 此致 Peter Re: Where can I find materials related to the DEVKIT-MPC5744P Rev A? 你好, 我当时正在和编写这些指南的工程师交谈。 这是他能找到的最早版本。 顺祝商祺! Peter
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NXP MBDTを使用してS32K396BMS-EVB上のMSDI MC33CD1030をLPMモードにする方法 こんにちは、 S32K396BMS-EVBを使ってCD1030にLPMを入力するためのMBDTの参照設定や準備済みモデルが必要です。 サポートしてください。 よろしくお願いします。
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Mac OS Tahoe update LinkServer No Probes found So I updated to Tahoe and the probes were not found when using LinkServer.  So I updated LinkServer to latest but it only works if I go into the directory in terminal and manually run  ./LinkServer probe After that the probe is found and I can use MCUXpresso.  This apparently happens to others as well.   https://community.nxp.com/t5/MCUXpresso-General/LPC-Link2-not-found/m-p/2200131/highlight/true#M5741 This is the error in the IDE when it tries to use LinkServer redlink> ProbeList Error: No probes found I also work at a large company and others who have updated their OS have the same issue and have to do the same thing.   Anyone know of a better fix? Re: Mac OS Tahoe update LinkServer No Probes found Hi @davidinsulet, Unfortunately, that's a current limitation of the LinkServer build that comes preinstalled on the latest version of MCUXpresso IDE. That said, this limitation has been identified and reported with the IDE team so they can correct the LinkServer version on a future release. On the meantime, the workaround that is described on the post you shared is the most effective method of getting around this issue specifically for MCUXpresso IDE. Alternatively, you would also recommend using MCUXpresso for VS Code, which is our newest development platform and doesn't currently have this limitation like the IDE does. Sorry for the inconvenience this may cause. BR, Edwin.
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