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How to obtain the correct Frame Pointer (FP) for DumpCallStack on S32K3 using the GHS compiler? Hi everyone, I am working on an S32K3 MCU using the Green Hills Software (GHS) compiler, and I am implementing a DumpCallStack function. To obtain the frame pointer (FP), I am using the following inline assembly: __asm volatile ("mov %0, r7" : "=r" (locals.fp)); However, the value I get for locals.fp is 0x02B1, which does not appear to be a valid frame pointer. It is not aligned and does not point to a valid stack location, so the call stack cannot be unwound correctly. My questions are: What is the correct way to obtain the current frame pointer when using the GHS compiler on the S32K3 (Arm Cortex-M7)? Does the GHS compiler always use R7 as the frame pointer, or can it omit the frame pointer or use another register depending on the optimization level? Are there any compiler options that must be enabled to preserve the frame pointer for stack unwinding? Is there a recommended GHS-specific API or intrinsic for retrieving the frame pointer instead of using inline assembly? If anyone has implemented stack unwinding or a DumpCallStack function with the GHS compiler on S32K3, I would appreciate any guidance or examples. Thank you! Re: How to obtain the correct Frame Pointer (FP) for DumpCallStack on S32K3 using the GHS compiler? Hi, I would not assume that R7 is always used as the frame pointer. Depending on the GHS version, optimization level, and compiler options, the compiler may use a different register or omit the frame pointer entirely and use R7 as a general-purpose register. The value 0x02B1 suggests that R7 might not be acting as a frame pointer in your build.  Please check the generated assembly and verify whether GHS is creating frame records at all. If frame pointers are enabled, you should see a consistent function prologue saving/restoring the frame pointer; otherwise stack unwinding based on R7/R11 will not be reliable. Since this is primarily a compiler-specific question, I would also recommend contacting Green Hills Software support. They can advise on: Whether GHS uses R7, R11, or another register as the frame pointer for your target/configuration. Which compiler options preserve frame pointers. Whether there is a recommended intrinsic or API for obtaining the current frame pointer. Preferred methods for implementing call stack unwinding with GHS. They are best positioned to provide guidance specific to your compiler version and settings. BR, Petr Re: How to obtain the correct Frame Pointer (FP) for DumpCallStack on S32K3 using the GHS compiler? Sure
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S32K3 Request to support always-on LPI2C Pin Low Timeout monitoring after transfer completion Hi,NXP We attempted to leverage the I2C_MASTER_EVENT_PIN_LOW_TIMEOUT event to implement recovery for a slave device that holds SDA low. During testing, we observed that the pin-low timeout interrupt is turned off once a transfer completes or an abnormal condition is detected. Our expectation is that this interrupt should remain enabled continuously, since real-time monitoring of the bus is required and the timeout interrupt enable must not be cleared at the end of a transfer. We consider the current RTD 7.0.1 handling of the timeout interrupt to be flawed. Could NXP provide an official recommendation or guidance on how to correctly handle this? Best Regards, xianlong Re: S32K3 Request to support always-on LPI2C Pin Low Timeout monitoring after transfer completion Hello @wuxianlong , Thank you for the detailed description and for pointing to the driver code. Your observation is correct: in the current RTD implementation, LPI2C_IP_MASTER_PIN_LOW_TIMEOUT_INT is enabled as part of the master transfer interrupt handling and it is disabled again when the master transfer is ended. This means that the RTD driver does not keep this interrupt enabled as a permanent bus-monitoring mechanism after transfer completion. From the hardware point of view, the S32K3 LPI2C module supports the pin-low timeout feature. The timeout threshold is configured by MCFGR3[PINLOW], and the MSR[PLTF] flag can be set when the selected SCL or SDA line remains low longer than the configured threshold. The reference manual also states that this flag can be set even when the LPI2C controller is idle. However, this hardware capability does not necessarily mean that the RTD driver keeps the corresponding interrupt enabled continuously. The current RTD implementation appears to manage this event in the context of an active master transfer. For continuous I2C bus monitoring after transfer completion, the recommended approach is to handle this at the application level, for example by checking the MSR[PLTF] status as part of the bus recovery logic. Please also note that the pin-low condition itself must be resolved by software. The PLTF flag cannot be cleared while the low condition is still present, and it must be cleared before a new START condition can be generated. Best regards, Pavel
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Ara240 Module Bring-Up on FRDM-IMX95-PRO Getting Started Video: (function() { var wrapper = document.getElementById('lia-vid-6403214335112w960h540r398'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos) This guide provides step-by-step instructions on how to verify successful communication and the runtime software environment to interface with the Ara240 module with the FRDM i.MX 95 Pro development board. Out of the Box: Get Familiar with the Ara240 Module Ara240 Module [Back view]Ara240 Module [Back view] Ara240 Module [Top view]Ara240 Module [Top view]         Connecting the M.2 Module This section explains how to connect Ara240, a discrete module, to the FRDM i.MX 95 Pro development board. The instructions in the FRDM i.MX 95 Pro Getting Start Guide will walk you through the boot-up process for the pre-loaded Embedded Linux image on the board and how to connect the USB debug cable. For additional details, see the official FRDM i.MX 95 Pro Development Board documentation. References: FRDM i.MX 95 Pro Quick Start Guide FRDM i.MX 95 Pro Development Board product page  FRDM i.MX 95 Pro Getting started page Getting Started with ARA2-M2-16G-GT Follow the steps below to connect the Ara240 module to the FRDM i.MX 95 Pro development board: Spoiler (Highlight to read) Important: Ensure the board is powered off before making any connections. Important: Ensure the board is powered off before making any connections. Insert the Ara240 module into the M.2 Key-M socket on the FRDM i.MX 95 Pro development board. Using the screw provided, secure the module. Connect the fan cable to the board’s fan header (refer to the FRDM i.MX 95 Pro board documentation for the exact header location). "How to connect two Ara240 devices?" The figure below illustrates the connection of Ara240 devices to the two M.2 Key-M slots on the FRDM i.MX 95 Pro development board. You can install one Ara240 device in either slot or connect two devices simultaneously by using both slots. Connect the Ara240 to the FRDM i.MX 95 Pro development board.Connect the Ara240 to the FRDM i.MX 95 Pro development board. Power on the Board Follow the instructions to power on (boot) the board found in the Getting Started with FRDM-IMX95-Pro. After powering on, verify that the fan and green LED indicators Ara240 module are on are on. Get the Software This section will walk you through the Ara240 Runtime software development kit (SDK), a streamlined subset of the Ara240 SDK designed for rapid enablement and execution on NXP platforms. The Runtime SDK simplifies installation and configuration, enabling developers to quickly deploy and run AI/ML workloads on the Ara240 module with minimal effort. Overview Refer to Ara240 software release notes for details on the Ara240 software development kit (SDK) The Getting Started page for Ara240 only outlines usage on specific i.MX development platforms For any other platforms please reach out to your NXP representative for guidance. Spoiler (Highlight to read) Q2'26 BSP (L6.18.20-2.0.0) onwards runtime environment for i.MX 8MP and i.MX 95 boards is packed with Linux BSP. Q2'26 BSP (L6.18.20-2.0.0) onwards runtime environment for i.MX 8MP and i.MX 95 boards is packed with Linux BSP.     Module Enumeration and Software Configuration This section provides instructions to verify proper installation of Ara240 module and configuration of the Ara240 Runtime SDK on the FRDM i.MX 95 Pro development board. Verify Device Detection Once the board has successfully booted, connect to the serial debug port to monitor system logs. To confirm that the Ara240 module is being detected by the board, run the following command: $ lspci | grep 1e58 Expected output: 0000:01:00.0 Processing accelerators: Device 1e58:0002 (rev 02) Enable Ara240 device For quick enablement, the Ara240 Runtime SDK starts at boot time. Refer to the Ara240 Runtime SDK documentation for detailed instructions and environment setup steps. Spoiler (Highlight to read) Q2'26 BSP (L6.18.20-2.0.0) onwards runtime environment for i.MX 8MP and i.MX 95 boards is packed with Linux BSP. Q2'26 BSP (L6.18.20-2.0.0) onwards runtime environment for i.MX 8MP and i.MX 95 boards is packed with Linux BSP.     Developer Experience This section provides an overview of Ara240 runtime software enablement using the FRDM i.MX 95 Pro development board. Verify Setup Environment Use the following guidance on how to connect required devices. For most of the demos, you would need a camera, keyboard, mouse, internet connection and a HDMI display monitor. Setup preparation for FRDM i.MX 95 Pro boardSetup preparation for FRDM i.MX 95 Pro board Spoiler (Highlight to read)  NOTE: You might need to use a USB hub to connect keyboard, mouse and camera at the same time.  NOTE: You might need to use a USB hub to connect keyboard, mouse and camera at the same time.   Runtime setup Description Runtime SDK delivers a complete runtime environment that enables AI/ML acceleration on the Ara240 module. To run demo applications, ensure that the Ara240 bring-up process has been successfully completed and the system is ready for demo evaluation. Refer to the Runtime SDK documentation for detailed guidance on: Verifying correct installation of the Runtime SDK. Checking and updating the Ara240 firmware version. Validating proxy service bring-up status. Executing benchmark tests on Ara240. Following these steps ensures that the module is properly initialized and ready for use. Ara240 supports the execution of CNNs, LLMs, VLMs, and agentic frameworks, enabling advanced AI workloads to run directly on Ara240. For comprehensive examples and end-to-end workflow guidance, please refer to the Ara SDK documentation page. Ara240 Demos Henceforth Q2'26 Linux BSP, GoPoint can be launched to explore preselected Ara240 demonstrations included in the NXP provided Linux Board Support Package. User Guide: GPNTUG: GoPoint for i.MX Applications Processors User Guide  FRDM-IMX9
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S32K3 FS26 new WDG period not work Hello, On my board, after power‑on reset, I configure the FS26 watchdog period to INFINITE during initialization. Then I exit DEBUG mode and enter NORMAL mode (the value read from SBC_FS26_FS_STATES_ADDR is 0xB). After that, I change the watchdog period to 64 ms (as shown in the screenshot), perform one watchdog refresh (feed), and the return value indicates success. WD_RFR_CNT increases by 1, and reading SBC_FS26_FS_WDW_DURATION_ADDR gives 0xB0CD, confirming that the period has been successfully updated to 64 ms. However, if I stop feeding the watchdog after this point, no error or reset occurs. In contrast, if I configure the watchdog period to 64 ms during initialization , then after exiting DEBUG mode, not feeding the watchdog does cause a reset as expected. Why does the watchdog not take effect when the period is changed from INFINITE to 64 ms in NORMAL mode, even though the register write and the refresh both succeed? S32K344 RTD7.0.0 FS26 6.0.0 S32DS3.6.4 EB30.0 BR, Jason Re: S32K3 FS26 new WDG period not work Hello, Oh! I forgot to switch accounts when replying – Jason07 is my another account. BR, Jason Re: S32K3 FS26 new WDG period not work Hello, Thank you very much for your reply. The reason I set the watchdog period to INFINITE during initialization is that, according to the driver code, certain operations are only performed when the period is INFINITE – for example, closing INIT_FS during the execution of the Sbc_fs26_InitDevice() function, and calling Sbc_fs26_WdRefresh inside Sbc_fs26_ClearFaultErrorCounter to clear the fault error counter. If I set the period to a finite value,  Sbc_fs26_WaitFailsafeRelease return E_NOT_OK inside Sbc_fs26_FsxbRelease, and the FS26 stays in the FS_STATES_FS0B_ASSERT state, unable to transition to FS_STATES_NORMAL_FS. BR, Jason Re: S32K3 FS26 new WDG period not work Hello, The watchdog does not become active because it was disabled when INIT_FS was closed. Configuring WDW_PERIOD[3:0] = 0000 selects the Infinite Open Window. According to the FS26 watchdog specification, the watchdog window can be disabled only during the initialization phase, and the disabling becomes effective when the initialization phase is closed. A watchdog disabled in this way cannot subsequently be enabled in NORMAL mode by writing a finite value to FS_WDW_DURATION. The successful register readback confirms that the new WDW_PERIOD field was written, and the incremented WD_RFR_CNT confirms that the refresh was accepted. These observations do not indicate that watchdog timeout monitoring was re-enabled. Runtime period changes are supported when the watchdog was enabled with a finite period during initialization. Therefore, configure a finite watchdog period during INIT_FS, for example the maximum finite period of 1024 ms if a long initialization interval is required. After entering NORMAL mode, the period can be changed to 64 ms. The new finite period becomes effective after the next watchdog refresh. This behavior also explains why the reset occurs when 64 ms is configured during initialization: in that case, the watchdog is enabled when INIT_FS closes. From safety perspective, infinite state is reached by watchdog disable, as the compare is in HW and flag will always rise on match. Best regards, Peter Re: S32K3 FS26 new WDG period not work Hello, Based on the observed behavior, the FS26 watchdog monitoring does not appear to start after changing WDW_PERIOD from Infinite Open Window to 64 ms in NORMAL_FS. The register write is successful, as confirmed by the readback value (0xB0CD), and watchdog refresh commands continue to be accepted, as indicated by WD_RFR_CNT incrementing. However, the absence of any watchdog timeout reaction after refreshes are stopped indicates that watchdog supervision itself is not active. When the watchdog period is configured as Infinite Open Window, Sbc_fs26_NormalFSSequence() closes INIT_FS by issuing an immediate watchdog refresh. Likewise, Sbc_fs26_ClearFaultErrorCounter() clears the fault error counter using consecutive watchdog refreshes because there is no watchdog window timing restriction in Infinite mode. When a finite watchdog period is configured, the driver follows a different path. Watchdog refreshes must be synchronized with the valid watchdog window, and the driver uses the watchdog timing mechanism (pfWdgNotification, timer synchronization, and Sbc_fs26_TimeWaitClearFault()) instead of issuing consecutive immediate refreshes.
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Please help renew my S32DS5.5 license Hi team, My S32DS5.5 license expired but i still need it for some old projects. Please help me renew it. Thank you! BR, Joaquin
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IGGM Points System & Rules Explained | How to Earn Points, Redeem And More? To provide players with more cost-effective gaming products and services, IGGM platform has officially launched a brand-new points system, designed to let you enjoy a superior shopping experience while spending less!   Below, we break down everything you need to know: how to earn points efficiently, use them for discounts or to redeem exciting rewards, and stack VIP benefits to maximize your savings.   Before Using the Points System - Registration Required   Please note that IGGM's new points system is available only to new-registered and logged-in users. If you haven't registered or logged in yet, you will need to do so to access Check-in and Points pages.   How to Earn Points?   Accumulating points at IGGM is simple and straightforward, primarily through two channels: daily check-ins and order rewards.   1. Daily Check-in   Simply click the "Check In Today" button on the IGGM Check-in Center page to complete your check-in; once the button changes to "️Checked In (Come back tomorrow)," your points have been successfully credited! Alternatively, you can also check in by clicking the current date on the calendar.   One-tap check-in (Easter egg)   There's a little Easter egg here! If you forget to check in for the day and land straight on the coupon redemption page, just tap the "little rocket" emoji at the bottom of the list to check in instantly - no need to navigate back to the Check-in Center. You'll still get those incremental rewards for consecutive check-ins.   Please note the visual differences between PC and mobile versions! For PC users, the small rocket only begins to shake and emit flames when you hover your cursor over it; a single click launches the rocket and credits your check-in points. For mobile users, the rocket icon shakes continuously—simply tap it to check in and earn your points instantly!   Other Check-in Entry   In addition, IGGM provides the following access points for quick and convenient daily check-ins:   1. Click "Go Now" on the coupon redemption page to visit the check-in center.   2. Click the coupon section at the bottom of the homepage to access the check-in center.   3. Click the banner at the bottom of any product page on IGGM to access the check-in center.   Incremental Rewards for Consecutive Check-ins   IGGM's check-in system rewards consistency. If you check in without interruption, your daily points will increase over time: 5 points on the first day, 6 points on the second, and 8 points on the third. From the fourth day onwards, as long as you maintain your streak, you will consistently receive the maximum reward of 10 points per day.   Notes: If you check in via the check-in banner on the product page during your shopping journey, you can return to your original page via Back Shopping at the bottom after completing the check-in and triggering the points accumulation. You don't have to worry about your shopping progress being affected!   Reset Upon Interruption   If you miss a day or break your streak for any reason, your progress will reset to zero. Your next check-in will start back at the Day 1 rate of 5 points. Please note that the daily check-in reset is based on the server's time zone; be sure to check in on time to avoid losing progress due to network issues or other interruptions.   2. Points for Orders   Additionally, whenever you make an order on the IGGM platform, the system will award you points based on your subtotal amount.   Point Accrual Rate: $1 = 1 Point   Under standard conditions, every $1 of your actual spending converts directly into 1 point. To simplify calculations for order amounts involving decimals, IGGM rounds to the nearest whole number when determining the points earned. For example, if you pay $17.35, you receive 17 points; if you pay $34.86, you receive 35 points.   To ensure system efficiency for small transactions, the subtotal amount paid for an order must be at least $1 to trigger point accrual; orders under $1 do not generate any points.   Furthermore, points for all orders will be automatically credited to your account by the system only after the order status has officially changed to "Completed"; the number of points corresponds to the amount of the qualifying purchase.   New User Perk: 10x Point Rewards   IGGM has a welcome gift for new users! Your first paid order on IGGM automatically qualifies for a generous 10x points reward (meaning you earn 10 points for every $1 spent).   Please note the calculation method: the subtotal amount is first rounded to the nearest whole number, and then multiplied by 10 to determine the points for your first order. For example, if your first order's subtotal is $17.35, you will receive 170 points ($17.35 → 17 × 10 = 170 points), rather than multiplying by 10 first and then rounding ($17.35 × 10 = 173.5 → 174 points).   However, if your first order's subtotal is less than $1, you will not receive any points, and your first-order privilege as a new user will be used up. Therefore, IGGM recommends buying higher-value items you need during your first order to make the most of the 10x point reward.   Due to the significant value of this offer, points for the first order will be credited after the order is successfully delivered and passes a security review, provided no refund occurs within 24 hours.   You can view the specific points added upon completion in the My Account → My Orders section of IGGM.com. If you have just completed a payment but do not see the points immediately, please do not worry - simply wait a short while.   Point Value and Validity   Understanding the value of your points helps you make the best use of them. In the IGGM point system, 100 points = $1 (meaning each point is worth approximately $0.01).   Please note that points are not valid indefinitely; each point expires 90 days from the date it was earned. IGGM employs a user-friendly rolling expiration policy: points earned on Day 1 will expire at the end of Day 91. The specific calculation time for rolling expiration depends on the time zone of your account's IP address.   You can check for notifications regarding points nearing expiration on the "My Points" page of your account at any time to ensure you don't miss out on benefits.   Multiple Ways to Use Points: Direct Cash Deduction and Coupon Exchange   When buying items on IGGM, you can choose to use your accumulated points to directly offset the cash cost of your order or exchange them for significant discounts at IGGM Coupon Redemption Center. The choice is entirely yours!   Option A: Direct Cash Deduction at Checkout   On the checkout page, you can use the points in your account balance to reduce the cost of your current order. However, to maintain the integrity of the IGGM points system, the proportion of the order total that can be offset by points is directly linked to your order subtotal.   Please refer to the table below for specific deduction ratios based on order subtotal ranges:   Order Subtotal Range Max Point Deduction Ratio $1.00 - $9.99         5% $10.00 - $49.99         8% $50.00 +                10%   Important notes on using points for cash deductions:   1.Points are awarded only for successfully completed orders; orders that are voluntarily cancelled, flagged for suspected fraud, or fully refunded are not eligible for points;   2.Points for your first order are not credited immediately; they will be issued within 24 hours after successful delivery, provided no refund has occurred;   3.If an order involving points undergoes a partial refund, the system will deduct the corresponding points (rounded based on the refund amount) and return any points that were consumed. Returned Consumed Points = Consumed Points × (Refund Amount / Subtotal Amount);   4.Points can be used in conjunction with VIP discounts;   5.Cannot be used in conjunction with discount codes or cash coupons;   6.Cannot be exchanged for cash;   7.Cannot be withdrawn as cash;   8.Cannot be transferred between accounts;   9.IGGM.com reserves the right of final interpretation for all points-related policies.   Option B: Redeem Discount Codes or Cash Coupons   You can also visit the points redemption page to exchange points (in tiers ranging from 100 to 500 points) for discount codes (various rates) or cash coupons (subject to minimum order requirements). For example, the $10 cash coupon can only be used if your order's subtotal amount is $100 or more. If your subtotal is less than $100, the coupon will not automatically appear at checkout.   Points Spent Discount Code Cash Coupon (Min. Order Req.) 100 3% $1 (Order ≥ $10) 200 4% $3 (Order ≥ $30) 300 5% $5 (Order ≥ $50) 400 8% $8 (Order ≥ $80) 500 10% $10 (Order ≥ $100)   All discount codes and cash coupons are limited to 30 per week, first come, first served! Different colors clearly indicate the current stock status: green for 21-30 remaining, orange for 11-20, and red for 1-10. When stock reaches zero, it will display "Out of stock." But don't worry, just come back next week!   By the way, if you forget to check in for the day, the little rocket emoji on this coupon page is your quick way to do so! With a simple tap, a shake of the little rocket, and your points are in the bag!   While coupons are great, please keep in mind that all discount codes or cash coupons are valid for only 3 days. Redeem them carefully and ensure the items you wish to buy are in stock to avoid wasting your points.   You can view your coupons and their current expiration status on the My Account → My Coupons page.   Note: You can quickly access the coupon redemption page via the "Coupon Center" at the bottom of the IGGM homepage. We recommend bookmarking this page for convenient future check-ins and redemptions - saving you time and effort.   Notes on Points Redemption Coupons:   1.Each reward is limited to the first 30 users per week on a first-come, first-served basis.   2.All discount codes and cash coupons require CF verification upon redemption.   3.Redeemed discount codes/cash coupons are valid for 3 days from the time of claim.   4.Only one discount code/cash coupon can be used per order. They cannot be combined with VIP discounts or points deductions.   5.Discount codes/cash coupons are not valid for gift cards and top-up services.   6.Redeemed discount codes, cash coupons and free orders cannot be returned or exchanged once claimed.   7.IGGM.com reserves the right of final interpretation.   Hidden Option C: Direct Exchange for In-Game Currency/Items (Coming Soon)   In addition to coupons, IGGM will soon add options to the redemption page allowing you to exchange points directly for specific in-game items, such as Monopoly GO cards, Diablo 4 materials, or POE 1/2 currency.   Once you meet the points requirements and click to redeem, a pop-up window will prompt you to enter the necessary delivery details for the game. After accurately filling in the information and completing the verification, the system will automatically generate a free order and display it in Coupon Order list; you just need to wait for it to be delivered safely. More point redemption features and options are coming soon - stay tuned!   If you encounter errors during the redemption verification process, please check your network connection and try again using a reliable VPN.   Furthermore, given the nature of virtual items, returns or exchanges are not possible once an order begins processing; however, if delivery fails due to issues on the IGGM platform, the points used will be fully refunded.   VIP Ranks & Benefits   For VIP members, IGGM offers tiered discounts to all users based on accumulated spending. Once your cumulative spending hits a specific threshold, you automatically unlock a permanent VIP discount:   VIP 1: Your Spending (<$1,000), Get a 1% discount.   VIP 2: Your Spending (≥ $1,000 and < $3,000) , Get a 2% discount.   VIP 3: Your Spending (≥ $3,000 and < $6,000), Get a 3% discount.   VIP 4: Your Spending (≥ $6,000 and < $10,000), Get a 4% discount.   VIP 5: Your Spending (≥$10,000), Get a 5% discount.   Discount Stacking Rules:   VIP Discounts CAN be combined with Points Deductions. VIP Discounts CANNOT be stacked with Discount Codes or Cash Coupons.   At checkout, you may apply either:   Option A: Discount Code or Cash Coupon (Alone) Option B: VIP Discount + Points Deduction (Note: Discount Codes and Cash Coupons are not valid for Gift Cards or Top-up services.)   Stacking Discounts and Maximizing Savings   How can you get the most savings when checking out? IGGM has designed a smart checkout system based on our VIP ranks and point-redemption rules.   At IGGM, VIP discounts stack perfectly with direct point deductions. However, please note that redeemed discount codes or cash coupons cannot be combined with VIP discounts or point deductions. Additionally, only one coupons may be used per order.   At checkout, the system automatically compares the final costs of "Option 1 (VIP Benefits + Direct Point Deduction)" and "Option 2 (Single Discount Codes or Cash Coupons)" to select the most cost-effective choice for you, saving you the trouble of manual calculations. Which option offers the best deal will be displayed next to that option (Best Value). Of course, if you have your own preferences regarding coupon and point usage, you are free to select your preferred discount method.   Refunds and Point Returns   IGGM's refund policy allows you to request a refund at any time prior to the completion of delivery. However, we have specific rules regarding the refund and rebate of your points in this situation:   Situation 1: Full Refund   If you cancel your order for personal reasons, orders suspected of fraud or requiring a full refund will not be awarded points; furthermore, points already used in such orders will not be refunded.   However, if a full refund is issued due to reasons attributable to IGGM, the points consumed for the order will be fully refunded to your account.   Situation 2: Partial Refund   If an order involving awarded points undergoes a partial refund due to special circumstances, the system will refund a portion of the consumed points on a pro-rata basis relative to the refund amount. Naturally, the points rebate you would have originally received upon order completion will also be adjusted; the corresponding points will be deducted based on the refund amount, with the figure rounded to the nearest whole number.   Here is the formula for calculating point returns during a refund:   Returned Consumed Points = Consumed Points × (Refund Amount / Subtotal Amount) Deducted Earned Points = Subtotal Amount - Refund Amount (rounded to the nearest whole number)   The all-new IGGM member point system is designed to offer you more viable discount options for your long-term gaming purchases. Every point accumulated is a sincere token of our appreciation for your support.   Log in to your IGGM account now, visit the Check-in Center to start accumulating points, and experience a smarter, more rewarding checkout process like never before!   Frequently Asked Questions about IGGM Points System   Q1: Can I transfer my VIP 5 perks from my old account to a newly created account and start accumulating check-in points there?   A: No. To ensure account security and platform fairness, VIP tiers and points are treated as exclusive assets of an individual account. According to our system security rules, transferring, merging, or gifting perks across different accounts is strictly unsupported.   Q2: My account currently has 277 points. If I buy items worth $34.68 and use up all my points to get a $2.77 deduction, but later receive a partial refund of $15.44 due to certain factors, how many points will I end up with?   A: Your original $34.68 order generates 35 points based on rounding. Due to the partial refund of $15.44, the system will proportionately deduct 15 points (rounded to the nearest whole number). Therefore, the net points earned from this purchase will be: 35 - 15 = 20 points. Additionally, the system will return the points you consumed. Based on the calculation formula: Consumed Points × (Refund Amount / Total Purchase Amount), you will get back 123 points. As a result, your final account balance will be 123 + 20 = 143 points.   Q3: Can I create unlimited new IGGM accounts and place small orders to exploit the 10x points newcomer reward?   A: No. IGGM strictly prohibits the malicious registration of multiple accounts, utilizing technical exploits, or engaging in order manipulation to farm newcomer benefits. Our system is equipped with rigorous anti-fraud and risk control mechanisms: the 10x points multiplier for the first order will only be credited after the order is successfully delivered and passes a 24-hour anti-abuse system review. If the risk control system detects multi-account farming linked by the same IP, same device, same payment method, or malicious account associations, the platform reserves the right to permanently ban the related accounts and clear all accrued benefits.   Q4: I just registered an account and my first order was a small item for $0.9. Because it was under $1, the system didn't give me any points. Then, my second order was for $100. Why didn't my second order get the 10x points? My first order didn't receive any points anyway, shouldn't this second order count as my actual "valid first order"?   A: No. The system strictly identifies the "New User First Order" based on the very first paid order under your account, regardless of the transaction amount. The threshold ruling out points for subtotals under $1 is a foundational platform policy. Therefore, we highly recommend that new users consolidate their shopping carts on their first purchase and bundle higher-value items into the first order to fully maximize the value of the 10x points perk.   Q5: If a website error prevents me from checking in for the day, causing my check-in streak to break, what measures will IGGM take to compensate for my points loss?   A: We sincerely apologize for any inconvenience caused. The daily check-in resets based on a specific time matching the server's time zone. If the streak is broken due to network latency or missing the refresh window, the system will strictly execute the automatic reset policy. We recommend completing your check-in as early as possible each day and ensuring a stable network environment. If the interruption is conclusively caused by a large-scale server outage on the platform, an official site-wide points compensation announcement will be issued once resolved. Please note that support agents do not have the authorization to manually alter individual check-in histories. Thank you for your understanding.   Q6: I spent 300 points to redeem a $5 cash coupon, but the game items I wanted have been out of stock on the platform for the past few days. As a result, the coupon expired within 3 days without being used. The stockout is the platform's issue, so why should my 300 points be deducted for nothing?   A: We apologize, but once a reward is redeemed at the Rewards Center, the corresponding points will be deducted and cannot be refunded. Because each reward is strictly limited to the first 30 users per week on a first-come, first-served basis, and the cash coupons are valid for 3 days, we highly recommend verifying current product stock and your purchase intent before making a redemption to avoid accidental cash coupon expiration.   Q7: Can I still request a refund if my order status is "Completed"? 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关于S32k144的pwm频率会周期变化的问题 我现在在开发nxp的s32k144遇到一个问题,我使用eb配置工具,我配置好了FTM0的四个通道输出,并且再代码中调用了PWM_Init();setdutycycle(8129);我在配置中选择的是中心对齐模式,不启动死区,也不和别的通道绑定,并且周期设置的是0.00125,每个通道都是独立模式,得到的是250us,占空比20%的方波,这显然不对,我希望是25%才对,所以我后面换了一下占空比为setdutycycle(16339),但是这个得到的结果是波形不对,通道变成了由150us周期66占空比的方波和100us周期为50占空比的方波交替出现,请问这是为什么?这是我的实际波形; 事实上可以看出我这里有两个问题:1、为什么我的pwm占空比设置会有偏差;2、为什么我的pwm周期在不断地变化? Re: 关于S32k144的pwm频率会周期变化的问题 Hi 请告诉我你测试的是哪个版本的Real-Time Drivers for S32K1还是之前哪个版本的AUTOSAR MCAL for S32K1 devices? 请注意,MPC5xxx 和 S32K1xx 器件的 MCAL 已停止支持。如需进一步支持,需经市场团队批准,请联系您的恩智浦销售人员寻求帮助。 Best Regards, Robin Re: 关于S32k144的pwm频率会周期变化的问题 我不清楚你使用的哪个版本软件,但需要注意设置Loading Point,参考以下两个讨论: Changing FTM_PWM period and duty cycle S32K116 PWM输出问题
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S32K3 fast standby wake up fail Hello, In a Fast Standby example project, I defined an array arr in the .standby_data section, but this array is not used anywhere in the code. However, if I comment out this array definition, the device fails to wake up from Fast Standby; if I keep it, wake‑up works as expected. Moreover, I noticed that the optimization level also affects the behavior: with -O0 optimization, wake‑up fails, but changing to -Os makes it work. Why does defining a variable in the .standby_data section affect the wake‑up functionality? And why does the optimization level have such an impact? S32K312 RTD400 S32DS BR, Jason Re: S32K3 fast standby wake up fail Hi@Senlent Thank you very much for your reply. After changing the address to 0x20408000, the previously failing cases are now working properly. By the way, regarding my other thread (S32K3 ADC Optimize DMA Streaming), I replied to you using the new account(Jason07) registered with the company email – I forgot to switch accounts when replying. Re: S32K3 fast standby wake up fail Hi@Jason22 Whether you comment out the "arr" array in your program affects the value of __BSS_SRAM_START, which will be used as the initial value of the MSP after a fast wake-up. If this value is too small, it can cause a stack overflow. In our example project, we recommend setting this value to 0x20408000, which is the end address of the standby RAM.
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S32K358 config tool dma has no DMA_IP_HW_INST_1 1. S32DS 3.6.10 2. chip S32K358 3. RTD: 7.0.1 problem: dma emux has no instance 1 ,just instance 0 this chip should have two instance of dma mux, but now the config tool just one. I want to use LPUart4 DMA,but it is in mux1. Someone give me a help. Re: S32K358 config tool dma has no DMA_IP_HW_INST_1 Hi, There is a single DMA module with 32 DMA channels and two DMAMUX instances. Each DMAMUX instance provides 16 channels and is mapped to half of the DMA channels. As the LPUART4 TX request is routed to DMAMUX1, you need to use DMA channels 16-31.   The DMAMUX configuration is handled in the RM component, so please add the RM component to the project and configure it accordingly. BR, Petr
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Request for Bare-Metal Driver Code Examples for LX2082 Processor I am currently working on a project based on the NXP LX2082A processor (custom board) and am looking for bare-metal software examples to accelerate our development. Could you please provide or direct me to any available bare-metal reference code, driver examples, or application notes for the following peripherals on the LX2082 processor? UART I2C SPI Ethernet (MAC/PHY initialization and communication) Specifically, I am interested in: Peripheral initialization sequences Register-level driver implementations Example source code in C Bare-metal examples without an operating system Any available board support package (BSP) or reference projects for the LX2082 platform If these resources are available under an NDA or require special access, please let me know the necessary procedure to obtain them. Thank you for your time and support. I look forward to your response. Best regards, sai chandu
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S32k344 design studio driver example code Hi Team  I wanted to run basic example codes on S32k344.  I have installed  S32 Design Studio for S32 Platform Version: 3.6.0 Build id: 241128 I am unable to find any diver examples in . I even with S32k extension and update to update s32k3xx package but the installation fails every time. It is stuck at 70%. Please let me know if you require any other information and help with basic examples. Regards Gopal Re: S32k344 design studio driver example code Hi @rathi_tg  To get started, we recommend using the latest version of the tools available, which is currently S32 Design Studio 3.6.10. There is no need to install it as a separate instance, as it can be installed as an update to your existing installation. Detailed instructions for this process can be found in the S32 Design Studio 3.6.10 RFP Installation Guide, which is available on the same download page as the S32DS installer. Regarding examples for S32K3 devices, these are included as part of the RTD packages. A good reference is the video How To Download, Install and Configure the RTD 5.0.0 with S32 Design Studio 3.6.0, which explains in detail what components need to be downloaded, how to install them, and how to create a project based on example. Although the video was created for RTD 5.0.0, the procedure is similar for newer RTD releases. Note: The latest RTD release available for S32K3 devices is RTD 7.0.1. Additionally, you may find useful examples and application projects in NXP's Application Code Hub, which contains a variety of ready-to-use examples for different devices and use cases. BR, VaneB Re: S32k344 design studio driver example code Hi   I have successfully imported the driver files and i have imported "Siul2_Dio_Ip_Example_S32K344" project. i have run the mex and updated the code. the code is built without any error. I have S32k344-WB with me which when powered on has a default switch and led program.  When I flash my built file the progress bar shows 100% but  i am unable to see any changes in the board behavior it is still executing the old code.  Regards  Gopal  Re: S32k344 design studio driver example code Hi @rathi_tg  How did you determine that the application is running old code? Also, please note that the example projects are tested with specific boards, which are listed in the description.txt file included with each example. Because different boards can have different hardware configurations, please verify that the pin assignments and configurations match your target board. You may need to update some of the pin settings accordingly to ensure the example works correctly on your hardware. Re: S32k344 design studio driver example code Hi @Valval  The issue got resolved i did not install the debug package  . Regards  Gopal
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I need RTM 1.5 package for S32 Power architecture Design Studio Project I am working on MPC5746 Target project using S32 Design Studio 2.1. While importing i am facing issue w.r.t Project was created using SDK_S32_PA_15 which is not installed. If i try to forcefully convert the project, i am facing compilation errors in CPU.h files. Please provide a compatible package. Re: I need RTM 1.5 package for S32 Power architecture Design Studio Project Hello, The SDK_S32_PA_15 is also known as S32 SDK 3.0.3. You can install this SDK into S32 Design Studio for PA v2.1 using the S32DS Extensions and Updates menu. This menu is located by: Help -> S32DS Extensions and Updates   If this package is installed correctly, then you shouldn't receive this error message.  Best regards, Peter
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Zephyr UAC2 → SAI reference on i.MX RT1020 Hi everyone, I'm trying to get a USB-to-I2S audio pipeline working on the i.MX RT1020 using Zephyr's UAC2 asynchronous explicit feedback sample, but I'm running into issues with the NXP SAI (I2S) driver and eDMA. Before I spend more time debugging DMAMUX and IRQ configuration, does anyone know of a working USB-to-I2S example for the RT10xx series using Zephyr? I'm particularly looking for any reference project that implements a UAC2 to SAI audio path on Zephyr. Thanks in advance! Re: Zephyr UAC2 → SAI reference on i.MX RT1020 Hi @lpc73 , Thanks for your interest in NXP MIMXRT series! There is currently no ready-made UAC2→SAI reference project for the RT10xx in upstream Zephyr. The building blocks are all supported on RT10xx: the SAI/I2S driver (nxp,mcux-i2s), eDMA, and the UAC2 class. DMAMUX routing is done via the devicetree properties nxp,tx-dma-channel / nxp,rx-dma-channel + pinctrl, not manually in C. The main piece you'll need to add is the feedback loop for the RT platform, and be sure to place DMA audio buffers in non-cacheable memory. If Zephyr isn't mandatory, the MCUXpresso SDK's dev_audio_speaker + sai_edma_transfer are the most mature ready-to-use UAC2→SAI examples. Best regards, Gavin
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CircO2 Nitric Oxide Tablets Review: A Complete Buyer's Guide CircO2 is a nitric oxide support supplement made by Advanced Bionutritionals. Unlike a lot of pills you swallow with water, CircO2 comes in a quick-dissolving tablet (sometimes called a lozenge) that melts in your mouth. This is one of the things that makes it stand out from other CircO2 Tablets on the market. The main idea behind CircO2 Oxygen Booster and Circulation Support is simple: help your body make more nitric oxide, so your blood vessels can relax and widen. When that happens, blood (and the oxygen it carries) can move more freely through your body. That can mean more energy, warmer hands and feet, and better stamina during the day.  
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Request for NXP V2X Evaluation Board and Design Files Dear NXP Team, We are evaluating V2X communication solutions for an automotive application supporting V2V, V2I and V2P safety messages. We are interested in NXP’s RoadLINK/SAF5400-based V2X solution and the OrangeBox platform. Kindly provide the following information: Recommended NXP V2X evaluation board or reference platform Evaluation-board ordering part number SAF5400 availability and lifecycle status Reference schematic and hardware design files Bill of materials and PCB layout guidelines RF matching and antenna reference design Hardware user manual and software development kit BSP, drivers and example applications Functional-safety documentation, including ASIL-B support details Security-device recommendations for V2X message signing and verification NDA procedure for accessing controlled technical documents Our intended application is an automotive V2X communication unit operating in the 5.9 GHz band. Please also confirm whether NXP currently offers a solution supporting DSRC/IEEE 802.11p, C-V2X PC5, or both. Kindly share the applicable product documents, commercial contact details and procurement process. Best regards, Renjith Thomas Senior Design Engineer - HW Get My Solutions +91 8015237416 Re: Request for NXP V2X Evaluation Board and Design Files Hello, Hope you’re doing well. This is our DSRC Safety Modem product catalog for automotive V2X applications: DSRC Safety Modem. You can also find our recommended Products for V2X Communications here. The RoadLINK SAF5400 is an automotive-qualified single chip DSRC modem for V2X applications, compliant with IEEE 802.11p, IEEE 1609.4, ETSI EN 302663, ETSI EN 302571, and ARIB T-109M. I'm sorry for the inconveniences this may cause, but, unfortunately, information about the SAF5400 and other V2X Automotive Products is protected under a Non-Disclosure Agreement. To obtain information about these products, could you please contact your Local Distributor from the Distributor Network so they can not only help you with the NDA process but also provide you the information you might need of those products? Best regards, Ana Sofia.
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GPIO wakeup triggered by short noise pulses during suspend Hi NXP team, We are using i.MX8MP on a custom board with Linux BSP LF-6.12.20. Several GPIO pins are configured as wakeup sources. Problem: during EMC transient testing (ESD), short noise pulses on these GPIO lines falsely wake the suspended system. We have already confirmed that software debounce cannot solve this: the wakeup decision is made by hardware while the CPU is suspended, and the GPIO interrupt handler — including the gpio-keys debounce — only runs after the system has resumed, so software cannot prevent the wakeup itself. We have also reviewed the Linux drivers (LF-6.12.20) and the i.MX8MP reference manual, and we could not find any hardware filter for the GPIO wakeup path. Please confirm whether this understanding is correct. Questions: 1. Does i.MX8MP have ANY hardware option (in GPIO, GPC, or configurable via ATF) to ignore very short pulses on a wakeup pin — for example a glitch filter or a minimum pulse-width setting? This includes level-trigger mode: does it require the level to be held for a minimum time, or does any instantaneous pulse still trigger wakeup? 2. If no such hardware option exists, what is NXP's recommended solution for this kind of false wakeup? Any application note on ESD protection for GPIO wakeup inputs would be appreciated. 3. Is there any NXP reference design where the Cortex-M7 checks/filters wakeup signals while the A53 stays in suspend? Platform: i.MX8MP custom board, BSP: LF-6.12.20 Best regards, i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: GPIO wakeup triggered by short noise pulses during suspend Hello @Leo_dev  Hope you are doing very well. Q1. Your understanding is correct. The i.MX8MP GPIO/GPC wakeup path has no hardware glitch filter or minimum pulse-width setting or debouncing register. Q2. As there is not an On-chip solution, the recommended design is adding a filter to the PAD. Q3. Yes, you can take a look to the AN13400 "i.MX 8M Low Power Design By M Core Running In System Suspend" is the primary NXP reference for this kind of architecture. Best regards, Salas.
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PTP over SJA1110 Hi, We are debugging PTP on a PolarFire SoC GEM connected through an SJA1110 switch. We observe that: PTP over Layer 2 (ptp4l -2) is received by the switch (ingress counters increase), but it is not forwarded (egress counters do not increase). PTP over UDP (ptp4l ) is forwarded correctly through the same bridge path. Normal Ethernet traffic (ICMP/ARP) also forwards correctly. Is there any special handling or additional configuration required on the SJA1110 to forward Layer 2 PTP frames (destination MAC 01:1B:19:00:00:00) across bridged ports? Are there any known restrictions on forwarding Layer 2 PTP? Also, is PTP over UDP (ptp4l) fully supported and recommended with the PolarFire SoC GEM, or is Layer 2 the only supported/recommended transport? Any guidance would be appreciated. Re: PTP over SJA1110 Hello @Ankur_pixl , In a typical gPTP / time-aware bridge use case, the switch is not expected to forward all gPTP frames transparently as ordinary multicast traffic. The usual flow is that the switch receives the gPTP frames from the Grandmaster, processes them through the gPTP stack running on the internal Cortex-M7 and then generates its own gPTP frames with the appropriate timestamps towards the connected downstream devices.   SJA1110 is typically configured for the Layer 2 Automotive Profile, where the PTP destination MAC address is 01:80:C2:00:00:0E. This address is used for 802.1AS/gPTP style Layer 2 transport and such frames are normally handled by the switch PTP/gPTP function rather than simply bridged as regular multicast traffic.   Your observation that the ingress counters increase, while the egress counters do not increase, suggests that the Layer 2 PTP frames are received by the switch but are not forwarded through the normal bridge path. One likely explanation is that the used PTP multicast MAC address is matched by the SJA1110 configuration, for example in the General Parameters table, DPI configuration, L2 Lookup Table or another PTP/trap-related configuration item, and the frames are therefore trapped to the host port, most likely to the internal Cortex-M7 host, instead of being forwarded to the expected external egress port.   This would also explain why PTP over UDP and normal Ethernet traffic such as ICMP/ARP are forwarded correctly. These frames do not match the same Layer 2 PTP/gPTP classification rule and are therefore handled as normal bridge traffic.   Please check the following points in your SJA1110 configuration:   1. Which PTP destination MAC address is configured in the switch, especially in the General Parameters table. 2. Whether PTP/gPTP frames are configured to be trapped to the host port. 3. Whether the internal Cortex-M7 host is running a gPTP stack or receiving the trapped PTP frames. 4. Whether the used destination MAC address is 01:1B:19:00:00:00 or 01:80:C2:00:00:0E. 5. Whether the L2 Lookup Table or multicast forwarding configuration contains an entry that forwards this destination MAC to the required external ports. 6. Whether the ingress and egress ports are in the same VLAN and forwarding domain for this traffic.   If your intention is to use SJA1110 as a gPTP/time-aware bridge, then the expected configuration is usually not simple transparent forwarding of the original gPTP frames. The switch should participate in the gPTP timing domain and generate the corresponding gPTP messages towards the connected devices.   If your intention is instead to use SJA1110 only as a plain Ethernet bridge for raw Layer 2 PTP frames, then the PTP trapping/special handling must be disabled or avoided for this traffic, and the corresponding multicast destination MAC address must be explicitly allowed in the L2 forwarding configuration.   Regarding the PolarFire SoC GEM, I cannot make a definitive statement about the recommended or fully supported PTP transport mode for that device. From the SJA1110 point of view, PTP over UDP may be forwarded as ordinary IP/UDP traffic if the bridge path allows it. However, this does not necessarily mean that UDP transport is supported or recommended by the PolarFire GEM driver for hardware timestamping. Please confirm the supported PTP transport and timestamping modes with the PolarFire SoC GEM documentation or with Microchip support.   Best regards, Pavel Re: PTP over SJA1110 Hello @Ankur_pixl , The destination MAC address 01:1B:19:00:00:00 is an IEEE 1588 Layer 2 PTP multicast address. This is different from the 802.1AS / Automotive Profile gPTP destination MAC address 01:80:C2:00:00:0E, which is typically used in the SJA1110 gPTP Automotive Profile configuration.   Based on your description, this does not look like a standard Linux bridge MDB issue. The MDB entries may be correctly installed and even reported as offloaded, but the frame may still not reach the normal multicast forwarding path.   A likely explanation is that the SJA1110 hardware or the SJA1110 DSA driver classifies this destination MAC as a PTP/control frame before the normal L2 multicast forwarding decision is applied. In that case, the frame may be redirected to the CPU/management path instead of being forwarded directly between the two user ports.   This would explain the observed behavior:   - the ingress counter increases, so the frame is received by the switch, - the MDB entries are installed and shown as offloaded, - but the egress counter does not increase, because the frame is likely trapped to the CPU/management route before normal port-to-port forwarding is applied.   If the CPU/management route is not available in your port-to-port forwarding path, the trapped frame may effectively be dropped.   Regarding the Cortex-M7: if you are using the switch through the Linux DSA bridge and you do not run or control a gPTP stack on the internal Cortex-M7, then this should not normally be something configured from the Cortex-M7 application. In this use case, the relevant configuration is owned by the Linux DSA driver and by the switch hardware configuration programmed by that driver.   However, "bridge mdb" may not be sufficient if a dedicated PTP/control-frame trap rule is active for 01:1B:19:00:00:00. To forward this traffic directly in hardware between two user ports, the switch configuration would need to ensure that:   1. the PTP/control-frame trap for 01:1B:19:00:00:00 is disabled or bypassed for this traffic, and 2. a valid L2 multicast forwarding entry exists for 01:1B:19:00:00:00 towards the required user ports.   At this point, I would not expect the standard `bridge mdb` command alone to override a lower-level PTP/control-frame trap rule if such a rule is active in the SJA1110 DSA configuration.   As the next step, please check whether your SJA1110 DSA driver or BSP enables PTP hardware timestamping or installs any MAC filter / PTP trap rule for 01:1B:19:00:00:00. If such a rule is present, the solution will likely require a driver-level change or a switch static configuration change, rather than only a runtime Linux bridge MDB command.   Could you please share the following information?   - Linux BSP/kernel version, - SJA1110 DSA driver source baseline, - full output of "bridge -d mdb show", - the involved DSA port names and physical switch port numbers, - whether PTP hardware timestamping is enabled in the SJA1110 DSA driver, - and, if possible, a packet capture on the DSA master/CPU interface to confirm whether the Layer 2 PTP frames are being trapped to the CPU path.   With this information we can further check whether the frames are being consumed by the PTP/control trap path, or whether there is another L2 multicast forwarding limitation. Best regards, Pavel Re: PTP over SJA1110 Hello, The destination MAC is 01:1B:19:00:00:00. We're using the switch with the Linux DSA bridge and have no control or configuration access over the Cortex-M7 core. How do we allow this traffic through in the L2 configuration? We used bridge mdb, but it doesn't work; the entries install and even show as offloaded, yet the frames still aren't forwarded between the ports. Does this need to be set explicitly on the Cortex-M7 core? Additional context on our setup: Our MAC/port configuration is as follows: bridge mdb add dev br-EPS port epc2-uplink grp 01:1b:19:00:00:00 permanent bridge mdb add dev br-EPS port t1-6 grp 01:1b:19:00:00:00 permanent These show as offloaded in bridge -d mdb show, but L2 PTP frames arriving on one port are not forwarded out the other. Importantly, one of the switch ports does not have a working CPU port; it operates purely as a route between two ports (port-to-port forwarding), with no host/CPU port in that path. Since the reserved multicast 01:1b:19:00:00:00 appears to be trapped to the management/CPU route by default, and that route is not available here, we suspect the frames are being dropped rather than forwarded. Could you advise how to configure the switch to forward this reserved PTP multicast MAC in hardware between the two user ports, without relying on a CPU/management port? -- Ankur
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Question About SHA-512 of an ECC Public Key Stored in the NVM Key Catalog Dear NXP Expert, We have a question regarding the HSE key management functionality. We are using the S32K312 with HSE-B, and we store an ECC public key in the NVM Key Catalog. In our application, we need to obtain the SHA-512 hash of the ECC public key stored in the NVM Key Catalog. After the key is stored, we would like to verify that it has been stored correctly by comparing its SHA-512 hash. For example: Let K be the ECC public key stored in the NVM Key Catalog. We would like to obtain the value SHA-512(K). Does HSE provide any API or mechanism to obtain the SHA-512 hash of a key stored in the NVM Key Catalog? If not, is there any recommended way to calculate or verify SHA-512(K) for a key that is stored in the catalog? Thank you for your support. Re: Question About SHA-512 of an ECC Public Key Stored in the NVM Key Catalog I got it. Thank you for your support Re: Question About SHA-512 of an ECC Public Key Stored in the NVM Key Catalog Hi @NghiaLX308  There is no API that allows the user to perform SHA-512 directly on key material. As a workaround, you can export the ECC public key  (using service HSE_SRV_ID_EXPORT_KEY) and then perform the SHA-512 operation (using service HSE_SRV_ID_HASH). Since an ECC public key is not secret, it can be exported in plaintext. There is no need to export it in an encrypted or authenticated format. Regards, Lukas
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Fallback mechanism for failed AB_SWAP update Hello, We are developing an application that uses the AB_SWAP mechanism of the HSE firmware on the S32K342 to perform OTA updates. We are currently activating the passive block once the passive region of the flash is entirely written to. We were wondering whether there is a fallback mechanism that we can use to verify/check whether the image we are booting from is corrupted, and if we can fallback to the 'known good' active region that has become the passive region after resetting. This arises from the fact that on some occasions, we overwrite the passive region without issuing a reset and midway through we reset the processor, resulting in a corrupted image in the flash.  Re: Fallback mechanism for failed AB_SWAP update Hey @lukaszadrapa , Thanks for the clarification. We are still trying to understand which type of secure boot strategy to use in our application. Advance Secure boot seems a bit complicated with having to install the SMR and CR. On the other hand, Basic Secure boot seems slightly easier to install but the exact implementation and installation details seem unclear. I was wondering if you could provide some insight into these options. I am referring to the HSE B Reference Manual and was also wondering if there is any additional documentation I should be referring to for this. Regards, Shiv Re: Fallback mechanism for failed AB_SWAP update Hi @Shiv_peak  I answered very similar question a couple of days ago, please take a look at: https://community.nxp.com/t5/S32K/S32K-OTA-Rollback/m-p/2400332/highlight/true#M60125 If you need more details, just let me know. Regards, Lukas Re: Fallback mechanism for failed AB_SWAP update Can you also elaborate on what you mean by 'device goes in recovery mode' if the basic secure boot fails? Does this mean that the core will not be released from reset and there is no fallback or recovery in this case? I ask because we want to have the functionality where if the secure boot fails, we boot another image, possibly in the passive bank. Re: Fallback mechanism for failed AB_SWAP update We provide this application note: https://www.nxp.com/webapp/Download?colCode=AN13465   It’s updated version of Secure Boot application note v0.1.1.0 (AN744511) released in 2021 which can be downloaded from: https://www.nxp.com/products/S32K3 Application note can be found here: Documentation -> Secure Files -> Secure Boot Application note v0.1.1.0 (AN744511) Associated demo project can be downloaded here: Design Resources -> Software -> Secure Files -> SecureBootAppNoteDemo (SW745310) The software was not updated, so use mentioned SW745310 if you are interested. Other examples for secure boot can be found in HSE Demo Examples (recommended): https://www.nxp.com/webapp/Download?colCode=S32K3_HSE_DemoExamples There are examples for all three modes – advanced secure boot, basic secure boot and SHE secure boot. Generally, advanced secure boot mode is recommended. Yes, it is not trivial task to configure the secure boot in this mode. However, it provides the best protection and configurability. The advantage is that you can select any signature scheme you want,  you can cover multiple regions and you can configure different sanctions if the secure boot fails. On other hand, basic secure boot mode always uses only GMAC tag which is calculated using a key derived from ADKP and it can cover one region only. If it fails, the device goes directly to recovery mode. I recommend to study following projects in HSE DemoExamples: S32K344_Advanced_SecureBoot S32K344_Basic_SecureBoot These are configuration projects which are supposed to protect application S32K344_SecureBootBlinky which is linked to those projects. Regards, Lukas Re: Fallback mechanism for failed AB_SWAP update Thanks for the clarity Lukas. I will look into the application note and the HSE demo examples and revert back in case of any queries. Regards, Shiv Re: Fallback mechanism for failed AB_SWAP update Ok that clears things up, thanks! So from what I am understanding: The Basic Secure Boot goes into recovery mode if the image verification fails. This recovery mode can be configured as Secure recovery using the attribute HSE_SECURE_RECOVERY_CONFIG_ATTR_ID. Configuring this mode requires programming the UTEST mode. Configuring this also needs the BOOT_SEQ == 1 in the IVT. The ADKP needs to be configured using HSE_APP_DEBUG_KEY_ATTR_ID in order to compute the GMAC. Couple of follow ups as I wrap my head around this: The Application Note you shared mentioned that configuring the ADKP can only be done in the CUST_DEL lifecycle. How do I verify the lifecycle of my system and is it safe to do so? Is the AppBL same as the IVT in the Basic Secure Boot. Do I need to append the GMAC and Recovery Image address to the IVT? Hoping to get a bit more clarity on these before I start implementation and testing on my boards. Thank you so much for being responsive and clearing my doubts! Regards, Shiv Re: Fallback mechanism for failed AB_SWAP update Take a look at section “2.6.1.3 Recovery Mode” in HSE firmware reference manual rev. 2.7. In short, there are two modes: JTAG based recovery mode – the device just hangs in endless loop in RAM (this piece of code is loaded to RAM by SBAF), so user can connect a debugger and perform some recovery steps. Secure recovery mode – this needs to be enabled by attribute HSE_SECURE_RECOVERY_CONFIG_ATTR_ID. Notice that this is OTP attribute programmed to UTEST memory. This starts recovery image which needs to be verified first. So, it is similar to basic secure boot. If the verification fails, it goes to JTAG recovery mode. The secure recovery mode can be used for recovery/rollback in runtime. But I do not recommend to run this from passive partition. All the code should be executed from active partition. In AB swap mode, you will have a copy of secure recovery image in both partitions anyway. Another option is to put this code to data flash memory if there’s enough space. Re: Fallback mechanism for failed AB_SWAP update See please my comments below. The Basic Secure Boot goes into recovery mode if the image verification fails. Yes. This recovery mode can be configured as Secure recovery using the attribute HSE_SECURE_RECOVERY_CONFIG_ATTR_ID. Yes. Configuring this mode requires programming the UTEST mode. The UTEST is programmed by HSE when calling set attribute service with HSE_SECURE_RECOVERY_CONFIG_ATTR_ID. Common issue – be aware that flash block 0 and UTEST are in the same read partition. You code cannot run from flash block 0 when programming this attribute. Configuring this also needs the BOOT_SEQ == 1 in the IVT. Yes. The ADKP needs to be configured using HSE_APP_DEBUG_KEY_ATTR_ID in order to compute the GMAC. Yes. Couple of follow ups as I wrap my head around this: The Application Note you shared mentioned that configuring the ADKP can only be done in the CUST_DEL lifecycle. How do I verify the lifecycle of my system and is it safe to do so? Yes, you can’t advance the life cycle until ADKP is set. Once the life cycle is advanced, secure debug is enabled, so you need to configure your debugger accordingly to be able to establish the connection. Take a look at this post: https://community.nxp.com/t5/S32K/S32K3-HSE/m-p/2066312/highlight/true#M47070 The life cycle status can be read from register DCMLCC in DCM module. Is the AppBL same as the IVT in the Basic Secure Boot. AppBL and IVT is signed and verified in the same way. IV and GMAC is also appended to the IVT. You can see that in “Table 118. IVT structure” in HSE firmware reference manual. Do I need to append the GMAC and Recovery Image address to the IVT? If you want to verify IVT, IV and GMAC must be added to IVT as mentioned above. If you want to use secure recovery image, pointer to the image and length of the image must be added to IVT. Regards, Lukas Re: Fallback mechanism for failed AB_SWAP update Thanks for the reply Lukas, this clarifies things! I will start implementing the Basic Secure Boot and will be in touch in case of any queries or doubts. Regards, Shiv 
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S32K314 CAN issue I am using S32K314  , and recently I got a issue about CAN when I doing  the test by short-circuiting of the oscillator ; after recovery  ,I monitored  SPI ,ADC ,these modules works OK, but CAN module can not work normally, the debuger show these information,  in this status, CAN can not receive or send any fram, how could this happened, and how to recover this fault by sw?   Re: S32K314 CAN issue Hi,  Thanks for your  reply . I try to add some test code in "Mcu_ClockSourceFailure_Notification" , but this notification do not be trigged; so from software side , how can we notice this issue happened then reset CAN Module? thanks Below is the value of the registers you mentioned: MCR CTRL1 CBT: FDCBT: ECR ESR1 Re: S32K314 CAN issue Hi, From the provided screenshot, the receive error counter (RXERRCNT) is increasing while TXERRCNT remains 0, which does not fully match a typical transmit-related issue even though ESR1 indicates a transmission attempt is ongoing. The oscillator short-circuit could potentially have affected the clocking, resulting e.g. in incorrect CAN bit timing after recovery. However, the current information is not sufficient to confirm this. Could you please provide: a wider view of the FlexCAN registers (including MCR/CTRL1/CBT/FDCBT, ECR and ESR1), the module and CAN protocol clock configuration after recovery, TX, RX and CAN bus measurements captured during the failure? If the FlexCAN module clock and the CAN protocol clock are running and have the expected frequency, you can also try performing a FlexCAN module software reset followed by a complete module reinitialization and check whether communication is restored. BR, Petr Re: S32K314 CAN issue Hi, If Mcu_ClockSourceFailure_Notification() is not entered, my first assumption would be that the corresponding MCU interrupt/notification path is not configured or enabled in the project. Could you please check: Whether clock monitoring (CMU) is enabled for the affected clock source. Whether the CMU interrupt is enabled. Whether the MCU module is configured to call Mcu_ClockSourceFailure_Notification() upon detection of a clock failure. It may also be useful to inspect CMU and RGM status registers after the oscillator short-circuit event to verify that a clock failure is actually being detected. From the FlexCAN register dump, the module appears enabled and synchronized to the bus (SYNCH=1), while RXERRCNT increases and TXERRCNT remains 0, now without bus activity. I see the bit timing registers shown (CTRL1, CBT, FDCBT) do not contain a valid CAN timing configuration, although this may be expected if Enhanced CAN Bit Timing is used and the actual timing is configured through the respective enhanced CAN bit timing registers. Therefore, before implementing a CAN reset strategy, it would be good to first verify whether the clock failure event is detected at all and whether the notification mechanism is properly configured. BR, Petr
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