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S32K314 HSE 安装问题 求助!我参考官方演示项目编写了HSE固件安装程序,但执行两次复位后,HSE安装地址0x007E0000处没有任何数据。这是否意味着HSE安装失败了?S32 版本为 3.6.8,芯片为 S32K314,RTD 版本为 7.0.1 1131_0-1788767775138.png1131_0-1788767775138.png 这是 ld 文件 1131_1-1788767805874.png1131_1-1788767805874.png 这是重写后的IVT向量 1131_2-1788767830677.png1131_2-1788767830677.png 1131_3-1788767849116.png1131_3-1788767849116.png 1131_4-1788767872384.png1131_4-1788767872384.png 最后,我附上我的 HSE 安装的demo项目。 回复: S32K314 HSE 安装问题 @VaneB 你好 我根据你的建议修改修改了链接器文件,并将ivt.c文件全部注释掉,重新启动程序两次过后,通过调试模式观察status = Hse_Ip_GetHseStatus(0u)的状态status的值 1001 0110 0000,但是第9位为0,说明HSE并未安装成功?而且获取不到任何版本信息,srvResponse = Hse_Ip_ServiceRequest(0u, u8MuChannel, &request, &pHseSrvDesc),srvResponse 的返回值为0xaa55a11e; 如下 1131_1-1788838145743.png1131_1-1788838145743.png 1131_2-1788838165453.png1131_2-1788838165453.png 1131_3-1788838180700.png1131_3-1788838180700.png 1131_4-1788838213520.png1131_4-1788838213520.png Re: S32K314 HSE 安装问题 嗨@杨工1131 我有几点看法: 根据链接器文件中的注释,HSE 固件应该放在 Block 0 中。但是,当前分配给 HSE_BINARY 的地址属于 Block 1。应该配置为 HSE_BINARY (R) : ORIGIN = 0x00400000 PFlash 区域应从 Block 1 开始: int_pflash : ORIGIN = 0x00500000, LENGTH = 0x00300000 - __HSE_CODE_SIZE /* 4096KB - __HSE_CODE_SIZE (sBAF + HSE) */ 建议不要使用硬编码地址,而是将 HSE_FW_ADDR 定义为: #define HSE_FW_ADDR (__HSE_BIN_START) 无需创建单独的 ivt.c 文件。图像矢量表结构已在Project_Settings → Startup_Code → startup_cm7.s中定义。 关于 IVT,如果您参考 S32K3xx 参考手册第 12 版第 32.5.3 节,CM7_2 起始地址之后的条目如下: .long 0xffffffff /* Offset 0x20: Reserved */ .long LC_CONFIG_ADDR /* Offset 0x24: Lifecycle configuration pointer */ .long CM7_3_VTOR_ADDR /* Offset 0x28: CM7_3 Start address */ .long HSE_FW_ADDR /* Offset 0x2C: Reserved */ 关于代码,我看到你使用了与示例相同的结构,所以我认为这部分不会有任何问题。 BR,VaneB
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EMI EMC 合规性证书和测试报告 大家好, 请帮忙确认一下下面提到的15W接收器套件是否符合EMI/EMC标准。 零件号:WPR1500-HV 产品描述 - 高压无线充电接收器 此致, 帕尔特·巴夫萨尔 Re: EMI EMC Compliance certificate and test report 你好@P907 , 感谢你的帖子。此EVK主要用于评估并通过基本的EMI/EMC测试,以符合CE标准。总的来说,我们的解决方案与市场上通用的解决方案之间并没有什么重大区别。 希望对您有所帮助。 BR 塞莱斯特 Re: EMI EMC Compliance certificate and test report 嗨, Celeste, 感谢您的回复。 能否请您帮忙分享一下测试报告及其结果?因此,我们将检查对这款 EVK 执行了哪些基本的 EMI/EMC 测试。 问候, 帕尔特·巴夫萨尔 Re: EMI EMC Compliance certificate and test report 你好@P907 , 当然,我可以和你分享。但是,这些材料不适合在社区等公共平台上分享。我稍后会通过私人邮件发送给你。请留意您的收件箱。 此致, 塞莱斯特 Re: EMI EMC Compliance certificate and test report 嗨,Celeste, 感谢您分享所请求的EVM的EMI/EMC测试报告。 此致, 帕尔特·巴夫萨尔
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死时间校正 NXP社区的各位好, 我想了解一下PWM-X 死区时间校正功能的相关情况。 根据文档,我了解到 PWM-X 可以根据电流/负载情况修改 PWM 脉冲。但是,我不清楚 PWM 模式是如何生成的,以及所需的反馈信号是如何连接和路由的。 在我的应用中,开关和电流检测电路都位于MCU外部: 感知到的电流信号是否需要直接连接到MCU引脚? 或者它应该先经过LPCMP ,然后通过TRGMUX或其他内部连接内部路由到 PWM-X? 此功能的预期信号路径和配置是什么? 我附上了一张来自 NXP 参考设计/文档的图片,显示了负载上略微衰减的输出波形。 我特别想了解的是用于生成该波形的PWM脉冲模式。 参考设计中所示的波形是负载/功率级产生的波形。但是,MCU 生成的 PWM 信号会经过栅极驱动器和开关级,因此 PWM 信号本身的形状不会与所示波形相同。 PWM-X 生成的脉冲 → 栅极驱动器/功率级 → 负载两端的最终波形 具体来说,我想了解 PWM-X 如何确定获得所示输出波形所需的脉冲宽度/占空比和定时,包括如何应用死区时间校正。 是否有任何参考设计、应用笔记、示例代码或参考软件实现了此 PWM-X 功能?提供一个示例,展示 PWM 配置、脉冲模式、引脚配置、内部信号路由和所需的外部电路,将非常有帮助。 FlexPWM同步 我还有一个关于FlexPWM同步的问题。 同步信号能否由其他外设在内部生成,还是必须来自外部MCU引脚? 例如, eMIOS生成的信号能否内部路由到 FlexPWM 同步输入? 任何关于内部路由/配置的示例或说明都将非常有帮助。 先行致谢。 此致, 象头神
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RT1172 LT8918 LCD parallel LCDIFV2 small layer + background underrun Unfortunately I can't directly connect the mipi output to this LCD, so LT8918 is added, but I don't seem to have problems with that. The test pattern goes through well onto that device and also my debug log shows that it syncs and passes basic setup. But I do get problems with the output. The current code I have is for a very simple small memory buffer (128x256) in the middle of 800x1280 screen. No need to look at the actual output screen, but it looks very distorted. Also in printed diagnostics I get a lot of underrun error as if the DMA is not getting data quickly enough for an entire row write. So, I'm not any expert in LCDs or NXP registers. Am I making some dumb mistake somewhere? There's plenty of uncertainty. Is SRAM_OC1 actually quite slow? Maybe there's some AXI or DMA setting to get the timings right? I reconfigured it in the MPU code to be noncached, but maybe that also is a mistake. Unfortunately I don't see a difference whether it's default or ncache region. There are a lof of other things to consider, like I tried changing the stride length to be the entire 800pixel row instead of the smaller 128 layer 0 size. The RGB pixel clock is slower than the MIPI byte clock, but I'd expect MIPI to be much faster anyway because it has 2 lines instead of the RGB parallel 24 connections. And also, the reason why I'm making such a small layer 0 area is because SDRAM might have errors. I am reducing this into a smaller controlled piece to get away from that uncertainty, but seems even in here I can't find exactly what's going wrong. It's neat to have come this far but also quite frustrating that I don't see what to do to get more progress. The background single color displays all work fine, also the test patterns make nice-shaped bar regions, so I don't think it's a real 'LCD' problem, it looks instead like the RAM buffer read or LCDIFv2 putting that to the parallel output has some timing issue. How could I debug this? Thanks. Re: RT1172 LT8918 LCD parallel LCDIFV2 small layer + background underrun I've tried a few more things, and now it actually looks like a stable output without underrun errors, at least according to my printed diagnostic. I think the primary change has been the first one, and other changes are a bit more difficult actually, but listing them for clarity. This particular setup is still RGB888 and I haven't wanted to change to experiment with alpha layer drawing yet as it's still not super good. 1. make the pixel clock much slower, down to a refresh closer to 15Hz. Maybe the DMA has extra time to work? But like you said, OCRAM should be fast. I have it set up to be an NCACHE region in that space too, in the MPU config. 2. the colors used are only black and white. Trying a green background actually introduces some background problems where the green can get shifted into an RGB pattern changing every row (off by 1 byte?). 3. the RAM layer 0 width is changed to 256 to match the height 256. Actually it's also fine as 128 height, just this particular log is 256 and you can see the stride changes too to 768. 4. The video settings for front porch and back porch are much bigger. I suspect this isn't the primary factor, I've also tried these settings at faster speeds, not super helpful. The datasheet maximum allows Hfp + Hbp + Hs to be as large as desired, is there any reason to have more than the 200 total here? Vertical settings are the ones limited to 250 altogether. So anyway, it's interesting! Technically the LCD datasheet says that it should be run at minimum 22Hz, but I don't see flickering on the white section. I'd love to run it faster. I haven't paid attention to DMA on RT1172 at all, is there anything to do to run it faster or give it more priority or something? Does LCDIFv2 have other settings for this? Particularly because OCRAM should be super fast, I'm surprised that slowing down so much had this effect. Re: RT1172 LT8918 LCD parallel LCDIFV2 small layer + background underrun Right. Thanks very much! Let's try more things. Here's another log. I wanted to stick with RGB888. Is there some reason ARGB8888 would be better for this? I might try playing with alpha sometime. CTRLDESCL5: 0xD8000260 I checked in the reference manual, the BPP setting is in bits 27-24, so that '8' indicates I successfully put it in RGB888, or so it seems. the last bytes seem unrelated and alpha settings seem harmlessly off. The screen output looks different but not fixed. Perhaps improved? There's still wraparound, but less aggressive. I've also experimented with increasing the speed of the pixel clock, not sure if that helps or hurts. I could try more video setting changes? I had thought my 25% Hsync settings were very strong here, but then again, I've never done this before. What makes a setting particularly good? Is Vsync relevant too? There's a LT8918 bridge that also needs to get these settings input, but I can also manage that. Am I limited to guessing the right numbers to put in? The driver is JD9365DA-H3, if that helps. This is a strange package with a touchscreen too, but I have no problems with that. Re: RT1172 LT8918 LCD parallel LCDIFV2 small layer + background underrun Hi @davidpspeedtech , Thanks for the update! However, the issue is that some of your settings aren't consistent. 0xD9000260 → the format latched in hardware is ARGB8888 (32-bit/pixel). So when you set stride = 384 (=128×3, RGB888), the hardware still fetches 128×4 = 512 bytes/row → per-line misalignment, reads past the buffer, and underrun. You changed only the stride or the BPP macro each time, but the hardware actually obeys .pixelFormat , which stayed ARGB8888 — the four values were never consistent. Please make them all consistent as 32-bit ARGB8888 or RGB888 in one shot:   #define SMALL_LAYER_0_BPP 4U #define SMALL_LAYER_0_STRIDE (SMALL_LAYER_0_WIDTH * 4) /* = 512 */ uint8_t smallLayer0_Buffer0[256][512]; .pixelFormat = kLCDIFV2_PixelFormatARGB8888, .strideBytes = SMALL_LAYER_0_STRIDE, /* 512, not 3200*/   CTRLDESCL3 should now read 0x200 (512). A 32-bit framebuffer and a 24-pin RGB888 output are independent — you do not need a 3-byte buffer for a 24-pin link. Also these three lines use eLCDIF bit definitions; LCDIFv2 has no RUN bit and this can disturb the control state:   LCDIFV2->CTRL &= ~LCDIF_CTRL_SFTRST_MASK; LCDIFV2->CTRL &= ~LCDIF_CTRL_CLKGATE_MASK; LCDIFV2->CTRL |= LCDIF_CTRL_RUN_MASK;   Gavin_Jia_0-1788249587860.pngGavin_Jia_0-1788249587860.pngGavin_Jia_0-1788249587860.png please drive it only with standard APIs. To confirm your other points: Stride is based on the RAM buffer width, not the screen width — correct. The background color is stable because it is register-generated (no memory fetch); this proves the output path is fine and isolates the fault to the layer fetch path. The color buffer flickering between primary/secondary colors ("like a byte is lost") is exactly underrun dropping bytes; it should disappear once the format is consistent. Bandwidth is not the bottleneck (OCRAM, 128-wide). If underrun still remains after this, lower the pixel clock or increase HBP/HFP to confirm. Re: RT1172 LT8918 LCD parallel LCDIFV2 small layer + background underrun Well, that doesn't fix it. Actually whether the stride is 128*3 for RGB888 or whether it's 800*4 setup for ARGB8888 and trying to put the entire screen into RAM, the output looks rather similar with distortion off the edge of the screen and I still get underrun errors. I've tried a lot of settings, not only the text in those files! #define SMALL_LAYER_0_HEIGHT 256U #define SMALL_LAYER_0_WIDTH 128U #define SMALL_LAYER_0_BPP 3U /* RGB888 */ #define SMALL_LAYER_0_STRIDE (SMALL_LAYER_0_WIDTH*SMALL_LAYER_0_BPP) /*384*/ ~debug print~ CTRLDESCL3: 0x 180 (Pitch/Stride = 384 bytes) Again, that also doesn't work. But I'm happy that you can confirm that my layer 0 stride setting should be based on the RAM buffer width and not based on the LCD screen width. Right? Since the interface to LT8918 has a 24 pin parallel connection it really should be RGB888. I am concerned sometimes that DMA or something isn't keeping up, but this is running out of SRAM_OC1 with the tiny buffer size. Perhaps even RGB565 would have similar output because the most significant bits could be output correctly on their RGB pins. I might even try something monochrome. I might be making more mistakes as visible in the sample code with the BPP set to 4 instead of 3 for RGB888. Is there any requirement to have the 'background area' in a different layer and buffered in some other memory? I like that the background setting seems to work correctly and the output color there is stable at whatever solid color I set it to. Some experimenting with non-white RAM buffers allow the screen to flicker between primary (RGB) or secondary colors, like an individual byte is lost, perhaps. Re: RT1172 LT8918 LCD parallel LCDIFV2 small layer + background underrun Hi @davidpspeedtech , Thanks for your interest in NXP MIMXRT series! I reviewed the attachments you provided, and some of the settings may need to be adjusted. CTRLDESCL3: 0x00000C80 (Pitch/Stride = 3200 bytes) #define SMALL_LAYER_0_BPP 3U /* RGB888 */ #define SMALL_LAYER_0_STRIDE (128 * 3) /* = 384 bytes */ uint8_t smallLayer0_Buffer0[256][384]; --> The PITCH you programmed into CTRLDESCL3 (3200 bytes) does not match your actual buffer layout. Your buffer is 128 x 256 in RGB888, so each row is only 128 x 3 = 384 bytes.   With PITCH = 3200, LCDIFv2 advances 3200 bytes per line instead of 384, so after each row it lands far past the valid data. This single mismatch is enough to produce BOTH symptoms you see: the wrong start address per line gives the distorted/skewed image, and fetching ~8x more (and invalid) data per line starves the output FIFO, which is what raises the underrun errors.   Please make the layer descriptor consistent with the buffer: CTRLDESCL3 (PITCH) = 384 (0x180), i.e. SMALL_LAYER_0_STRIDE = 128 * 3.  Buffer base address 64-byte aligned; keep it non-cacheable (your current setting is correct) or clean the D-cache before display. Best regards, Gavin Re: RT1172 LT8918 LCD parallel LCDIFV2 small layer + background underrun Hi @davidpspeedtech , The descriptor is now self-consistent: CTRLDESCL5=0xD8000260 (BPP=8=RGB888), CTRLDESCL3=0x300=768=256×3. You read it correctly. But the underlying mismatch is still there; it's just masked by the low clock. The color "changes every row, like a byte is lost" is the proof: your memory dump is all 0xFFFFFFFF and Center Pixel reads one pixel as a single 32-bit word — i.e. the content is still 32-bit/pixel while the hardware fetches 3 bytes. White is 0xFF in every byte so it hides it; green drifts per line. Lowering the pixel clock "removes" the underrun, but not because OCRAM is slow (OCRAM is fast, on-chip memory is not the bottleneck). Underrun depends on LCDIFv2's fetch throughput as an AXI master. You dropped the refresh to ~13.5 Hz (18.85 MHz ÷ (1000×1400)), cutting the fetch demand 3–4×, so it stops — but that's below the panel's minimum. To run fast without underrun, these may helps: Switch to ARGB8888 end-to-end: .pixelFormat=ARGB8888 , BPP=4, stride=256×4=1024, buffer at 4 bytes/pixel, and make sure the pixel-writing code writes 32-bit words. Two reasons: (a) it matches your existing 32-bit content → fixes green; (b) the RM notes packed RGB888 issues bursts of length 15 on the bus (less efficient, more underrun-prone), while ARGB8888 is 32-bit aligned with clean length-16 bursts. Verify with a green dump: it should be a clean repeat, not drifting per row. Raise the LCDIFv2 b_clk (clock root) and restore the pixel clock to ≥22 Hz — that's the correct lever for speed, not lowering the clock. LCDIFv2 does not use eDMA, so "raising DMA priority" doesn't apply; the available levers are b_clk, burst length, outstanding requests, and the THRES dynamic-priority threshold. Take the timing from the JD9365DA-H3 panel datasheet — don't guess — and match the LT8918 input timing to it. ~200 horizontal blanking is fine; larger blanking eases underrun but raises htotal (needing a higher pixel clock), so it's a trade-off — the root fix is a higher b_clk. Vsync/vertical porch must match the panel but have little effect on per-line underrun. Best regards, Gavin
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Could you please provide me the pin delay of LS1021AXE7KQB? Hi, Currently, I'm designing PCB for my board. For critical timing requirement of DDR4 interface, I need to compensate the pin delay difference in the  LS1021AXE7KQB package on the PCB. So, could you please provide me the pin delay information of LS1021AXE7KQB? Thanks in advance! Best regards! Jason QorIQ LS1 Devices Re: Could you please provide me the pin delay of LS1021AXE7KQB? All internal die to pad wires of the DDR4 interface are length matched within the package, so the layout trace length task is to be done between processor's and SDRAM's pins. No specific package delay values were provided as they are not needed for the design approach. Re: Could you please provide me the pin delay of LS1021AXE7KQB? Hi,yiping For DDR4 interface of LS1021A, is it necessary to compensate pin delay difference in the package on the PCB?  Thanks in advance! Best regards! Jason Re: Could you please provide me the pin delay of LS1021AXE7KQB? The requested documents are NXP Confidential Proprietary and can only be provided under non-disclosure agreement (NDA).   Did you sign NDA with NXP? If yes, would you please provide your NDA copy or your NDA number?   You could sing a new NDA from https://www.nxp.com/webapp-signup/ndaReqForm Re: Could you please provide me the pin delay of LS1021AXE7KQB? Asked for the required information from the AE team. Re: Could you please provide me the pin delay of LS1021AXE7KQB? Hi, Any response is welcome! Thanks in advance! Best regards! Jason Re: Could you please provide me the pin delay of LS1021AXE7KQB? Hi, yiping: Get it, many thanks to you!!! BTW, I have another question.  eTSEC1 and eTSEC3 of LS1021A will be configured as RGMII mode to driver PHY. But the size of my board is very big,  I'm afraid that the too long trace on PCB will cause insufficient drive capability for RGMII interface(250Mbps per data signal) . Could you please provide the route constraint for RGMII interface, especially trace length on PCB based on common FR-4 PCB(Dk 4.2~4.4, Df 0.022)? Cause, I can't find any PCB design consideration on NXP website.  Also AN4878_Design Checklist only show the design requirement of schematic. Thanks in advance! Best regards! Jason Re: Could you please provide me the pin delay of LS1021AXE7KQB? Would you please create a new thread for your new question? Thanks.
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EMI EMC Compliance certificate and test report Hi Team, Could you please help to check and confirm that below mentioned 15W receiver kit is EMI/EMC compliant. P/N: WPR1500-HV Description - High Voltage Wireless Charging Receiver Regards, Parth Bhavsar Re: EMI EMC Compliance certificate and test report Hello @P907 , Thanks for your post. This EVK is mainly for evaluation and pass basic EMI/EMC test to be CE compliance. In general there aren't any major different between our solution and general solution on market. Hope it helps. BR Celeste Re: EMI EMC Compliance certificate and test report Hi Celeste, Thank you for the reply. Could you please help us to share the test report and its results. So, from that we will check which are the basic EMI/EMC test is performed on this EVK. Regards, Parth Bhavsar Re: EMI EMC Compliance certificate and test report Hello @P907 , Of course, I can share them with you. However, these materials are not suitable for sharing on public platforms such as the Community. I will send them to you via private email shortly. Please keep an eye on your inbox. Regards, Celeste Re: EMI EMC Compliance certificate and test report Hi Celeste, Thank you for sharing EMI/EMC test report for the requested EVM. Regards, Parth Bhavsar
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デッドタイム補正 こんにちは、NXPコミュニティの皆さん、 PWM-Xのデッドタイム補正機能について、いくつか説明を求めています。 ドキュメントによると、PWM-Xは電流や負荷の状態に基づいてPWMパルスを修正できると理解しています。しかし、PWMパターンがどのように生成され、必要なフィードバック信号がどのように接続・ルーティングされるのかはよくわかりません。 私のアプリケーションでは、スイッチと電流検出回路はMCUの外部にあります: 検出された電流信号は直接MCUのピンに接続される予定ですか? それとも、まずLPCMPを経由してから、 TRGMUXまたは別の内部接続を介してPWM-Xに内部的にルーティングされるべきでしょうか? この機能における想定される信号経路と構成はどのようなものですか? 負荷全体でわずか に減衰する出力波形 を示すNXPの**リファレンス・デザイン**/**ドキュメント**の画像を添付しました。 私が特に理解しようとしているのは、この波形を生成するために使用されるPWMパルスパターンです。 リファレンス・デザインに示されている波形は、負荷/電力段階での得られる波形です。しかし、MCUで生成されるPWM信号はゲートドライバとスイッチングステージを通過するため、PWM信号自体は示された波形とは異なる形状になります。 PWM-Xは負荷全体→ゲートドライバー/パワーステージ→パルスを生成し、その結果として波形を生成します 具体的には、PWM-Xが、図示された出力波形を得るために必要なパルス幅/デューティサイクルとタイミングをどのように決定するのか、また、デッドタイム補正がどのように適用されるのかを理解したいと考えています。 このPWM-X機能が実装されている リファレンスデザイン、アプリケーションノート、例コード、リファレンスソフトウェア などはありますか?PWM構成、パルスパターン、ピン配置、内部信号ルーティング、および必要な外部回路を示す例があると非常に役立ちます。 FlexPWM同期 FlexPWMの同期についても質問があります。 同期信号は他のペリフェラルから内部的に生成できるのでしょうか、それとも外部のMCUピンから発信しなければならないのでしょうか? 例えば、 eMIOS で生成された信号を内部的にFlexPWM同期入力にルーティングすることは可能でしょうか? 内部ルーティング/設定に関する例や説明があれば大変助かります。 よろしくお願いいたします。 よろしくお願いします、 ガネーシャ
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定时器触发DMA传输 你好, 我目前正在使用MCXN947微控制器。 我尝试通过 CTIMER 匹配中断触发 DMA 数据传输到采样缓冲区。 其思路是通过 DMA 每隔 x 个定时器间隔(具体来说是每隔 10 微秒)将 GPIO 寄存器的状态(具体来说是某些引脚的输入值)写入采样缓冲区。 我可以确认我的GPIO引脚已正确配置为输入。 我可以确认我的计时器工作正常,每 10 微秒触发一次比赛。 我可以确认我的 DMA 传输工作正常,因为缓冲区会被值填满。 我可以确认源地址(GPIO PDIR 寄存器)在 DMA 配置中已正确设置。 我可以确认我的目标地址在 DMA 配置中也设置正确,因为它始终位于缓冲区起始地址和结束地址之间(这意味着它可以正确递增和循环)。 但不知何故,错误的值被复制到了缓冲区中。我在调试器中看到,我尝试传输的寄存器的值为0x00020000 (引脚 17 为高电平,其余引脚为低电平)。但是,我的缓冲区只填充了0秒。这是一个 uint32_t 类型的缓冲区,包含 512 个元素,全部初始化为0xFF 。随着 DMA 传输的增加,整个缓冲区逐渐被0x0填充,而不是预期的0x00020000值(该值永远不会改变 - 引脚 17 始终为高电平)。 你知道这是什么原因造成的吗?或者我可能遗漏了什么? 以下是我的驱动程序配置: 计时器: CTIMER0 kCTIMER_Match_1 CTIMER0_IRQn(中断触发回调是可选的,但我为了调试目的在我的代码中使用它) DMA: DMA0 kDma0RequestMuxCtimer0M1 kINPUTMUX_Ctimer0M1ToDma0Ch8Ena EDMA_0_CH8_IRQn(中断触发回调是可选的,但我为了调试目的在我的代码中使用它) GPIO: GPIO3 端口3 引脚 17 以下是开始采样之前寄存器的状态。 reg_gpio3.pngreg_gpio3.pngreg_gpio3.pngreg_gpio3.pngreg_gpio3.png reg_port3.pngreg_port3.pngreg_port3.pngreg_port3.pngreg_port3.png reg_edma0_ch8.pngreg_edma0_ch8.pngreg_edma0_ch8.pngreg_edma0_ch8.pngreg_edma0_ch8.png reg_inputmux0_dma.pngreg_inputmux0_dma.pngreg_inputmux0_dma.pngreg_inputmux0_dma.pngreg_inputmux0_dma.png reg_inputmux0_timer.pngreg_inputmux0_timer.pngreg_inputmux0_timer.pngreg_inputmux0_timer.pngreg_inputmux0_timer.png reg_ctimer0.pngreg_ctimer0.pngreg_ctimer0.pngreg_ctimer0.pngreg_ctimer0.png             MCX N Re: Timer triggers DMA transfer 你好, 由于IP限制,我无法将我的整个项目发送给您。不过,我可以给你一个包含我的设置的小应用程序的 c 文件。GPIO、DMA 和定时器配置与我这边的相同。文件已附上。 Re: Timer triggers DMA transfer 你好@jabitbe2_jcplc 您能否与我们分享一下您的项目?我想尝试重现这个问题,并在我这边进行调查。 谢谢! 此致, 爱丽丝 Re: Timer triggers DMA transfer 你好@jabitbe2_jcplc MCXN947 支持 TrustZone 和网络安全归因控制。 如果访问源自与引脚安全配置不匹配的安全域,则对相应 GPIO 寄存器的读写操作可能无效。 请您确认 GPIO3 引脚 17 对应的位是否配置为允许非安全访问,并再次进行测试? 如果该位当前配置为仅安全,则意外的 GPIO 行为可能与 TrustZone 安全设置有关。 谢谢! BR 爱丽丝
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iMX8M Plus CCコントローラ こんにちは、 iMX8M plusプロセッサをベースにしたカスタムSOMを開発し、専用キャリアボードを搭載しています。この要件では、IDピンでサポートされたUSB1 OTGが必要です。IDピンはGPIO1_IO4から取得しました。 基板スペースの制約とIDピンの要件から、設計には HD3SS3220IRNH - TI(CCコントローラと差分多行 )を使用する予定です。 i.mx8m plusがOTGとしてHD3SS3220IRNHをサポートしているか確認してください。特にフラッシュ目的で、このコントローラーはサポートされているのでしょうか? Re: iMX8M Plus CC Controller こんにちは@Zhiming_Liu  IDピンがサポートされている他のテスト済みCCコントローラをご存知いただけますか? Re: iMX8M Plus CC Controller こんにちは@govind18  i.MX 8M Plusは、TI HD3SS3220と連携してデュアルロールUSBタイプCポートを実装するようシステム設計で設定可能です。ただし、このデバイスはNXPのEVKによって公式に検証またはサポートされているType-Cコントローラではありません。GPIO1_IO4はUboot/LinuxでUSB IDとして使用でき、UUUプログラミングには影響しません。HD3SS3220は、電源投入時にデフォルトでUFP/Sinkに設定することをお勧めします。 よろしくお願いします、 志明
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需要对 LPC4078 EEPROM 页面擦除进行说明 我正在使用 LPC4078 和 MCUXpresso,并尝试在 Eeprom 中存储数值。 我想在不清除整个页面的情况下在页面中间写几个字节。 在数据表中可以看到,在将数据写入页面寄存器后,还必须将其编程到非易失性存储器中,而这是通过擦除/编程操作完成的。 擦除/编程操作是擦除整个页面,还是只擦除有新数据的页面区域?- 擦除/编程的地址设置会忽略 6 个 lsbs,因此它只知道页面。 UM10562.pdf 没有明确说明这个问题。 谢谢! 亚历克斯 Re: lpc4078 eeprom page erase clarification required 我附上了一个工作区,其中包含上述项目。我使用 lpc-link2 调试器在 LPC4078 上运行了它。 (我懒得让半托管工作,所以使用断点来检查数据)。 Re: lpc4078 eeprom page erase clarification required 你好@alex_conway 对于 LPC4078 EEPROM,最小擦除/编程单位为一页(64 字节)。因此,每次擦除/编程操作都会擦除整个页面。如果你只想写入几个字节,请先读取整个页面,然后修改所需的字节,最后在页面上执行擦除/编程操作。您可以在自己身边进行测试。   谢谢!   BR 爱丽丝 Re: lpc4078 eeprom page erase clarification required 嗨,爱丽丝、 我的实验证明并非如此: 我使用 lpc_board_ea_devkin_4088 库和 periph_eeprom 演示项目编写了一个小程序来启动它。 我擦除了一页 Eeprom,然后读了回来。令我惊讶的是,结果都是 "0",而不是 0xFF 然后,我将 "ABCDEFG/0 "写入该页面的地址 0,并读回页面。我收到 "ABCDEFG\0 然后,我将 "ABCDEFG/0 "写入该页的地址 7,并回读该页。我收到 "ABCDEFGABCDEFG\0 除了两件事之外,一切都在预料之中: 1. 擦除 eeprom 后读数为 0 2. 从Chip_EEPROM_Write()的实现来看,似乎没有读取-修改-擦除-写入的顺序。只有 Chip_EEPROM_WritePageRegister 之后的 Chip_EEPROM_EraseProgramPag。 这就是我提问的原因。 谢谢! 亚历克斯 Re: lpc4078 eeprom page erase clarification required 在所有 printf 字符串中添加换行符后,我的半托管系统就能正常工作了!还有更清楚的证据证明了我所说的一切: 擦除将 Eeprom 设置为 0x00 该代码不执行读-修改-擦除-写序列,只执行擦除-写序列。 LPC4078 在擦除时似乎只擦除写入的位置。 我真的很想澄清这一点。 谢谢! 亚历克斯 Re: lpc4078 eeprom page erase clarification required 尽管事态“升级”(无论这意味着什么),但恩智浦方面对此事仍未作出进一步回应。 我还需要进一步澄清。 Re: lpc4078 eeprom page erase clarification required 嗨@alex_conway 感谢您的回复,很抱歉回复晚了。 遗憾的是,我们之前的社区脚本存在故障,因此客户回复无法在我们的内部系统中触发案例更新通知。对于延误,我深表歉意。 关于 LPC4078 上的 EEPROM,根据用户手册,与实际 EEPROM 块的所有通信都是通过 64 字节的页面缓冲区进行的。因此,请确保您的 EEPROM 操作符合用户手册中描述的要求。 Alice_Yang_1-1788510957201.pngAlice_Yang_1-1788510957201.pngAlice_Yang_1-1788510957201.png Alice_Yang_0-1788510947469.pngAlice_Yang_0-1788510947469.pngAlice_Yang_0-1788510947469.png 目前,除非按照这些要求访问 EEPROM,否则我们无法确定是否存在问题。 谢谢! BR 爱丽丝 Re: lpc4078 eeprom page erase clarification required 嗨,爱丽丝、 我正在使用 eeprom_17xx_40xx.h 中的函数。和 eeprom_17xx_40xx.c(由恩智浦提供,并包含在我附上的项目中) Chip_EEPROM_Write() 函数调用 Chip_EEPROM_WritePageRegister() 函数,然后调用 Chip_EEPROM_EraseProgramPage() 函数。 Chip_EEPROM_WritePageRegister() 函数使用 Chip_EEPROM_SetAddr() 函数设置 EEPROM 地址,该函数负责移位和消隐低 6 位。 然后使用 Chip_EEPROM_WriteData() 函数将数据字节写入 EEPROM 写入数据寄存器 (WDATA)。 Chip_EEPROM_EraseProgramPage() 使用 Chip_EEPROM_SetAddr() 函数设置页地址,启用擦除/页编程位,并等待编程完成。 我找不到任何读取页面中现有 EEPROM 数据以执行页面读取-修改-写入操作的代码。 然而,正如我的项目所展示的那样,EEPROM 页擦除似乎不会擦除整个页面,而只会擦除写入数据寄存器中加载了新数据的地址。 谢谢! 亚历克斯
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iMX8M Plus CC Controller Hii, We are developing the custom som based on the iMX8M plus processors with custom carrier board. In this, We have a requirement for USB1 OTG supported with ID pin. We have taken ID pin from GPIO1_IO4. Due to board space constraint and ID Pin requirement we are planning to use HD3SS3220IRNH - TI (CC Controller with diff mux) in our design. Please confirm whether i.mx8m plus supports HD3SS3220IRNH as OTG. Specifically for Flashing purpose whether this controller is supported? Re: iMX8M Plus CC Controller Hi @govind18  The i.MX 8M Plus can be configured in system designs to work with the TI HD3SS3220 to implement a dual-role USB Type-C port; however, this device is not a Type-C controller that has been officially verified or supported by NXP‘s EVK. GPIO1_IO4 can be used as USB ID in Uboot/Linux and does not affect UUU programming. It is recommended that the HD3SS3220 be configured to UFP/Sink by default at power-on. Best Regards, Zhiming Re: iMX8M Plus CC Controller Hi @Zhiming_Liu  Could you please suggest any other tested CC controller that has ID pin Supported?
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SE050 安全元件与 i.MX 8M Plus 和 Yocto Linux 的集成 大家好, 我正在使用 i.MX 8M Plus EVK 和 NXP SE050 安全元件。我想使用适用于 i.MX 平台的 Yocto 构建系统,在 Linux 系统下启动并运行 SE050。 请问是否有任何可用的集成/移植文档、应用笔记或参考实现,用于将 SE050 与 i.MX 8M Plus 和 Yocto 集成和测试? 我偶然发现了 NXP Plug & Trust 中间件存储库,其中提到了对 Linux 的 i.MX6UL 和 i.MX8MQ 的支持: https://github.com/NXP/plug-and-trust 我还想了解这种现有的实现方式是否可以直接与 i.MX 8M Plus 一起使用,或者是否需要任何平台特定的移植,特别是对于 I²C 接口和 Yocto 集成。 谢谢, 罗汉 SE050 Re: SE050 Secure Element Integration with i.MX 8M Plus and Yocto Linux 你好@rohannathi , Plug & Trust 中间件 GitHub 迷你包是Linux 使用的子集;建议使用 nxp.com/se050 上的完整软件包进行开发,因为它包含示例、工具和完整的文档。 i.MX 8M Plus 与现有的 iMXLinux 主机目标完全兼容——无需针对 i.MX 系列进行移植。 NXP 有一个参考设计——NavQPlus (8MPNAVQ) ——它基于相同的 i.MX 8M Plus SoC (与 i.MX 8M Plus EVK 相同的 SOM),并具有板载 SE050 安全元件,支持Yocto Linux 和 ROS2 。这是目前最接近 SE050 + i.MX 8M Plus + Yocto 的硬件参考,其 BSP/Yocto 层配置可作为直接指南。 您可以访问https://community.nxp.com/t5/Secure-Authentication-Knowledge/Integrating-EdgeLock-SE05X-to-FRDM-IMX91/ta-p/2138152查看更多详情。 希望对您有所帮助。 祝你有美好的一天, 坎 ------------------------------------------------------------------------------- 笔记: - 如果此回复解答了您的问题,请点击“标记为正确答案”按钮。谢谢你! - 我们会持续关注帖子,从最后一条回复发出后持续7周,之后的回复将被忽略。 如果您之后有相关问题,请另开新帖并引用已关闭的帖子。 -------------------------------------------------------------------------------
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CodeWarrior and PEmicro Multilink to MCU MKL03Z16VFK4R Hi,  I have MCU MKL03Z16VFK4R and I need to program it on winXP using PEmicro Multilink Universal. According to the information I have gathered, there is CodeWarrior 10.6 that support winXP. Could you share the CodeWarrior 10.6 software installer? or, Do you have other software that support winXP? Thank you Re: CodeWarrior and PEmicro Multilink to MCU MKL03Z16VFK4R Hi @Chalearmrat  Thank you for your post. There is not an available 10.6 Code Warrior installer you could review the different versions of CodeWarrior available at CodeWarrior Downloads | NXP Semiconductors The recommended version for Kinetis is CodeWarrior for MCUs 11.1 (that could be used at Windows 11), but it does not include support for KL03. carlos_o_0-1778783252765.pngcarlos_o_0-1778783252765.png The KL0x series are supported at MCUXpresso IDE and the SDKs could be downloaded from MCUXpresso SDK Builder carlos_o_1-1778783488621.pngcarlos_o_1-1778783488621.png Re: CodeWarrior and PEmicro Multilink to MCU MKL03Z16VFK4R Hi, CodeWarrior 10.6 is quite old, and official installers may no longer be readily available. For the MKL03Z16VFK4R with a PEmicro Multilink Universal, I would recommend checking NXP’s archived CodeWarrior downloads and PEmicro’s legacy software/tools for Windows XP compatibility. If you cannot access the installer, contacting NXP or PEmicro support with the exact MCU and debugger model would be the safest way to obtain a supported legacy package.
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S32R264 – CLK_OUT0 (CLKOUT) 限制为 60 MHz,我可以输出 80 MHz 吗? #S32R2X 我使用的是S32R264。我有一个关于 CLK_OUT0 的问题(图 6-3 显示了通过 RM 中的 MCB_CLKOUT_SEL 选择 CLKOUT),以及是否可以在该引脚上以 80 MHz 的频率输出 SDPLL_CLK80/AFEPLL_CLK80。 然而,表 5-3(“最大系统级时钟频率”)指出 CLK_OUT[01] 的最大频率为 60 MHz,但没有解释此限制的原因。 我注意到只有一个输出端连接了 CMU——也许这就是原因,但我不用 CMU。 我需要为产生啁啾信号的外部前端板提供 80 MHz 的时钟信号,并且我希望所有信号都使用同一个时钟源。 目前我有两个独立的 100 MHz 振荡器(CWX813‑040.0M 用于 MCU,CWX813‑100.0M 用于前端)。我怀疑即使是性能优良的独立振荡器,也可能由于相位不一致而降低信号质量。我的波形生成器运行在 100 MHz 时钟频率下,而 MCU 内部的 AFE 运行在 40 (320) MHz 时钟频率下。我想将波形生成频率切换到 80 MHz,并从 MCU 获取该时钟信号,以便整个系统同步且同相。 如果 CMU 被禁用,是否可以在 CLK_OUT0 上输出 80 MHz 信号? 60 MHz 频率限制的真正原因是什么?
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S32R264 – CLK_OUT0 (CLKOUT) limitation to 60 MHz, can I output 80 MHz? #S32R2X I am using S32R264. I have a question about CLK_OUT0 (Figure 6-3 shows CLKOUT selection via MCB_CLKOUT_SEL in RM) and the possibility to output SDPLL_CLK80/AFEPLL_CLK80 at 80 MHz on this pin. However, Table 5‑3 ("Maximum system level clock frequencies") says the max frequency for CLK_OUT[01] is 60 MHz, with no explanation for this restriction. I noticed only one output has a CMU attached – maybe that's the reason, but I don't use CMU. I need to provide 80 MHz to an external Frontend board that generates Chirp, and I want a single clock source for everything. Currently I have two separate 100 MHz oscillators (CWX813‑040.0M for MCU, CWX813‑100.0M for Frontend). I suspect that even good independent oscillators may degrade signal quality due to lack of phase alignment. My waveform generation runs from the 100 MHz clock, while the AFE inside MCU runs from 40 (320) MHz. I would like to switch waveform generation to 80 MHz and take that clock from MCU, so the whole system is synchronous and in phase. Is it possible to output 80 MHz on CLK_OUT0 if CMU is disabled? What is the real reason for the 60 MHz limit?
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IMXRT1024でヒューズを焼損させずにHABをテストする 署名のないledのblinkyコードを使ってHAB監査API(報告状況と報告イベント情報)を実装しました。EVKボードは開いており、ヒューズも焼けていません 署名なしイメージ(CSF=0) - HABが4イベント情報で失敗 署名画像 - HAB パス0イベント情報 なので、ボードでもオープンHAB認証が実行されているのでイベント情報が見られると仮定しました。 しかし今回は同じIVT(CSF=0)でプロジェクトファームウェアを使い、同じHAB監査を実施しました 署名なし画像 - 0 イベント情報 のHABパス リードされた点滅ログ(署名なし): RVTヘッダー 0x 2002c0: tag=0xdd len=0x 038 par=0x43 HAB:RVTバージョン=0x 40305 居住区:report_status() = 0x33(HAB_FAILURE) HAB: config = 0xf0(HAB_CFG_OPEN) HAB: state = 0x66(HAB_STATE_NONSECURE) HAB: event[0], 8バイト HAB: hdr: tag=0xdb len=0x 0 8 par=0x43 HAB: status=0x33(HAB_FAILURE) reason=0x22(HAB_INV_ADDRESS) context=0x a(HAB_CTX_AUTHENTICATE) engine=0x 0(HAB_ENG_ANY) HAB: raw: db 0 8 43 33 22 a 0 HAB: event[1], 20バイト HAB: hdr: tag=0xdb len=0x 014 par=0x43 HAB: status=0x33(HAB_FAILURE) reason=0x c(HAB_INV_ASSERTION) コンテキスト=0xa0(HAB_CTX_ASSERT) engine=0x 0(HAB_ENG_ANY) HAB: raw: db 0 14 43 33 c a0 0 0 0 0 0 0 60 0 10 0 0 0 0 20 HAB: event[2], 20バイト HAB: hdr: tag=0xdb len=0x 014 par=0x43 HAB: status=0x33(HAB_FAILURE) reason=0x c(HAB_INV_ASSERTION) context=0xa0(HAB_CTX_ASSERT) engine=0x 0(HAB_ENG_ANY) HAB: raw: db 0 14 43 33 c a0 0 0 0 0 0 60 0 10 20 0 0 0 1 HAB: event[3], 20バイト HAB: hdr: tag=0xdb len=0x 014 par=0x43 HAB: status=0x33(HAB_FAILURE) reason=0x c(HAB_INV_ASSERTION) コンテキスト=0xa0(HAB_CTX_ASSERT) engine=0x 0(HAB_ENG_ANY) HAB: raw: db 0 14 43 33 c a0 0 0 0 0 0 0 60 0 20 0 0 0 4 HAB: VERDICT = 4 イベント情報 記録済み -- 上記のデコード済みフィールドを参照 私のプロジェクトファームウェア(署名なし) HAB: RVTヘッダー 0x002002c0 HAB: tag=0xdd len=0x0038 par=0x43 HAB:RVTが確認され有効 居住区:RVTバージョン=0x00040305 居住区:report_status() = 0xf0 HAB: config = 0xf0 HAB: state = 0x66 HAB: 監査イベント情報やクエリなし... HAB: report_event(idx=0) 0x33返されました(イベント情報やクエリなし) HAB: VERDICT = PASS(監査イベント情報なし) なぜ違いがあるのか Re: Test HAB on IMXRT1024 without burning fuses こんにちは、 @Abhay2080 さん。 ご連絡ありがとうございます!LED点滅コードが入っているSDK版と、画像作成に使われているSPT版の両方をいただけますか? ご辛抱いただきありがとうございます! すてきな一日を、 カン ------------------------------------------------------------------------------- 注記: この投稿があなたの質問への回答になっている場合は、「正解としてマーク」ボタンをクリックしてください。ありがとうございます! - 前回の投稿から7週間Threadをフォローしており、その後の返信は無視しています もし後で関連する質問があれば、新しいThreadを開き、閉じたThreadを参照してください。 -------------------------------------------------------------------------------
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CIRサンプル・トゥ・タップ・インデックス・マッピングおよびSR150におけるファーストパス後のセカンダリーピークに関する質問 こんにちは、 私は以下のデバイス、SDK、ファームウェアを使用しています。 ・対象デバイス:村田製作所製 2BP EVK型(NXP Trimension SR150) ・SDKバージョン:v05.11.05 ・ファームウェア:PNP_RhodesV4_SE_v05.11.05.bin SR150から取得したCIRデータに関して、2つ質問があります。 1. CIRサンプルとタップ指数の関係 SR150から取得された16のCIRサンプルと対応するTap Indexとの関係について、説明していただけますか? 私の理解では、16個のCIRサンプル(cir[0]からcir[15]まで)には、それらの絶対タップインデックスを直接示す情報は含まれていません。 cir[0]に対応するタップインデックスを特定する方法、または計算式はありますか? また、診断情報で利用可能なファーストパスインデックスと配列インデックスcir[0]からcir[15]との関係についても理解したいと思っています。 例えば、CIRサンプリングウィンドウがFirst Path Indexを基準に決定される場合、First Path Index cir[0]の前後に何タップが対応しているかを知りたいです。 2. 第一道の直後に観測された二次峰 CIRを調べる中で、検出された第一経路の約3〜4サンプル後に比較的明確な二次ピークが現れるケースを観察しています。 添付図は、この動作の一例を示しています。 この例では、主要なCIRピークはタップインデックス834付近で観測され、別の局所的なピークは、約3タップ後のタップインデックス837付近で現れます。図中の赤い円で示されているのが、二次ピークである。 20260907.png20260907.png この二次ピークの可能な原因を説明していただけますか? 特に、これはSR150の内部相関器処理による既知または予想される応答、例えば送信・受信パルスの自己相関特性や相関応答のサイドローブなどである可能性はありますか? サポートにあらかじめ感謝いたします。 よろしくお願いいたします。 Re: Questions about CIR Sample-to-Tap Index Mapping and Secondary Peak after First Path on SR150 こんにちは、@Ricardo_Zamora さん。 ご回答とSR150のサポート経路の明確化に感謝します。 詳細な情報はNDAの下で公開できないことを理解しています。 これらの技術的な質問については、適切なモジュールパートナーまたは直接の担当者に連絡します。 改めて、サポートとご指導に感謝いたします。 よろしくお願いいたします。 Re: Questions about CIR Sample-to-Tap Index Mapping and Secondary Peak after First Path on SR150 こんにちは、 あなたの調子が良いといいのですが。ご不便をおかけして申し訳ありませんが、この製品の情報はNDA(秘密保持契約)に基づいており、公開されていません。 チップについての詳細は、代理店ネットワークで利用可能な当社の代理店のいずれかにお問い合わせください。NXPですか?または、このデバイスを手に入れるのを手伝った直接の連絡先がいれば、ぜひ連絡してください。 もし当社のUWB製品に関する情報をお探しの方やこのテクノロジに興味がある方は、パートナー(Trimension UWB Partners)のこれらの開発キットとモジュールをご確認いただくことをお勧めします。 これらのキットやモジュールに興味がある場合は、直接彼らに相談してプロセスやサポートを受けられるかを知る必要があります。なぜなら、このテクノロジのサポートは彼らを通じて行われるからです。 ドキュメントとソフトウェアは対応するUWBモジュールパートナーによって配布されます。モジュールを選択すると、パートナーのページに案内され、データシート、アプリケーションノート、必要なイネーブルメントにアクセスできます よろしくお願いいたします。 リカルド
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S32k344 MBIST LBIST I'm in the process of implementing S32k344 BISTs in a green hills project. I'm using  SW32K3_SPD_1.0.6_D2512 in the source code form since I don't use Tresos or NXP DS. I was able to import most of the bist functions, except few defines that I'm not sure about (can't find them anywhere). Can anybody answer below questions. 1. Can I run LBIST MBIST while S32k344 is in lock step mode? 2. Is the following defines correct, I guessed by examining the code? #define BIST_MBIST_0 1U #define BIST_MBIST_1 2U #define BIST_MBIST_2 3U #define BIST_MBIST_3 4U #define BIST_MBIST_4 5U #define BIST_MBIST_5 6U #define BIST_MBIST_6 7U #define BIST_MBIST_7 8U #define BIST_MBIST_8 9U #define BIST_MBIST_9 10U #define BIST_MBIST_10 11U #define BIST_LBIST_0 0U the config data I used are as follows: static const BIST_CHANNEL_CONFIG_TYPE BistConfig[BIST_SAFETYBOOTCFG_NB] = { { (BIST_CHANNEL_TYPE)BIST_MBIST_0, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_1)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_1, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_2)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_2, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_3)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_3, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_4)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_4, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_5)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_5, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_6)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_6, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_7)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_7, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_8)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_8, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_9)) }, //#endif { (BIST_CHANNEL_TYPE)BIST_MBIST_9, (BIST_CONTROL_TYPE)((0x80100000U) | BIST_MBIST_PTR_VAL(BIST_MBIST_10)) }, { (BIST_CHANNEL_TYPE)BIST_MBIST_10, (BIST_CONTROL_TYPE)(0x00100000U) }, { (BIST_CHANNEL_TYPE)BIST_LBIST_0, (BIST_CONTROL_TYPE)((0x00001108U) | BIST_LBIST_PTR_VAL(BIST_NIL)) } }; Re: S32k344 MBIST LBIST Hello, 1. Can I run LBIST MBIST while S32k344 is in lock step mode? Yes. The S32K344 lockstep architecture does not prevent execution of STCU2 LBIST/MBIST. The BIST mechanism is part of the device safety infrastructure and is designed to test logic and memories managed by STCU2. The S32K3 Safety Manual explicitly lists both lockstep and STCU2 LBIST/MBIST as safety mechanisms of the device. 2. Is the following defines correct, I guessed by examining the code? The numerical values are essentially correct for S32K344, but including MBIST_10 (HSE_ROMs) in the Safety Boot configuration is not required from a safety perspective, and the recommended path is to use the validated SPD configurations directly. Best regards, Peter Re: S32k344 MBIST LBIST Peter,   Thank you very much for replying. I have been stuck with this BIST test issues for few days now. I'm testing with S32k344 White board, code is build with green hills multi IDE rev 8.1. The safety boot BIST is not passing. I'm sure the max clock requirement is met for core and peripherals. I have core_clk at 160Mhz from external crystal 16Mhz and PLL, AIPS_PLAT_CLK is 80Mhz, AIPS_SLOW_CLK is 40Mhz, DCM_CLK as 40 MHz, LBIST_CLK is 40Mhz,  QSPI_MEM_CLK is 160Mhz. I have this error when unit reset from bist run, DES register has 0x00408175, few reserved bits get set, and FES register has 0x2000 (doesn't make sense). would you kindly answer following questions? 1. with all the clock signals mentioned above, should they be enabled through MC_CGM->MUX_0_DC_x registers? I'm getting conflicting information, currently they are enabled. 2. In the reference manual, STCU2 chapter, there is this "While running MBIST on EMAC time stamp memory, MC_CGM.MUX_9_DC_0[DIV] should be appropriately configured to ensure EMAC_CLK_TS should be at least 1.5 times the AIPS_SLOW_CLK frequency." does that mean I have to config configure the clock and enable it in the MC_CGM->MUX_9_DC_0 register? 3. If I want to see the example code S32_SPD_Demo in SW32K3_SPD_1.0.6_D2512 package, I guess I need to install latest NXP design studio, import the spd zip file as update site, and also the RTD package, is that right? 4. I believe MBIST 10 is HSE_RAMS, MBIST 11 is HSE_ROMS, please see the table below from SPD doc folder. MBIST BIST ID BIST Instance Name Reset Domain Safety Boot Safety Diagnostic 0 SYS0_RAMS Main ü ü 1 SYS1_RAMS Main ü ü 2 DMA_TCD_RAM Main ü ü 3 CM7_0_TOP Main ü ü 4 CM7_1_TOP Main ü ü 5 FLEX_CAN_RAMS Main ü ü 6 QSPI_PERI_RAMS Main ü ü 7 EMAC_TSN_RAM Main ü ü 8 EMAC_RAMS Main ü ü 9 b03_ETF_RAMS Main ü ü 10 HSE_RAMS Main ü ü 11 HSE_ROMS Main   ü Re: S32k344 MBIST LBIST An update to my problem, after I enabled bit 8 and 9 in the STCU_RUNSW_REG to use PLL, I'm consistently seeing DES register 0x11 and FES register of 0x10. The bist_get_exec_status(BIST_SAFETYBOOT_CFG) return value is NOT RUN (0x03). There is nothing in the BIST ERR_STAT register, none of the END flag is set. In the FCCU NCF_S0 register, bit 2 is set. It seems BIST didn't start, but I do see the reset. I captured the register setting by writing to flash in the other bank. Re: S32k344 MBIST LBIST Hello, the STCU self-test sequence is being entered and reaches the ST_DONE reset phase. However, the STCU also reports an unrecoverable fault (STCU_URF), which explains why the SAF BIST driver subsequently reports BIST_NORUN. The issue therefore appears to be an STCU execution/configuration failure rather than a case where BIST was never triggered. On S32K3, seeing both a destructive and functional reset indication simultaneously is often a sign that you are looking at a reset history, not necessarily the immediate reset source Since you are porting the SW, I would start with simply just MBIST only test to see if it pass sourced from PLL. Also I would double check the clock settings for the tests. Best regards, Peter Re: S32k344 MBIST LBIST I checked the all possible clocks, I believe they are correct. I also compared the config data in the register with values from NXP studio spd example project, they are also correct. One new information. After system come back from BIST reset, I see value 0x18 in DCMROD3 register. How do I resolve this error? Thanks. XRen_Parker_0-1788544110794.pngXRen_Parker_0-1788544110794.pngXRen_Parker_0-1788544110794.png Re: S32k344 MBIST LBIST Hello, On S32K344, RCCU reports lockstep mismatches, and when connected with a debugger, it is not uncommon to get RCCU-related faults that would never occur in standalone execution. In case you follow the setting from example, you are looking at full BIST. Example is tested and it is fully working by default. But your port reporting URF fault, which tells me not everything is identical. Looking at STCU documentation user can set pointer to tests. 54.9.4 STCU2 Configuration (CFG) petervlna_0-1788766597312.pngpetervlna_0-1788766597312.png You can try shrinking tests first and the slowly add more tests. In MBIST and LBIST control registers you can set which test will be last: petervlna_1-1788766735386.pngpetervlna_1-1788766735386.png By pointing to for example in CFG register you can execute single MBIST partition: petervlna_2-1788766853581.pngpetervlna_2-1788766853581.png petervlna_3-1788766973925.pngpetervlna_3-1788766973925.png Best regards, Peter
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CodeWarriorとPEmicro MultilinkをMCU MKL03Z16VFK4Rに接続 こんにちは、 私はMCU MKL03Z16VFK4Rを持っており、P Emicro Multilink Universalを使用してWindows XP上でこれをプログラムする必要があります。私が収集した情報によると、WinXPをサポートするCodeWarrior 10.6が存在するようです。 CodeWarrior 10.6のソフトウェアインストーラーを共有していただけますか? または、Windows XPをサポートする他のソフトウェアはありますか? よろしくお願い申し上げます。 Re: CodeWarrior and PEmicro Multilink to MCU MKL03Z16VFK4R こんにちは、 @Chalearmratさん 投稿ありがとうございます。 利用可能なCodeWarrior 10.6インストーラーはありません。CodeWarriorのダウンロードページ(NXP Semiconductors)で、利用可能なCodeWarriorのさまざまなバージョンをご確認ください。 Kinetisに推奨されるバージョンはCodeWarrior for MCUs 11.1(Windows 11で使用可能)ですが、KL03のサポートは含まれていません。 carlos_o_0-1778783252765.pngcarlos_o_0-1778783252765.png KL0xシリーズはMCUXpresso IDEでサポートされており、SDKはMCUXpresso SDK Builderからダウンロードできます。 carlos_o_1-1778783488621.pngcarlos_o_1-1778783488621.png Re: CodeWarrior and PEmicro Multilink to MCU MKL03Z16VFK4R こんにちは、 CodeWarrior 10.6はかなり古いバージョンであり、公式インストーラーはもはや容易に入手できない可能性があります。PEmicro Multilink UniversalをMKL03Z16VFK4Rする場合は、NXPのCodeWarriorのアーカイブダウンロードや、Windows XP対応のPEmicroのレガシーソフトウェア・ツールを確認することをお勧めします。インストーラーにアクセスできない場合は、正確なMCUとデバッガモデルをNXPまたはPEmicroサポートに問い合わせるのが、サポートされているレガシーパッケージを入手する最も安全な方法です。
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Test HAB on IMXRT1024 without burning fuses I have taken unsigned led blinky code and implemented HAB audit API (report status and report event). EVK board is open and fuses not burnt Unsigned image(CSF=0) - HAB fail with 4 events Signed image - HAB pass 0 events  So i assumed that even board is open HAB authentication runs and hence i can see events. But now i taken project firmware with same IVT (CSF=0) and i implemented same HAB audit but this time Unsigned image - HAB pass with 0 events Led blinky logs (unsigned): RVT header at 0x 2002c0: tag=0xdd len=0x 038 par=0x43 HAB: RVT version = 0x 40305 HAB: report_status() = 0x33(HAB_FAILURE) HAB: config = 0xf0(HAB_CFG_OPEN) HAB: state = 0x66(HAB_STATE_NONSECURE) HAB: event[0], 8 bytes HAB: hdr: tag=0xdb len=0x 0 8 par=0x43 HAB: status=0x33(HAB_FAILURE) reason=0x22(HAB_INV_ADDRESS) context=0x a(HAB_CTX_AUTHENTICATE) engine=0x 0(HAB_ENG_ANY) HAB: raw: db 0 8 43 33 22 a 0 HAB: event[1], 20 bytes HAB: hdr: tag=0xdb len=0x 014 par=0x43 HAB: status=0x33(HAB_FAILURE) reason=0x c(HAB_INV_ASSERTION) context=0xa0(HAB_CTX_ASSERT) engine=0x 0(HAB_ENG_ANY) HAB: raw: db 0 14 43 33 c a0 0 0 0 0 0 60 0 10 0 0 0 0 20 HAB: event[2], 20 bytes HAB: hdr: tag=0xdb len=0x 014 par=0x43 HAB: status=0x33(HAB_FAILURE) reason=0x c(HAB_INV_ASSERTION) context=0xa0(HAB_CTX_ASSERT) engine=0x 0(HAB_ENG_ANY) HAB: raw: db 0 14 43 33 c a0 0 0 0 0 0 60 0 10 20 0 0 0 1 HAB: event[3], 20 bytes HAB: hdr: tag=0xdb len=0x 014 par=0x43 HAB: status=0x33(HAB_FAILURE) reason=0x c(HAB_INV_ASSERTION) context=0xa0(HAB_CTX_ASSERT) engine=0x 0(HAB_ENG_ANY) HAB: raw: db 0 14 43 33 c a0 0 0 0 0 0 60 0 20 0 0 0 0 4 HAB: VERDICT = 4 EVENT(S) LOGGED -- see decoded fields above but  my  project firmware(unsigned) HAB: RVT header at 0x002002c0 HAB: tag=0xdd len=0x0038 par=0x43 HAB: RVT found and valid HAB: RVT version = 0x00040305 HAB: report_status() = 0xf0 HAB: config = 0xf0 HAB: state = 0x66 HAB: querying audit events... HAB: report_event(idx=0) returned 0x33 (no events or query HAB: VERDICT = PASS (no audit events logged) Why there is a difference  Re: Test HAB on IMXRT1024 without burning fuses Hi @Abhay2080 , Thanks for the reaching out! May I have the sdk version that has the led blinky code and the SPT version used for building the image?  Thank for your patience! Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
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