Multi Source Translation Content

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Multi Source Translation Content

Discussions

Sort by:
S32K324 FlexIO SPI Master Emulation (S32DS 3.5 / RTD 4.0.0 ) Hello, I am configuring a FlexIO-emulated SPI Master on an S32K324 to communicate with an external SPI slave device. Due to trace routing on our custom board, the physical lines targeting this device are wired to the chip's default FlexSPI0 pins. Therefore, I must use the emulated Flexio_Spi driver stack. this is my setup BUS_FLEXSPI0_UP_SBC_CS PTD8 fxio_d11 BUS_FLEXSPI0_UP_SBC_CLK PTD9 fxio_d0 BUS_FLEXSPI0_UP_SBC_MOSI PTD15 fxio_d10 BUS_FLEXSPI0_UP_SBC_MISO PTD22 fxio_d27 My Environment: IDE:S32 Design Studio for S32 Platform (Version: 3.5, Build id: 240726 Update 13) CPU : S32K324 SDK: Real-Time Drivers (RTD) Version 4.0.0 (Production Release) Is there an official NXP application note or guide that illustrates the end-to-end integration stack specifically for RTD 4.0.0? I need a reference that covers everything from assigning the pins in the tool, mapping the shifters/timers, up to initializing the driver in the main application code. Re: S32K324 FlexIO SPI Master Emulation (S32DS 3.5 / RTD 4.0.0 ) Hello @Kazarian , There is no dedicated application note, to my knowledge, that describes the full end-to-end integration of FlexIO-emulated SPI specifically for S32K324 with RTD 4.0.0 and with this exact pin assignment. The closest official reference is the example project included in the S32K3 RTD package. Please check the RTD example similar to  Lpspi_Flexio_Ip_Transfer_S32K344. This example demonstrates the intended RTD integration flow for FlexIO-based SPI transfer, including the FlexIO SPI driver initialization and the relation between LPSPI and FlexIO SPI instances.   For your custom board, the main points to adapt are the following (as a general guidance): Pins configuration Configure the listed pins in the Pins tool as FlexIO signals: PTD8 → FXIO_D11, chip select PTD9 → FXIO_D0, clock PTD15 → FXIO_D10, MOSI PTD22 → FXIO_D27, MISO Make sure the MISO pin has the input buffer enabled. Also verify in the S32K324 IOMUX/pinout documentation that these FlexIO functions are available for your exact package. FlexIO SPI configuration In the FlexIO SPI configuration, map the SPI signals to the corresponding FlexIO pin numbers, not only to the physical MCU pins: SCK = FXIO_D0 MOSI = FXIO_D10 CS = FXIO_D11 MISO = FXIO_D27 Assign the required FlexIO timers and shifters consistently with the generated configuration. Best regards, Pavel
View full article
IMX8MP On chip RAM memory access Hello, I want to learn how I can access the OCRAM  to read and data to the memory. Can anyone advice how I could achieve that on Linux cortex A-53? On-Chip RAM - OCRAM (576 KB) start address: 0x00900000 => reserved for ROM start address: 0x00918000  =>OCRAM FREE AREA end address: 0x0097FFFF https://www.nxp.com/webapp/Download?colCode=IMX8MPRM  Thank you! IMX8MPLUS  i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Yocto Project Re: IMX8MP On chip RAM memory access Hi Roman Luz, does this tip works for you? Regards, Stefano Gigli Re: IMX8MP On chip RAM memory access Hi @Roman_Loz , you could try including compatible = "shared-dma-pool"; and it should work. ocram_dma: ocram_dma@970000 { no-map; compatible = "shared-dma-pool"; reg = <0 0x970000 0 0xC00>; // 3KB }; Regards, Samhitha Kashyap Re: IMX8MP On chip RAM memory access Hi, I am trying to use the OCRAM the way you suggested but I get kernel panic when I try to memcpy to/from it. Could you please help me understand what am I doing wrong or missing? dtsi: resmem: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; ocram: ocram@900000 { no-map; reg = <0 0x900000 0 0x70000>; }; ocram_dma: ocram_dma@970000 { no-map; reg = <0 0x970000 0 0xC00>; // 3KB }; ... module init: // Find the OCRAM DMA node by name np = of_find_node_by_name(NULL, "ocram_dma"); if (!np) { pr_err("Failed to find OCRAM DMA node in device tree\n"); return -ENODEV; } // Lookup the reserved memory region rmem = of_reserved_mem_lookup(np); if (!rmem) { pr_err("Failed to lookup reserved memory for OCRAM DMA\n"); return -ENODEV; } // Map the reserved memory region ocram_dma_base = ioremap(rmem->base, rmem->size); if (!ocram_dma_base) { pr_err("Failed to map OCRAM DMA memory\n"); return -ENOMEM; } copy: memcpy(current_address, mv->A, MATRIX_STRUCT_SIZE);   Re: IMX8MP On chip RAM memory access Hi @Samhitha_Kashyap, Please note that the NXP does not recommend the modification in the node for 448 KB OCRAM Space as it is used by other drivers. One can use memory regions after 0x970000 to Support DMA using the compatible = "shared-dma-pool" property. Thanks & Regards Sanket Parekh Re: IMX8MP On chip RAM memory access Hi @Sanket_Parekh, Thanks for the response, it was helpful!  Would it be possible for me to modify the device tree to support DMA within the 448 KB OCRAM space, if I can't use it for the user application? Thanks & Regards, Samhitha Kashyap Re: IMX8MP On chip RAM memory access Hi @Samhitha_Kashyap , I hope you are doing well.   You can determine how much memory in the OCRAM, Linux kernel Reserved for itself by looking into the dtsi file (reserved memory node) of the soc in the case of imx8mp, it is 448 KB.   resmem: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; ocram: ocram@900000 { no-map; reg = <0 0x900000 0 0x70000>; };   ..... .....   }   So here 0x70000 ( 448K) bytes are reserved for Linux usage. and cannot be virtually mapped to the userspace as specified by the no-map property. after 0x7000 bytes you can use it for other applications. But you need to make sure that any  M7 core Application not using OCRAM. which can be determined by looking into the Linker script of a particular application.   Thanks & Regards Sanket Parekh   Re: IMX8MP On chip RAM memory access Hi Sanket, Would it be possible to verify how much memory the Linux utilizes and the rest can be used for the user application. If it is possible, how could I verify the same and allocate the rest of the memory for my application.  Thanks & Regards, Samhitha Kashyap Re: IMX8MP On chip RAM memory access Hi @Samhitha_Kashyap  I hope you are doing well. To access OCRAM First you need to ensure that you don't try to access the region that is used by ATF. in the case of u-boot, one can use md/mw command to access OCRAM directly. It is not recommended to use OCRAM in userspace as Linux itself uses it. Thanks & Regards Sanket Parekh
View full article
Question about RW612 OTBR Thread Certification Architecture Hello NXP Team,   I noticed the Thread Group certified component:   "NXP RW612 Wireless MCU With Integrated Tri-Radio OTBR" (Thread 1.4)   I also found separate certifications for:   - NXP i.MX MPU With IW610 Tri-Radio OTBR - NXP i.MX MPU With IW612 Tri-Radio OTBR - NXP RW612 Wireless MCU With Integrated Tri-Radio OTBR   I would like to better understand the certification architecture used for the RW612 OTBR certification.   Could you please clarify:   1. Was the certification achieved using RW612 as a standalone MCU/RTOS-based Thread Border Router?   2. Was an external RCP/NCP device used in the certified configuration?   3. Which software platform was used during certification (FreeRTOS, Zephyr, or another platform)?   4. Is there any public reference design or documentation describing the certified RW612 OTBR implementation?   Our goal is to understand whether the RW612 OTBR certification represents a standalone MCU-based Thread Border Router solution rather than a Linux-host-based OTBR architecture.   Thank you for your support.   Best regards, Kyonghwan Cho   Re: Question about RW612 OTBR Thread Certification Architecture Hello, Hope you are doing well. My name is Ricardo and I have been assigned this case. A1: Yes. The RW612 OTBR certification is a true standalone, single-chip solution. A2: No. Unlike the i.MX MPU + IW610/IW612 OTBR certifications (which use a Linux host with an external IW6xx radio co-processor in RCP mode), the RW612 certification does not use any external RCP or NCP device. A3: Let me confirm. A4: For specific details on the test configuration, test reports, or certification scope, please contact the Thread Group directly at threadgroup.org. Best Regards, Ricardo Re: Question about RW612 OTBR Thread Certification Architecture Hello @KyonghwanCho , Thank you for your patience. I have the confirmation that the SW platform used was FreeRTOS. Also, please check below OTBR user guide and build guide ot-nxp/examples/br/README-OTBR.md at release/v1.4.0.5_26.03 · NXP/ot-nxp ot-nxp/src/rw/rw612/README.md at release/v1.4.0.5_26.03 · NXP/ot-nxp Best Regards, Ricardo
View full article
I need to configure DMA for SPI I am using S32DS IDE and RTD 3.0 can anyone tell me how to start the DMA with SPI with step by step instructions or any other example code if available Re: I need to configure DMA for SPI Thank you for your response Do this work for s32k322 MCU Re: I need to configure DMA for SPI Hi @ershi  Included with the RTDs are provided two example codes for SPI communication using DMA, one using Low-Level Drivers (Ip) and one using High-Level Drivers (MCAL). You can refer to the thread HOWTO: S32 Design Studio - Create a New S32DS Project from Example for guidance on how to import the examples. Also, you can refer to the example provided in the thread Example S32K31 SPI Multiple Packet Transmit & Receive: Solution for DMA Cache Issue. BR, VaneB Re: I need to configure DMA for SPI Hi @ershi  Although the examples are not specifically designed for the S32K322, the functionality is generally the same across the S32K3 family, unless otherwise stated in the Reference Manual Therefore, you can use this project as a reference for your implementation and adapt it as needed for your specific device. Re: I need to configure DMA for SPI I had configurated everything but still it is not working initially it is return as LPSPI_IP_STATUS_SUCCESS  for (Lpspi_Ip_AsyncTransmit )and second time it is showing failed LPSPI_IP_STATUS_FAIL  I can able to send the data through spi using this api without the dma Lpspi_Ip_SyncTransmit() I have attached few configuration screenshot  Re: I need to configure DMA for SPI Hi @ershi  Could you also share images of the RM and IntCtrl_Ip driver configurations? Re: I need to configure DMA for SPI Hi @VaneB  I've attached the screenshots for the RM and IntCtrl_IP driver configurations, along with a short video clip for your detailed reference. I noticed one difference in the LPSPI configuration page. In the SPI General tab, under Spi_Phy_TxDmaChannel, the naming is different between the TX and RX configurations. Please let me know if you need any additional details InterruptsInterruptsInterruptsInterruptsInterruptsInterruptsInterruptsInterruptsInterrupts RMRMRMRMRMRMRMRMRM Re: I need to configure DMA for SPI Hi @ershi  Thank you for sharing all the information. I just have one observation. In the Dma_Ip driver configuration, you have defined DMA_SPI_CALLBACK_0 as the Interrupt Callback. However, the LPSPI DMA callbacks are already provided by the driver and can be found in the Lpspi_Ip_Irq.c file. For LPSPI2, the configured callbacks should be: Lpspi_Ip_LPSPI_2_IrqTxDmaHandler for the TX DMA channel Lpspi_Ip_LPSPI_2_IrqRxDmaHandler for the RX DMA channel Re: I need to configure DMA for SPI Hi @VaneB  Thank you for the clarification. I updated the Dma_Ip configuration so that, for LPSPI2, the TX and RX DMA channels now use the callbacks from Lpspi_Ip_Irq.c: Lpspi_Ip_LPSPI_2_IrqTxDmaHandler for the TX DMA channel Lpspi_Ip_LPSPI_2_IrqRxDmaHandler for the RX DMA channel nxp However, the DMA-based LPSPI transfer is still not working as expected on my side. I have attached a screenshot of the current configuration for your reference. If there are any additional settings, I should adjust please let me know Re: I need to configure DMA for SPI Hi @ershi  Could you please let me know how you are implementing the SPI communication? Also, have you test the code from the example I shared previously? Re: I need to configure DMA for SPI Hi @ershi  Are you connecting the LPSPI2 SOUT signal directly to SIN, or are you using a logic analyzer to verify the transmitted and received data? Re: I need to configure DMA for SPI Hi @VaneB       I have deleted the previous configuration and now the SPI data is transmitting through DMA, but the problem is that the data is not matching  #define RX_MSG_SIZE (15U) #define TX_MSG_SIZE (15U) uint8_t txBuffer_check[TX_MSG_SIZE] = {0x48,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x10,0x11,0x12,0x13,0x14,0x15}; uint8_t rxBuffer_check[]={0};  if(Lpspi_Ip_AsyncTransmit(&Lpspi_Ip_DeviceAttributes_SpiExternalDevice_1_Instance_2_BOARD_InitPeripherals,txBuffer_check,rxBuffer_check,TX_MSG_SIZE,spi_DMA_Function) == LPSPI_IP_STATUS_SUCCESS) { Dma_Ip_ReturnType status = {0},status1 = {0}; Dma_Ip_LogicChannelStatusType channelStatus ={0},channelStatus1 ={0}; status = Dma_Ip_GetLogicChannelStatus(DMA_LOGIC_CH_0,&channelStatus); status1 = Dma_Ip_GetLogicChannelStatus(DMA_LOGIC_CH_1,&channelStatus1);    return SYS_SUCCESS; }   Re: I need to configure DMA for SPI Hi @VaneB, I have rewritten the code and it is working perfectly now. The data is coming in correctly. Thank you for your assistance. Re: I need to configure DMA for SPI Hi @VaneB  In our previous discussion about configuring DMA for SPI. I have noticed the RX buffer data is not matching with the logic analyser data Tx buffer is working perfectly working well. I have added detailed information in the dropbox.
View full article
S32K3 ADC Optimize DMA Streaming Hello, When the adc group has only one channel and the Adc Enable Optimize DMA Streaming Groups configuration item is checked, a hard fault occurs when the Adc_Ipw_SetupTcdSingleAdcChannelMajorLink function is executed. In the case of a single channel, if the Adc Group Without Interrupts configuration item is checked and ACCESS_MODE_STREAMING, Select Adc Streaming Dma Channel is enabled. Otherwise, the number of the dma channel in the configuration file is 255, which is reasonable here. But what I don't understand is why when ADC_ENABLE_GROUP_STREAMING_RESULTS_RORDER or ADC_OPTIMIZE_DMA_STREAMING_GROUPS is STD_ON, instead of STD_ON==GroupPtr ->AdcWithoutInterrupt, the Adc_Ipw_SetupTcdSingleAdcChannelMajorLink function will be called. This seems unreasonable, and also because the call to this function leads to hard fault. BR, Jason Re: S32K3 ADC Optimize DMA Streaming Hi@Jason22 Please do not use your QQ email account next time; please use your company email account instead. I tested this, but I didn't find any problems. I have attached my test project and test result for your reference. Also, i check your code and i found some error in your code. 1.clock init is wrong, your code can't not run successfully, 2."adc_group0_val" should be attribute to "no-cacheable area" also: The usage instructions for Optimize DMA streaming groups are clearly explained in the user manual. RTD_ADC_UM.pdf
View full article
i.MX8MP SError. remote proc starts M7 core and arecord plughw:wm8962audio,0 Hi, On FRDM-i.MX8MP (Linux 6.12.34-lts-next), ALSA capture on wm8962 works fine until the Cortex-M7 is started via remoteproc. After any M7 firmware starts, arecord triggers a kernel panic.   Summary: - Without M7: arecord OK - After starting M7: panic in fsl_sai_runtime_resume → regmap_write (SError 0xbf000002) - Reproduced with BSP stock firmwares: - imx8mp_m7_DDR_hello_world.elf - imx8mp_m7_DDR_rpmsg_lite_str_echo_rtos.elf So this does not look specific to our custom M7 app.   Reproduce: 1) Boot Linux, keep M7 stopped 2) arecord -D plughw:wm8962audio,0 -f S16_LE -r 16000 -c 1 -d 1 /tmp/t.wav → OK 3) echo stop > /sys/class/remoteproc/remoteproc0/state echo imx8mp_m7_DDR_hello_world.elf > /sys/class/remoteproc/remoteproc0/firmware echo start > /sys/class/remoteproc/remoteproc0/state 4) same arecord → Kernel panic (SError)   Panic path (abbreviated): snd_pcm_capture_open → ... → fsl_sai_runtime_resume → regmap_write → SError 0xbf000002   Tried: - Remove optional "audio" (AUDPLL) clock from imx8mp-cm7 DT node → still fails - Disable AudioMIX ownership / Audio PLL init in our M7 clock_config → still fails with stock hello_world anyway   Questions: 1) Is concurrent use of Linux SAI/wm8962 and M7 remoteproc supported on i.MX8MP? 2) Does SDK BOARD_BootClockRUN() mapping AudioMIX to M7 conflict with A53 audio power domain? 3) Any known 6.12 fixes for AudioMIX / fsl_sai runtime resume SError? 4) Recommended clock_config for M7 when audio must remain owned by Linux (UART/RPMsg only on M7)?   Thanks.   ------------------------- imx8mp-cm7 dts node -------------------------- imx8mp-cm7 {         compatible = "fsl,imx8mn-cm7";         rsc-da = <0x55000000>;         clocks = <&clk IMX8MP_CLK_M7_DIV>;              //<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;         clock-names = "core", "uart4";         mbox-names = "tx", "rx", "rxdb";         mboxes = <&mu 0 1               &mu 1 1               &mu 3 1>;         memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>,                 <&m4_reserved>;         status = "okay";         fsl,startup-delay-ms = <500>;     };   ------------------ Panic log ------------------ root@FRDM-test:/lib/firmware# echo imx8mp_m7_DDR_hello_world.elf > /sys/class/remoteproc/remoteproc0/firmware root@FRDM-test:/lib/firmware# echo start > /sys/class/remoteproc/remoteproc0/state root@FRDM-test:/lib/firmware# root@FRDM-test:/lib/firmware# root@FRDM-test:/lib/firmware# root@FRDM-test:/lib/firmware# arecord -D plughw:wm8962audio,0 -f S16_LE -r 16000 -c 1 -d 1 /tmp/t_ex.wav [ 58.448085] SError Interrupt on CPU0, code 0x00000000bf000002 -- SError [ 58.448101] CPU: 0 UID: 0 PID: 644 Comm: arecord Tainted: G C O 6.12.34-lts-next #1 [ 58.448109] Tainted: [C]=CRAP, [O]=OOT_MODULE [ 58.448111] Hardware name: NXP FRDM-IMX8MPLUS (DT) [ 58.448113] pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 58.448118] pc : _raw_spin_unlock_irqrestore+0x10/0x50 [ 58.448130] lr : regmap_unlock_spinlock+0x14/0x20 [ 58.448136] sp : ffff8000854e3670 [ 58.448138] x29: ffff8000854e3670 x28: ffff8000854e3c30 x27: 0000000000000001 [ 58.448147] x26: ffff0000d06da088 x25: 0000000000000000 x24: ffff0000d06da390 [ 58.448153] x23: ffff0000d1c18f60 x22: ffff0000d0363c10 x21: 0000000001000000 [ 58.448160] x20: 0000000000000000 x19: ffff0000d14a3000 x18: 0000000000000002 [ 58.448168] x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000000 [ 58.448174] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 [ 58.448180] x11: 0000000000000000 x10: ffff0000dccabb90 x9 : 0000000000000390 [ 58.448188] x8 : ffff0000dccabbac x7 : ffff8000854e3940 x6 : ffff0000dccabba0 [ 58.448194] x5 : ffff8000808ed440 x4 : 0000000000000008 x3 : ffff8000808ece60 [ 58.448200] x2 : 0000000001000000 x1 : ffff0000dcca5280 x0 : 0000000100000001 [ 58.448208] Kernel panic - not syncing: Asynchronous SError Interrupt [ 58.448211] CPU: 0 UID: 0 PID: 644 Comm: arecord Tainted: G C O 6.12.34-lts-next #1 [ 58.448217] Tainted: [C]=CRAP, [O]=OOT_MODULE [ 58.448221] Hardware name: NXP FRDM-IMX8MPLUS (DT) [ 58.448223] Call trace: [ 58.448225] dump_backtrace.part.0+0xd4/0xe0 [ 58.448234] show_stack+0x18/0x30 [ 58.448240] dump_stack_lvl+0x60/0x80 [ 58.448246] dump_stack+0x18/0x24 [ 58.448251] panic+0x168/0x360 [ 58.448258] add_taint+0x0/0xbc [ 58.448264] arm64_serror_panic+0x64/0x70 [ 58.448269] do_serror+0x3c/0x70 [ 58.448273] el1h_64_error_handler+0x30/0x54 [ 58.448279] el1h_64_error+0x64/0x68 [ 58.448283] _raw_spin_unlock_irqrestore+0x10/0x50 [ 58.448289] regmap_write+0x58/0x80 [ 58.448294] fsl_sai_runtime_resume+0xc4/0x280 [snd_soc_fsl_sai] [ 58.448304] pm_generic_runtime_resume+0x2c/0x44 [ 58.448312] __genpd_runtime_resume+0x30/0x80 [ 58.448318] genpd_runtime_resume+0x130/0x2c4 [ 58.448325] __rpm_callback+0x48/0x1e0 [ 58.448330] rpm_callback+0x68/0x80 [ 58.448334] rpm_resume+0x3bc/0x6a0 [ 58.448340] __pm_runtime_resume+0x50/0x9c [ 58.448344] snd_soc_pcm_component_pm_runtime_get+0x3c/0x138 [ 58.448350] __soc_pcm_open+0x60/0x488 [ 58.448355] soc_pcm_open+0x30/0x58 [ 58.448359] snd_pcm_open_substream+0x594/0x850 [ 58.448364] snd_pcm_open+0x118/0x24c [ 58.448368] snd_pcm_capture_open+0x4c/0x7c [ 58.448372] snd_open+0xa0/0x19c [ 58.448379] chrdev_open+0xb0/0x21c [ 58.448386] do_dentry_open+0x138/0x4c4 [ 58.448392] vfs_open+0x2c/0xf0 [ 58.448397] path_openat+0x6fc/0x1074 [ 58.448403] do_filp_open+0xa0/0x15c [ 58.448407] do_sys_openat2+0xc8/0x100 [ 58.448413] __arm64_sys_openat+0x64/0xc0 [ 58.448420] invoke_syscall+0x48/0x104 [ 58.448427] el0_svc_common.constprop.0+0xc0/0xe0 [ 58.448433] do_el0_svc+0x1c/0x28 [ 58.448438] el0_svc+0x30/0x100 [ 58.448444] el0t_64_sync_handler+0x120/0x12c [ 58.448450] el0t_64_sync+0x190/0x194 [ 58.448458] SMP: stopping secondary CPUs [ 58.448464] Kernel Offset: disabled [ 58.448466] CPU features: 0x00,00000080,00200000,4200420b [ 58.448469] Memory Limit: none [ 58.762124] ---[ end Kernel panic - not syncing: Asynchronous SError Interrupt ]---   i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Yocto Project Re: i.MX8MP SError. remote proc starts M7 core and arecord plughw:wm8962audio,0 Hi @humm  Q1. Yes, but only if the two cannot compete for the same audio resources. Q2. Yes, there will be conflicts. In scenarios where Linux controls the audio, the M7 side must remove the AUDIOMIX mapping and the code related to power-on and SAI PLL initialization, leaving AUDIOMIX entirely to the A53/Linux's audiomix_pd management. Q3. No—because this isn't a bug in the fsl_sai driver, but rather a resource ownership configuration issue. Q4.M7 SDK BOARD_RdcInit() — The most crucial step: Removes the M7 (DID1) allocation for SAI3/SDMA3/I2C3. Remove the allocations of RDC_PDAP_SAI3, RDC_MDA_SDMA3*, RDC_PDAP_SDMA3, and RDC_PDAP_I2C3 to DID1, keeping these resources accessible to A53. B.R Re: i.MX8MP SError. remote proc starts M7 core and arecord plughw:wm8962audio,0 Hi @pengyong_zhang  Thank you very much for your guidance. Following your advice, I updated the RDC configurations to assign SDMA3 to Domain 0 (A53/Linux) and shared SAI3, I2C3, and SDMA3 permissions between Domain 0 and Domain 1. Here is the diff of the RDC changes I applied: -RDC_MDA RDC_MDA_SDMA3p DID1 0x0 0x0 +RDC_MDA RDC_MDA_SDMA3p DID0 0x0 0x0 -RDC_MDA RDC_MDA_SDMA3b DID1 0x0 0x0 +RDC_MDA RDC_MDA_SDMA3b DID0 0x0 0x0 -RDC_MDA RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0 +RDC_MDA RDC_MDA_SDMA3_SPBA2 DID0 0x0 0x0 -RDC_PDAP RDC_PDAP_SAI3 PDAP_D1_ACCESS 0x0 0x0 +RDC_PDAP RDC_PDAP_SAI3 PDAP_D0D1_ACCESS 0x0 0x0 -RDC_PDAP RDC_PDAP_SDMA3 PDAP_D1_ACCESS 0x0 0x0 +RDC_PDAP RDC_PDAP_SDMA3 PDAP_D0D1_ACCESS 0x0 0x0 -RDC_PDAP RDC_PDAP_I2C3 PDAP_D1_ACCESS 0x0 0x0 +RDC_PDAP RDC_PDAP_I2C3 PDAP_D0D1_ACCESS 0x0 0x0 After applying these changes, arecord works on Linux without triggering any SError, even while the M7 core is running its RTOS firmware. Thanks again for your help!
View full article
RW612 FLEXCOMM3/I2S3 Supporting driver We are using RW612 FLEXCOMM3/I2S3 with the following fixed hardware wiring: - GPIO24 = I2S DATA input from PCM6120 SDOUT - GPIO25 = I2S SCK output to PCM6120 BCLK - GPIO26 = I2S WS output to PCM6120 FSYNC The codec is PCM6120 in slave mode. RW612 is intended to be the I2S master generating BCLK/WS and receiving audio data. What we have verified: - GPIO25/GPIO26 can be driven correctly in plain GPIO mode - FLEXCOMM3 clock source is AUDIO PLL at 12.288 MHz - I2C communication with PCM6120 is working - PCM6120 register configuration is accepted Observed behavior: 1. FLEXCOMM3 configured as I2S RX with kI2S_MasterSlaveNormalMaster does not generate any SCK/WS edges on GPIO25/GPIO26. 2. FLEXCOMM3 configured as I2S TX with kI2S_MasterSlaveNormalMaster also does not work: FIFOSTAT.TXNOTFULL=1, but TXLVL remains 0 after writes to FIFOWR, and no SCK/WS edges appear on the pins. 3. PCM6120 reports missing clocks (ASI_STS=0xFF, DEV_STS1=0x80). Questions: 1. Is RW612 FLEXCOMM I2S RX in Normal Master mode expected to drive SCK/WS onto external pins? 2. Is a single FLEXCOMM instance supported for the use case “master clock generation + receive data from external codec”, or is a dual-FLEXCOMM architecture (TX master + RX slave with I2S bridge) required? 3. For FLEXCOMM3 I2S TX master, are there additional prerequisites for FIFO writes to be accepted beyond I2S_TxInit(), FIFOWR writes, and MAINENABLE? 4. Is there any known limitation specific to FLEXCOMM3 on GPIO24/25/26 (AON domain) for I2S clock output? Pls help about the topic Re: RW612 FLEXCOMM3/I2S3 Supporting driver Hi @duyhung, hope you are doing well. Would you please clarify if you are using FreeRTOS or Zephyr to perform the tests? Are you using the FRDM-RW612 board? Please also provide which version (either SDK or Zephyr) you are using, and if you're taking an example as base for your development. Additionally, the Reference Manual of RW612 (UM11865) includes a basic configuration guide for I2S peripheral in section 28.2, would you please confirm if you have followed this general steps? Re: RW612 FLEXCOMM3/I2S3 Supporting driver Hi @RomanVR , Thank you for your response. Please find the clarifications below. 1. RTOS We are using bare-metal and FreeRTOS for both test. No Zephyr is involved in these tests. All initialization and I2S configuration are done directly with the NXP SDK drivers. 2. Board We are not using the FRDM-RW612. We are using a custom Dev Board based on RW612ETA2I. The MCU is the same, but the board layout differs. The audio codec (PCM6120) is wired to FLEXCOMM3 / I2S3 on the following fixed pins: Signal GPIO Direction I2S DATA (SDOUT from PCM6120) GPIO24 Input I2S SCK (BCLK to PCM6120) GPIO25 Output I2S WS (FSYNC to PCM6120) GPIO26 Output I2C SDA (PCM6120 config) GPIO56 (FC14) Bidirectional I2C SCL (PCM6120 config) GPIO57 (FC14) Bidirectional AUX_EN (PCM6120 power) GPIO54 Output 3. SDK Version We are using SDK_2.x_RD-RW612-BGA, version 25.03.00. 4. Base Example We used rdrw612bga_i2s_dma_record_playback as the reference example. That example uses FLEXCOMM1 (TX master) + FLEXCOMM0 (RX slave) + I2S bridge, which we confirmed is working. However, our hardware constraint forces us to use a single FLEXCOMM (FC3 only) for the entire I2S link to PCM6120. PCM6120 must work in Slave mode because we dont have External clock to source for BCLK . We attempted to configure FC3 as kI2S_MasterSlaveNormalMaster to have it generate SCK/WS while receiving data. 5. UM11865 Section 28.2 – I2S Configuration Steps We have reviewed UM11865 Section 28.2 and can confirm all 6 configuration steps are followed: Step 1: Flexcomm enabled with CLOCK_EnableClock + RESET + CLOCK_AttachClk Step 2: FIFO configured (FIFOCFG=0x35, ENABLETX=1, SIZE=8) Step 3: I2S pins set via IO_MUX_SetPinMux(IO_MUX_FC3_I2S), AON MCI_IOMUX enabled Step 4: Rate configured (CFG1 MSTSLVCFG=0b11=NormalMaster, DIV=3 → BCLK=3.072MHz) Step 6: DMA enabled in FIFOCFG Despite following all steps, we observe: - No SCK/WS edges on GPIO25/GPIO26 - TX FIFO not accepting data: TXNOTFULL=1 but TXLVL stays 0 after FIFOWR writes Section 28.2 Step 4 states "For controller operation, the clock determines the I2S rate" but does not specify whether PERSEL=I2S_RECEIVE with NormalMaster is expected to drive SCK/WS onto the pads. Can you clarify: 1. Is PERSEL=I2S_RECEIVE (0b101) capable of driving SCK/WS as outputs when MSTSLVCFG=NormalMaster? 2. Why does TXLVL remain 0 after writes to FIFOWR with PERSEL=I2S_TRANSMIT? Is MAINENABLE required before FIFOWR writes are accepted? 6. Observed Issue – Our Specific Question After all configuration above, GPIO25 and GPIO26 produce zero edges. PCM6120 reports missing clocks (ASI_STS = 0xFF, DEV_STS1 = 0x80). We further ran a diagnostic: we configured FC3 as I2S TX master (instead of RX master) and found that writes to FIFOWR do not increment TXLVL — FIFOSTAT stays at 0x30 (TXNOTFULL=1, TXLVL=0) regardless of how many words we write. Relevant register state after TX master probe:   CFG1 = 0x17003C (MSTSLVCFG=3 = NormalMaster, DATALEN=24, MAINENABLE=0) DIV = 3 (divider=4, BCLK = 12.288MHz / 4 = 3.072MHz) FIFOCFG = 0x35 (ENABLETX=1, TXI2SE0=1) FIFOSTAT = 0x30 (TXNOTFULL=1, TXLVL=0 after writes) After MAINENABLE=1: STAT = 0x5 (BUSY=1, LR=1 — clock logic running internally) SCK/WS edges on GPIO25/GPIO26: 0 Our specific question to NXP: When FLEXCOMM3 I2S is configured as kI2S_MasterSlaveNormalMaster (either TX or RX), is it expected behavior on RW612 that SCK/WS are not driven onto GPIO25/GPIO26 (AON domain), even though STAT shows the peripheral is internally running? Alternatively: Is a single-FLEXCOMM topology (one FC as both clock master and RX data receiver) supported by the RW612 I2S hardware, or does RW612 always require two separate FlexComm instances (one TX master + one RX slave via I2S bridge) for this use case? Thank you. Re: RW612 FLEXCOMM3/I2S3 Supporting driver Hi @duyhung, thanks for providing additional details of your setup. Based on the reference manual (RM00278), when the I2S instance is configured in normal master mode, the SCK and WS signals are configured to be generated but not to transmit or receive data, as it is detailed in section 31.1.2 of the RM00278 in CFG1[MSTSLVCFG] register. In the I2S driver, this configuration is applied within the "I2S_TxInit();" function, which also configures the Flexcomm instance being used and the FIFO as a transmitter instance. Given the previous information, the double Flexcomm topology with shared signals (as it is done in the example you have already tested) is suggested, as it is demonstrated in a similar example shown in Figure 9 in section 3.6.2.1.1 of UM11865. Additionally, if you are taking as base the I2S with DMA playback example, would you please share the modifications you have done to the example?
View full article
Will multiple Ara240's support P2P communication? Subject says everything. Can you connect multiple Ara240's through an appropriate PCIe switch and use P2P communication to run larger models? Re: Will multiple Ara240's support P2P communication? The online resource for ARA24 is quite limited but it would be helpful with BAR2 content
View full article
S32DS 3.4 - .mex file and ConfigTools Pins do not open Hi, I'm using S32 Design Studio 3.4 with the S32K1xx SDK RTM 4.0.1 for the S32K142. I'm facing an issue where the .mex file and ConfigTools (Pins/Clocks/Peripherals) no longer open. What happens: Double-clicking the .mex file does nothing. ConfigTools → Pins also does nothing. Once, the .mex editor opened correctly and I could see the Pins view, chip package, and peripherals, but after clicking OK, it never opened again. This happens even in a new workspace   I have already tried: Creating a new workspace. Importing the project again. Updating the S32 Design Studio Platform Tools package. Selecting S32 Configuration Tools as the editor for .mex. Restarting S32DS. The project builds correctly, but the Configuration Tools editor never opens. Has anyone seen this issue before? Is this caused by an SDK installation problem, corrupted Config Tools, or a workspace issue? Any suggestions would be appreciated. Eclipse IDE Usage and Settings SDKs Re: S32DS 3.4 - .mex file and ConfigTools Pins do not open Hi @VaneB, Thank you for your reply. I installed S32K1xx SDK RTM 4.0.3 in S32 Design Studio 3.4 and created a new Hello project using the 4.0.3 SDK (not an imported project). The project builds correctly, but the .mex file still does not open in the Configuration Tools editor. When I double-click the .mex file, I can select S32 Configuration Tools as the editor, but after clicking OK, nothing happens. I also verified that the Configuration Tools plugins (Pins Tool, Clocks Tool, Peripherals Tool, Framework, etc.) are installed. Could you please advise what else I should check? Is there a known issue with the Configuration Tools editor not opening in S32DS 3.4? Thank you. Re: S32DS 3.4 - .mex file and ConfigTools Pins do not open Hi @Resham_Bhattad  Please note that S32K1xx SDK RTM 4.0.1 is not compatible with S32DS 3.4. For IDE version, the supported SDK versions are S32K1xx SDK RTM 4.0.2 and 4.0.3. Based on the error, it looks like the IDE cannot find the SDK path. This can happen if the SDK is not installed, the project was imported, or the SDK location configured in the project does not match the SDK installed on your machine. BR, VaneB Re: S32DS 3.4 - .mex file and ConfigTools Pins do not open Hi @Resham_Bhattad  If you access any of the ConfigTools tools, are you able to see and select the project you created from the drop-down list?
View full article
S32K312 Secureboot Authentication When changing to a different FBL while Secureboot is enabled, the META Data values ​​generated via the HMAC Key change. As the FBL is changed, the HSE needs to recalculate the META Data using the HMAC Key; however, because the HMAC Key is deleted due to the new FBL, recalculating the META Data becomes impossible. Consequently, a reset occurs due to a verification failure at the FBL, making it impossible to launch the application. Is there a way to re-authenticate the changed FBL using the HMAC Key, thereby allowing both the FBL and the application to run normally?  When running the HSE_SRV_ID_SMR_ENTRY_INSTALL service, HseResponse returns 0xA5AA5317. This corresponds to the following definition: #define HSE_SRV_RSP_KEY_EMPTY ((hseSrvResponse_t)0xA5AA5317UL) This indicates that the key is empty. (As I asked previously, I suspect this response appears because that region has been erased.) I have checked the smrEntry values. When I set a breakpoint at the point where SecureBootState is 0, I confirmed that smrEntry was entirely 0. When I set a breakpoint at the return point where Fota_S32k3_SecureBootProcess ends, I confirmed that the values appeared. At the time of return, the SecureBootState value was 1. I would greatly appreciate it if you could guide me on how to inject the key or otherwise resolve this issue. 1) When a breakpoint is set at if(SecureBootState == 0) / Result: smrEntry = 0 2) A breakpoint at return secureBootProcessResult, the last part of the Fota_S32k3_SecureBootProcess function Re: S32K312 Secureboot Authentication All cryptographic keys declared within the NVM and RAM key catalogs, except for the key type HSE_KEY_TYPE_SHE, can be provisioned (i.e. initialized and updated) by the host via a key import service, defined by the structure hseImportKeySrv_t. The SHE keys is provisioned by the host via services hseSheLoadKeySrv_t or hseSheLoadPlainKeySrv_t.The keys can be installed in plain or encrypted text as shown in the above figure, in the demo all keys are installed in plain text. Do you try the reference code about S32K344_Update_NVM_keys_related_test at \S32K3_HSE_DemoExamples\? # Update NVM keys. ## 1. Objective The main purpose of this example is to a import symmetric key and AES GMAC generate keys. ## 2. Procedure The steps followed to achieve this are: 1. Format Key Catalogs. 2. Declare the HMAC key info that will update initial version. 3. Declare a key container. 4. Copy the key info to the key container. 5. Copy the key data in the container. 6. *You can add any other data to the container*. 7. Import in RAM a copy of the AES provision key to sign the container using the HSE. 8. Sign the container and generate GMAC ## 3. Hardware This example requires the following hardware in order to properly execute: - S32K344-EVB or S32K344-CVB. - If using S32K344-CVB, then an external debugger is also required (PEmicro Multilink rev. C). Re: S32K312 Secureboot Authentication Hi @jeongwoo  It seems that the primary issue currently blocking further progress is that we do not know whether the HMAC key is still available. As a first step, could you please confirm whether you have performed the check I suggested previously and what the result was? “To confirm if the key is erased or not, you can use service HSE_SRV_ID_GET_KEY_INFO, structure struct hseGetKeyInfoSrv_t. Using this service, you will get information in hseKeyInfo_t, so you can check the state of key.” Once we have confirmed the state of the key, we can proceed with the next steps. If the key is missing or has been erased, we can try to install it again. Alternatively, you could also attempt to install the key directly using the same procedure that was originally used during provisioning and see whether the operation succeeds. Regards, Lukas Re: S32K312 Secureboot Authentication A key can be imported or update by HSE service HSE_SRV_ID_IMPORT_KEY. Take a look at these tables in HSE Firmware reference manual rev. 2.7: Table 47. Key provisioning usage when importing a key in an empty slot in the NVM key catalog Table 48. Key provisioning usage when updating  a key (non-empty slot) in the NVM Key Catalog This explains when a key can be imported in plain and when authentication and encryption is needed. If a key slot is empty and you have SU rights, a key can be imported in plain without authentication. If a key slot is not empty (you are updating a key) and you have SU rights, authentication is mandatory and encryption is optional. With user rights only, authentication and encryption is always mandatory regardless of fact that a slot is empty or not. S32K344_Update_NVM_keys_related_test example only shows, how to prepare and sign a key container which is needed for authenticated key import. But the key is not imported in this example. Import of a key is shown in S32K344_AES_EncryptDecrypt, for example. Used API for AES key is LoadAesKey in this project. For HMAC, there’s LoadHmacKey API. This can be used for import of HMAC key in plain without authentication or encryption.
View full article
FRDM-MX95 PRO software packages? I was wondering what OS software packages will be available for the MX95 PRO?  Will Android AAOS be available for it as a demo image?  Is there anyone we can communicate with about what will specifically be available? Re: FRDM-MX95 PRO software packages? currently, only linux 6.18.20_2.0.0 demo images for imx95 frdm pro Embedded Linux for i.MX Applications Processors | NXP Semiconductors you can download demo images from the link above, for android, I checked the board file, the latest android 16.0.0_2.0.0 is based on kernel 6.18.20_2.0.0, so should support frdm pro, but this version android hasn't verified on this board yet, only 19x19 evk and 15x15 frdm Re: FRDM-MX95 PRO software packages? Any news if we will get android automotive on the frdm-mx95 or would we have to upgrade to frdm-mx95 pro version? Re: FRDM-MX95 PRO software packages? let me confirm auto android team again, the owner is on vacation, and come back office in next week, any update I will let you know it Re: FRDM-MX95 PRO software packages? refer to the link as below https://www.nxp.com/design/design-center/software/embedded-software/i-mx-software/android-automotive-os-for-i-mx-applications-processors:ANDROID-AUTO auto android demo images are only for imx95 19x19 evk Re: FRDM-MX95 PRO software packages? Are there any plans for android or AAOS?  Seems weird that the FRDM MX95 Pro wouldn't have an AAOS version especially since the Evaluation board 19x19 has been discontinued and benched.  Is there a reason the pro being a 19x19 processor wouldn't work as the evaluation board. Re: FRDM-MX95 PRO software packages? Thanks. There seems to be a genuine lack of Android automotive support. The frdm has a lot of potential but without additional support from nxp we are left on our own. From my understanding the evk has been dropped from support from toradex and discontinued. With the frdm pro having the same hardware there should be some support. We need the BSP which would make building the images a lot easier.
View full article
新舊硬件版號差別 同樣 ringo 版本,為什麼 左邊是舊的 版號 332 可以使用,右邊新的 B222 不能使用,332/B222 區別 怎麼樣 B222可以正常使用
View full article
MIMXRT1060-EVKB - Debugger no longer reaches ResetISR/main, GDB disconnects after flash programming Hi NXP Team I'm facing a strange issue with my MIMXRT1060-EVKB that started suddenly. The board was working fine previously, but now I cannot debug any application, including the SDK examples. Environment Board: MIMXRT1060-EVKB IDE: MCUXpresso IDE 24.12.x Debug Probe: On-board LinkServer Connection: USB Problem When I start a debug session: The project builds successfully. Flash programming completes successfully. After programming, the debugger resets the target but never reaches ResetISR  or main(). The GDB session immediately terminates. Console output: Closing flash driver MIMXRT1060_SFDP_QSPI.cfx Flash Write Done Flash Program Summary: 850584 bytes in 0.06 seconds Starting execution using system reset and halt target Stopped (Was Reset) [Reset from Unknown] GDB stub (crt_emu_cm_redlink) terminating - GDB protocol problem: Pipe has been closed by GDB. What I have already tried Tested with a new SDK example (UART interrupt example) — same behavior. Placed a breakpoint at ResetISR — it is never hit. main() is never reached. Performed Mass Erase — no change. Rebooted the PC. Tried on another laptop with a fresh MCUXpresso installation — same issue. Verified the DIP switches are configured for QSPI Flash boot mode, not Serial Downloader (ISP) mode. Any suggestions would be greatly helpful. Thanks Prathyush. i.MXRT 106x Re: MIMXRT1060-EVKB - Debugger no longer reaches ResetISR/main, GDB disconnects after flash programm Hi @ShellyZhang , Thank you for your suggestion. I followed the exact sequence you recommended. I disconnected the power and debug cables, toggled the last two pins of SW4 to put the board into Serial Download Mode, reconnected the board, and performed a Mass Erase using the LinkServer GUI Flash Programmer. The mass erase completed successfully. After that, I restored the board to QSPI Boot Mode, reset the board, and started a new debug session. Unfortunately, the issue still persists. The application is programmed successfully, but the debugger does not reach ResetISR or main(). I also verified that the same behavior occurs with an unmodified SDK example project, so it does not appear to be specific to my application.   Thanks, Prathyush Re: MIMXRT1060-EVKB - Debugger no longer reaches ResetISR/main, GDB disconnects after flash programm Dear @Prathyush_27 , Please try this sequency: 1. Disconnect the power cable and the debug cable from the board, then set the board boot mode to Serial Download Mode. 2. Reconnect the power cable and the debug cable, then use MCUXpresso IDE → GUI Flash Tool / LinkServer GUI Flash Programmer → Erase Flash Memory → Mass Erase. 3. Restore the board to QSPI Boot Mode, reset the board, and then start a new debug session. Best Regards, Shelly  Re: MIMXRT1060-EVKB - Debugger no longer reaches ResetISR/main, GDB disconnects after flash programm Hi Prathyush_27, Thank you for your reply. Your feedback will help us better understand the issue and may also benefit others who encounter similar problems. Best Regards, Shelly Re: MIMXRT1060-EVKB - Debugger no longer reaches ResetISR/main, GDB disconnects after flash programm Hi @ShellyZhang , Thank you for your assistance. I was able to identify the root cause of the issue. It turned out to be the SW2 DIP switch configuration. The last two switches on SW2 had been accidentally toggled, which prevented the debugger from starting the application correctly. After restoring the last two SW2 switches to their original positions, everything worked as expected. The debugger now successfully reaches ResetISR and main(), and debugging works normally. This was a configuration issue on my board rather than a problem with the SDK or the debugger. Thank you again for your support. I hope this information is helpful to anyone who encounters a similar issue in the future. Re: MIMXRT1060-EVKB - Debugger no longer reaches ResetISR/main, GDB disconnects after flash programm Dear @Prathyush_27 , Could you please try the following two approaches? 1. Verify Flash Programming and Boot Please try using MCUXpresso Secure Provisioning Tool 26.06 to program a simple LED blink application while the board is in Serial Download Mode, and then switch the boot mode back to QSPI Boot Mode. If the LED application runs successfully after a reset, it indicates that the flash device and boot process are functioning correctly. In that case, I suspect that LinkServer GUI Flash Programmer may not have completed the flash erase operation successfully. If the LED application can boot and run after a reset, please try launching a normal debug session again to see whether the issue still occurs. 2. Run the Application from RAM Please modify the project configuration to run the application from RAM: 2.1 Enable Link application to RAM: 2.2 Under Defined Symbols, configure: XIP_EXTERNAL_FLASH=0 XIP_BOOT_HEADER_ENABLE=0 2.3 Rebuild the project. 2.4 Start a normal debug session and run the application. Please let us know the results of both tests, especially whether the LED application can boot successfully from QSPI flash and whether the RAM-based application can run under debug. Best regards, Shelly
View full article
I want to use flexio to work as a special spi, 20bit mosi output at the same time 20 chip dac need  to be controled  at the same time , I want to use flexio  to work as special spi,  to control the dac device. deltails as below: one  cs , one clk,  20 mosi,   use 20 pins,  to  output dac values to  20 dac devices at the  same time , can you give the  mcuexpross code  and project ? thanks! 回复: I want to use flexio to work as a special spi, 20bit mosi output at the same time Is  the  question two hard  lead to  there is nobody  can give  any suggestions  ? 回复: I want to use flexio to work as a special spi, 20bit mosi output at the same time 1、 cs pull low level 2、flexio transmit 20 channel mosi evrytime, every channel transmit one bit,  one transmit use one shift register, 3、transmit 8 times use all the 8 shift registers , and every channel transmit  8 bits。 4、step 2 、3 is one  dma  transmit.  use  3 times of dma to transmit 24bit  data every channel, because  the dac chipi is  24bits. 5、pull cs high。 can  this work ok? 回复: I want to use flexio to work as a special spi, 20bit mosi output at the same time is   there anybody ? Re: I want to use flexio to work as a special spi, 20bit mosi output at the same time the  chip i use is mcxn947. 回复: I want to use flexio to work as a special spi, 20bit mosi output at the same time Hi @justdomyself  For a similar implementation, I recommend checking the FlexIO QSPI application note AN14175 and the FlexIO SPI DMA examples in the MCUXpresso SDK. The AN14175 example demonstrates how to use FlexIO timers and shifters to create custom serial interfaces, which is closer to your requirement of driving 20 DAC channels simultaneously with one clock and multiple data outputs. The FlexIO SPI DMA example is also useful for understanding the basic FlexIO timer, shifter, and DMA configuration. BR Harry 回复: I want to use flexio to work as a special spi, 20bit mosi output at the same time Where is the project code for AN14175 located? Where can I download it? 回复: I want to use flexio to work as a special spi, 20bit mosi output at the same time Hi @justdomyself  Search | NXP Semiconductors Please search AN14175 in the NXP official website. And you can click the Associated File: AN14175SW to download the software. BR Harry 回复: I want to use flexio to work as a special spi, 20bit mosi output at the same time An error occurred during import: An error occurred during compilation: An error occurred during debugging: When executing BOARD_PowerMode_OD, the debug function crashes immediately with the error shown in the image above. Could you provide a newer, working project? My software version: MCUXpresso IDE v25.6 [Build 136] [2025-06-27] 回复: I want to use flexio to work as a special spi, 20bit mosi output at the same time Hi @justdomyself  You can download the SDK version corresponding to AN14175. BR Harry
View full article
Image-specific SBOM and CVE assessment support for FlexBuild LSDK-25.12 Hi NXP team, We are using LSDK-25.12_DEBIAN-13_LF-6.12.20 with FlexBuild to build a Debian-based product image for the i.MX8MP. To support our vulnerability assessment and conformity assessment under RED / EN 18031, we need to establish a repeatable process for identifying the software components and known vulnerabilities in the final shipping image. We have reviewed the FlexBuild 25.12 source tree and found that: SBOM-flexbuild.spdx.json contains only a single package entry describing the FlexBuild tool itself, rather than the contents of a built image. SCR.txt is an SDK-wide Software Content Register and does not represent the components actually installed in a specific target image. We could not identify any image-specific SBOM or CVE manifest generation mechanism in flex-builder. Based on these findings, could you please clarify the following? Does NXP currently provide an official or recommended method for generating an image-specific SBOM, such as a per-image SPDX document, from a FlexBuild Debian build? If this capability is planned, could you indicate the target release or expected availability? Does NXP currently provide or plan to provide Vigiles integration for the Debian Linux SDK / FlexBuild, equivalent to the meta-timesys workflow available for Yocto? If direct integration is not available, is manually creating and importing a CSV manifest, as described in the Vigiles FAQ, still the recommended approach for FlexBuild-based images? What are the official sources for security advisories, CVE applicability information, and security fixes for the following components included in this release? linux-imx lf-6.12.20-2.0.0 uboot-imx lf-6.12.20-2.0.0 imx-atf imx-optee-os NXP-provided firmware and binary packages, such as DDR, HDMI, VPU, and wireless firmware For example, should we rely on NXP security advisories, fixed-CVE lists in release notes, specific maintained Git branches, or another official source? What is the maintenance and security-update lifecycle for LSDK-25.12 and its associated lf-6.12.20 BSP components? In particular: For how long will security fixes be provided for this release? Which branches or repositories should be monitored for backported fixes? What upgrade cadence does NXP recommend for products requiring an ongoing vulnerability-management process? Our goal is to establish a repeatable and evidence-based SBOM and CVE assessment process for the actual shipping image. References to any official documentation, supported tools, or recommended procedures would be greatly appreciated. Thank you. Re: Image-specific SBOM and CVE assessment support for FlexBuild LSDK-25.12 Hi @Chavira , Thank you for the clarification regarding the support status of the Debian distribution. We understand that the Debian integration itself is provided as a proof of concept. However, our remaining questions concern the underlying BSP components, which as far as we can tell are the same repositories and branches consumed by the Yocto BSP releases: - linux-imx (lf-6.12.20-2.0.0) - uboot-imx (lf-6.12.20-2.0.0) - imx-atf - imx-optee-os - NXP-provided firmware binaries (DDR, HDMI, VPU, wireless) Could you please confirm, independently of which build system or root filesystem is used: 1. Are security fixes for these components delivered through the lf-* release branches, and is the fixed-CVE information published in the Yocto BSP release notes the authoritative source for CVE remediation status of these components? 2. For the lf-6.12.20 generation specifically, which subsequent lf-* releases or branches should we monitor to obtain security fixes applicable to these components? 3. What is the maintenance duration for the lf-6.12.20 BSP component generation, and what upgrade cadence does NXP recommend for products that must maintain an ongoing vulnerability-management process? We are not asking NXP to support or validate our Debian-based image; we only need to identify the official sources of security-fix information for the NXP BSP components themselves, so that we can track and apply them in our own maintenance process. Thanks Re: Image-specific SBOM and CVE assessment support for FlexBuild LSDK-25.12 Hi  @Leo_dev, Thank you for contacting NXP Support. Unfortunately, Debian is considered by NXP to be a proof of concept distribution and therefore does not receive the same level of support, validation, and long term maintenance as our Yocto based BSP releases. In fact, during boot, Debian displays a disclaimer indicating that the software is provided without any guarantee of functionality or support. As a result, issues encountered on Debian may not receive the same level of investigation or validation as those reproduced on a Yocto based image. For production development and fully supported use cases, we recommend using the Yocto BSP provided by NXP. All of our publicly available source code is hosted on GitHub and can be accessed through the following organization: https://github.com/nxp-imx Best regards, Chavira Re: Image-specific SBOM and CVE assessment support for FlexBuild LSDK-25.12 Hi @Leo_dev, 1. Yes. Security fixes for NXP BSP components are typically delivered through the official lf- release branches. The i.MX Linux BSP release notes (RN00210) and associated manifests/change logs are the primary NXP references for tracking integrated fixes and CVE remediation status 2. For the LF6.12.20 generation, monitor subsequent BSP releases such as LF6.12.34_2.1.0, LF6.12.49_2.2.0, LF6.18.2_1.0.0, and newer releases, as security and maintenance fixes are carried forward into these branches. 3. For products requiring ongoing vulnerability management, NXP's recommended practice is to regularly track and evaluate newer BSP maintenance and quarterly releases to obtain security updates and bug fixes
View full article
S32K388 TCP/IP stack 5.0.0 not working Hi @PavelL, I was able to run the example TCP/IP stack example project previously with the following configuration: • S32KDS version 3.6.5 • RTD (Real-Time Drivers) version 7.0.0 • TCP/IP Stack version 4.0.0 However, after upgrading to the following versions and did the same setup procedure, it is not working: • S32KDS version 3.6.8 • RTD (Real-Time Drivers) version 7.0.1 • TCP/IP Stack version 5.0.0 I have attached my project. Thanks for the help again. Re: S32K388 TCP/IP stack 5.0.0 not working Hello @James_Zhang_SE , I need time for investigation. I'll do my best to reply within this week. Thank you for your understanding. Best regards, Pavel Re: S32K388 TCP/IP stack 5.0.0 not working Hello @James_Zhang_SE , I apologize for delayed response caused by my workload. The root cause is EthIf_Cfg.c , as we've already discussed in this thread S32K388 tcpip stack 4.0.0 missing lwip folder while compiling The example is working now on my S32K388EVB-Q289. Anyway, I did lots of changes in your project but the most critical is the EthIf_Cfg file. All modified files can be found in the attached zip. You may check the changes by yourself. Please notice that provided code is without any warranty. Once you replace files by the patch, please do not forget to do Update Code. Best regards, Pavel Re: S32K388 TCP/IP stack 5.0.0 not working Hi Pavel, Thank you so much for your help! After applying the same steps as before, I was able to ping and test the TCP loopback. I have a few quick questions: For the Ethif Config fix and RTD workarounds, will they be added in future releases of the driver and example project? Since I'm not too familiar with this stack. When something is not working, do you have a suggested systematic way to debug? Re: S32K388 TCP/IP stack 5.0.0 not working Hello @James_Zhang_SE , Thank you for sharing your current status.   If my previous post helped to solve the issue, please mark it as a solution, as this may help other users facing a similar problem.   Regarding point 1:   I have reported the EthIf_Cfg issue to the responsible software team. The release date of the fix is not known yet. There is still an internal discussion about where the RTD workaround should be implemented, whether in the MAC driver or in the clock configuration area. For now, we need to accept the current situation and apply the workaround manually.   Regarding point 2:   My usual debug flow is to check the pin configuration, clock configuration, interrupt configuration, FIFO sizes and the required RTD workaround code. The gPTP examples are also a very good reference, because they provide functional Ethernet-related configurations that can be used for comparison. Best regards, Pavel
View full article
S32K344 AB-Swap auto-boot failure after HSE_ActivatePassiveBlock; firmware boots only via J-Link Sta Platform: S32K344 with AB-Swap scheme. Separate firmware images reside in Active and Passive blocks. Observation: After executing HSE_ActivatePassiveBlock() to swap active/passive partitions, a full power cycle does not trigger automatic firmware startup. Firmware executes successfully only when J-Link is attached and Start Application is triggered from debugger. Could anyone explain the root cause and provide recommended fixes? Re: S32K344 AB-Swap auto-boot failure after HSE_ActivatePassiveBlock; firmware boots only via J-Link Hi @HQZ  Are you sure there is a valid image in the passive partition? What do you observe if you attach a debugger to the running target without resetting it after power-up? Did the device enter JTAG recovery mode? Or you can simply reset the device by your debugger and then check if it reached the entry point of your application.  If the device is stuck in an endless loop at address 0x2040012C, it indicates that it has entered JTAG recovery mode. This could also point to an issue with the IVT configuration or IVT integrity. Also, is the image in the passive partition linked to run from the active partition address space, i.e. starting at 0x00400000? Finally, are you using Secure Boot? Regards, Lukas Re: S32K344 AB-Swap auto-boot failure after HSE_ActivatePassiveBlock; firmware boots only via J-Link Hi @HQZ  “while Partition B firmware is linked starting at 0x600000” – this is the problem. Both images must be linked for active partition addresses – 0x400000. The applications are always running from active partition, not from passive partition. Solution – use the same linker file for both projects. It works with your debugger because debuggers set the program counter “manually” to entry point address which is found in elf file. Regards, Lukas Re: S32K344 AB-Swap auto-boot failure after HSE_ActivatePassiveBlock; firmware boots only via J-Link Hello@lukaszadrapa  Platform: S32K344, AB-Swap architecture. Independent firmware images are stored in Active Block and Passive Block separately. HSE Secure Boot is disabled. Problem Description: After calling HSE_ActivatePassiveBlock() to complete the Active/Passive partition switch, the device cannot automatically boot the target firmware after power cycle and reset. However, if the J-Link debugger is connected to the chip and "Start Application" is clicked within the debugger software, the swapped firmware runs normally. Additional background: Firmware resides in both Partition A and Partition B. The only difference between the two images is the LED blinking frequency. Partition A firmware is linked starting at 0x400000, while Partition B firmware is linked starting at 0x600000. After invoking HSE_ActivatePassiveBlock() and reset, I dumped flash contents with J-Link. The contents of Partition A and Partition B have been physically swapped, confirming that HSE_ActivatePassiveBlock() takes effect. Questions: 1. What is the root cause of this behavior? Why does cold power-on boot behave differently from debugger-triggered "Start Application"? 2. What feasible solutions can resolve the auto-boot failure after AB partition swap? Thanks for your support. Re: S32K344 AB-Swap auto-boot failure after HSE_ActivatePassiveBlock; firmware boots only via J-Link Hello@lukaszadrapa  I have tried the AB‑partition swap according to previous suggestions, but the issue still persists. The HSE firmware version used is s32k344_hse_fw_1.5.0_2.40. Test setup for validating AB‑swap: Single linker script with application‑based self‑update. The application is responsible for programming the new firmware image into the passive partition. Linker script: Only one linker script is used, and the firmware start address is always set to 0x00400000. Workflow: 1. The application running in Partition A (logical address 0x00400000) receives new firmware over CAN. The only difference between Partition A and Partition B firmware is the LED‑blinking frequency. 2. The application programs the new firmware directly into the physical address of the passive partition (0x00600000). 3. After programming completes, the HSE_ActivatePassiveBlock() service is called. 4. The chip is then reset. Observation: The firmware fails to run after reset. However, when J‑Link is connected and "Start Application" is triggered from the debugger, the firmware from Partition B executes correctly. What other root causes can lead to unsuccessful partition swap, and what are the corresponding solutions? Regards
View full article
IMX8M Plus GPU DRAM contention We are running Yocto Linux on an IMX8M Plus What we have noticed is that during any GPU activity, we get huge latency spikes for memory access from the CPU (1-3ms spikes). This is a huge issue, as we are using XDP for networking. We have tried tuning IMX8MP_ICM_A53, IMX8MP_ICM_GPU3D and IMX8MP_ICM_GPU2D, setting them to 7, 2, 2 for QoS control. This made the latency spikes less frequent, but they are still there. The only option we found was doing absolutely no GPU activity or removing the GPU from the device tree, however this is not acceptable for our use-case. Are there some other setting that could be tuned to alleviate this behavior? We cannot have the GPU locking the DRAM for more than a 50-100 μs at most Graphics & Display Linux Re: IMX8M Plus GPU DRAM contention Hi @richardlovgren, Thank you for contacting NXP Support! Could you please tell me which BSP version you are using? Does this issue reproduce on an EVK as well, or is it only occurring on your custom hardware? Could you also provide the log files, your device tree, and any other relevant information so that I can investigate and diagnose the issue on my side? Additionally, please share the exact steps to reproduce the problem, so I can try to replicate it in my setup. Best regards, Chavira
View full article
EZH-V use case for IMXRT700 Hi team NXP! From the spec of IMXRT700 it was said to be architected in the 3 domain of media, compute and sense domain, which each of the cores on chip would require their own separate image to run. But it seems that there are only very few documented usage of the EZH-V core. I have read the application notes AN14614, AN14618 and AN14654, but there are still very few information regarding this core and it roles in graphical processing for RT700. It was said that it is used to implement the smartDMA engine, but in other MCX family MCU there are no mentioning of the existence of this core and the smartDMA can be directly used by the Arm CM33 core via the mcuxpresso sdk provided APIs. So now I am extremely confused, can I still directly use the smartDMA on iMXRT700 directly or must I build the image for the EZH-V via LLVM as per AN14614 instruction? This seems quite counterintuitive though having to resort to RPMsg for IPC communication as supposed to be directly driven by the Cpu0. On top of this, I am not aware of any actual demo or use case that has been provided by NXP that explicitly utilized this EZH-V core. I have also review the some of the source headers available, and only some very intuitive basic operations have been provided. May I know what is the usage of the EZH-V? Re: EZH-V use case for IMXRT700 okay quick update, after taking a look of the smartDMA driver in the mainline Zephyr now I understand the situation. The smartDMA has always been/planned as a standalone subsystem with its own core that could have the potential to run firmware on its own, but never have been actually presented as a fully standalone RISC-V core. In the current existing example, the smartDMA has never really touched the custom firmware installation path and only used as a slightly special DMA IP. So now the question should pivot to if I could still use the smartDMA in the old fashion; directly invoked via the CM33 instead of doing the complex IPC setup, as of time of writing, the smartDMA IP is yet to be exposed as a supported IP of the official maintained mimxrt700_evk. Re: EZH-V use case for IMXRT700 Hi @mayliu1 , Thanks for the quick reply, so you mean the smartDMA is no longer coupled to the CM33 core and therefore must be used via the EZH-V core? In NXP's other MCU family like MCX the smartDMA is coupled to the CM33 and can be directly invoked via APIs, there are application notes documenting such use cases AN14172, AN14916, and they do not involve building the standalone image for the RISC-V core.  So what is the current architecture on the i.MXRT700? All documents about EZH-V are very ambiguous and I am not aware of any existing demo or guides that have thoroughly covered the usage of EZH-V.  Has NXP revised the architecture of smartDMA so it is no longer part of the core CM33 system and grouped to the RISC-V companion core instead? Can I still invoke the smartDMA directly via the CM33? Re: EZH-V use case for IMXRT700 Hi @TomC818 , Thank you so much for your interest in our products and for using our community. According to AN14614 and the i.MX RT700 Reference Manual, my understanding is that the SmartDMA functionality on the i.MX RT700 is implemented through the EZH-V RISC-V core rather than as a conventional DMA peripheral such as eDMA. In general, eDMA is still the preferred solution for standard memory transfer operations and can be configured directly by the CM33 core. However, SmartDMA-related processing, such as certain graphics/data post-processing or data format conversion tasks, is typically implemented by firmware running on the EZH-V core. Based on AN14614, CPU0 is responsible for loading and booting the EZH-V firmware, after which the actual processing is performed by EZH-V. From this perspective, EZH-V behaves more like a programmable coprocessor than a traditional DMA engine. Therefore, SmartDMA on RT700 is better viewed as a programmable processing engine running on the EZH-V core, rather than a traditional DMA peripheral directly driven by CM33 alone. Wish it helps you Best Regards May Re: EZH-V use case for IMXRT700 hey umm... if NXP didn't actually prepare or have any planned support for "With the assistance of the EZH-V, the Cortex-M33 cores can be freed to perform other tasks. While the EZH-V is executing the assigned task, the CM33 cores can execute other tasks in parallel." as per the reference manual described, I think I will be pursuiting a different option from ST or Infineon, considering the fact that RT700 documentations and examples are still extremely unpolished and all over the place. Support for most of the marketted unqiue features of this MCU are very sparse and few between. With such a the complex heterogeneous architecture, such little examples and guides are just abyssal. Re: EZH-V use case for IMXRT700 On i.MX RT700, SmartDMA is not exposed in the same way as a conventional standalone DMA peripheral directly controlled by the CM33. The SmartDMA-style capability is provided through the EZH-V engine, so the typical usage model is for the CM33 to load and start the EZH-V firmware, then coordinate with it as needed.
View full article
S32K358 eMIOS ISR stuck at 85°C Dear NXP Support Team, we are facing an issue on S32K358 during temperature tests at around 85°C.   In our application we use 6 eMIOS channels, each one configured to generate interrupts on both PWM edges with a frequency of 200Hz.   At 85°C, the MCU sometimes gets stuck inside one eMIOS ISR. The ISR does not exit because the code checks the interrupt flag by reading the eMIOS registers, but the flag is 0 (file Emios_Mcl_Ip_Irq.c 😞   if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].S) & (uint32)eMIOS_S_FLAG_MASK))    After debugging, we noticed that when the issue occurs, the variable containing the eMIOS base address is NULL (Emios_Ip_paxBase). When the application works correctly, the same pointer is valid and the eMIOS registers are read properly. It seems that, in some conditions, the reference to the eMIOS peripheral is corrupted or cleared during ISR execution.   Do you have any indication about possible known issues or root causes, such as stack overflow, memory corruption, concurrent accesses, ISR handling, or temperature-related behavior?   Best regards, Simon Re: S32K358 eMIOS ISR stuck at 85°C Hi vane, I'm currently using RTD 7.0.0 Re: S32K358 eMIOS ISR stuck at 85°C Hi @simon98  Which RTD version are you working with? Any additional information would be helpful. Also, in RTD versions prior to 6.0.0, there was a known issue related to the incorrect memory mapping of static variables within function scope (ARTD-159985). This issue describes a problem where the variable Emios_Ip_paxBase, defined in both Emios_Mcl_Ip.c and Emios_Mcl_Ip_Irq.c, is assigned inconsistent initialization characteristics. Further details are provided in the Software Release Notes. BR, VaneB Re: S32K358 eMIOS ISR stuck at 85°C Hi @simon98  Could you please provide a simple application that reproduces the observed behavior? Also, could you confirm whether you are working with a custom board or an evaluation board? Additionally, could you share how the testing is being performed to confirm that the issue occurs at 85 °C? Re: S32K358 eMIOS ISR stuck at 85°C Hi @VaneB , Currently i'm working with a custom board with S32K358 where i use these eMIOS_1 channels to generate PWM of 200 Hz: ch3, ch9,  ch11, ch12, ch13, ch19. Code is generated using SImulink  Putting my custom board into a climatic cell at 85°C i've observed the stucking behaviour after some time. While i was debugging with S32DS (3.6.7) I've found out that it stuck into the ISR(EMIOS1_1_IRQ) so i've put into it some custom counter near entry/exit function, and also into Emios_Pwm_IrqHandler and Emios_Pwm_Ip_IrqHandler functions, in order to detect what parts of the code are executed.  After some tests i've found out that, when it stucks, inside static void Emios_Pwm_IrqHandler(const uint8 Instance, const uint8 Channel) {     /* Check that an event occurred on Emios channel */     if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].S) & (uint32)eMIOS_S_FLAG_MASK))     {         /* Check that an event occurred on EMIOS channel */         if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))))         {             Emios_Pwm_Ip_IrqHandler(Instance, Channel);         }         else         {             /* Do nothing - in case of spurious interrupts, return immediately */         }     } }   the if condition: if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].S) & (uint32)eMIOS_S_FLAG_MASK))   is always 0 because, for some reason, Emios_Ip_paxBase[Instance] points to 0. This means that nobody is clearing the interrupt flag so it enters in a loop where it cannot escape.   here's the code i've used to detect this probelm: static void Emios_Pwm_IrqHandler(const uint8 Instance, const uint8 Channel) {     // uint32_t s;     // uint32_t c;     // uint32_t s_flag;     // uint32_t s_ovr;     dbg_pwm_last_instance = Instance;     dbg_pwm_last_channel = Channel;     dbg_pwm_last_base_addr = (uint32_t)Emios_Ip_paxBase[Instance];     dbg_pwm_last_c_addr = (uint32_t)&Emios_Ip_paxBase[Instance]->CH.UC[Channel].C;     dbg_pwm_last_s_addr = (uint32_t)&Emios_Ip_paxBase[Instance]->CH.UC[Channel].S;         dbg_emiosipirq_static_state1++;     /* if (Instance == 1)     {         switch (Channel)         {             case 16:                 dbg_emiosipirq_static_cnt_ch16++;                 break;             case 17:                 dbg_emiosipirq_static_cnt_ch17++;                 break;             case 18:                 dbg_emiosipirq_static_cnt_ch18++;                 break;             case 19:                 dbg_emiosipirq_static_cnt_ch19++;                 break;             default:                 dbg_emiosipirq_static_cnt_oth1++;                 break;         }     }     else     {         dbg_emiosipirq_static_cnt_oth2++;     } */     /* Lettura reale dei registri vista dal codice */    /*  s = Emios_Ip_paxBase[Instance]->CH.UC[Channel].S;     c = Emios_Ip_paxBase[Instance]->CH.UC[Channel].C;     s_flag = s & (uint32)eMIOS_S_FLAG_MASK;     s_ovr  = s & (uint32)eMIOS_S_OVR_MASK;     dbg_pwm_last_s = s;     dbg_pwm_last_c = c;     dbg_pwm_flag_mask = (uint32)eMIOS_S_FLAG_MASK;     dbg_pwm_ovr_mask = (uint32)eMIOS_S_OVR_MASK;     dbg_pwm_last_s_and_flag = s_flag;     dbg_pwm_last_s_and_ovr = s_ovr;     if (s_flag != 0U)     {         dbg_pwm_s_flag_yes++;     }     else     {         dbg_pwm_s_flag_no++;     }     if (s_ovr != 0U)     {         dbg_pwm_s_ovr_yes++;     }     else     {         dbg_pwm_s_ovr_no++;     }     if ((s_flag == 0U) && (s_ovr != 0U))     {         dbg_pwm_flag0_ovr1_count++;     }     else if ((s_flag != 0U) && (s_ovr != 0U))     {         dbg_pwm_flag1_ovr1_count++;     }     else if ((s_flag != 0U) && (s_ovr == 0U))     {         dbg_pwm_flag1_ovr0_count++;     }     else     {         dbg_pwm_flag0_ovr0_count++;     } */     /* Check that an event occurred on EMIOS channel */     if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].S) & (uint32)eMIOS_S_FLAG_MASK))     {         dbg_emiosipirq_static_state2++;         /* Check that an event occurred on EMIOS channel */         if (0U != ((Emios_Ip_paxBase[Instance]->CH.UC[Channel].C) & ((uint32)(eMIOS_C_DMA_MASK | eMIOS_C_FEN_MASK))))         {             dbg_emiosipirq_static_state3++;             Emios_Pwm_Ip_IrqHandler(Instance, Channel);         }         else         {             dbg_emiosipirq_static_state4++;             /* Do nothing - in case of spurious interrupts, return immediately */         }     }     else     {         dbg_emiosipirq_static_state5++;         //Emios_Pwm_Ip_IrqHandler(Instance, Channel);         //Emios_Pwm_Ip_IrqHandler(1, 19);     } } These are the global vars in which i've stored the addresses which Emios_Ip_paxBase should point to: dbg_pwm_last_base_addr = (uint32_t)Emios_Ip_paxBase[Instance]; dbg_pwm_last_c_addr = (uint32_t)&Emios_Ip_paxBase[Instance]->CH.UC[Channel].C; dbg_pwm_last_s_addr = (uint32_t)&Emios_Ip_paxBase[Instance]->CH.UC[Channel].S; I've put also some custom code to read NVIC registers run time: attached you can find the file with Thread, general registers, NVIC registers and variables expressions, EMIOS registers, for 6 tests i made. Also i will provide you the S32DS project i used to test this behaviour in a private message. I hope all these information could be usefull. I remain at your disposal for any further information. BR, SImon Re: S32K358 eMIOS ISR stuck at 85°C Hi @simon98  Thank you very much for providing this information. Since the code appears to be getting stuck in EMIOS1_1_IRQ, which corresponds to eMIOS 1 Channel 19 based on your configuration, let’s try to narrow the analysis to this specific part. To simplify the debugging and rule out any interference from other modules, please create a minimal test project that only includes this eMIOS configuration. This will help us isolate the behavior and better understand the root cause. For guidance, you can review the examples provided in the thread S32M27x/S32K3 – eMIOS Usage. Does the same behavior still occur? Also, if you have an evaluation board, it would be great if you could try the same code there. Re: S32K358 eMIOS ISR stuck at 85°C Hi vane, I'll try this week to give you a simple project that replicate the behaviour Re: S32K358 eMIOS ISR stuck at 85°C Hi @VaneB , I tested the issue on my custom board using a simplified configuration that only includes the six eMIOS1 channels. Unfortunately, in this setup I am not able to reproduce the error. The application runs correctly and does not get stuck in EMIOS_1_IRQ. At the moment, I am looking into whether it is feasible to load the complete project developed for our custom board onto the EVB. Before proceeding, I would also like to understand if the hardware differences between the custom board and the EVB could potentially lead to any unexpected behavior or even damage to the EVB. BR, Simon Re: S32K358 eMIOS ISR stuck at 85°C Hi @simon98  Our evaluation boards are designed mainly for use at room temperature and have not been tested or qualified for very low or very high temperatures. You may still use the evaluation boards outside the room-temperature range, but we cannot guarantee their performance under those conditions. Re: S32K358 eMIOS ISR stuck at 85°C Hi @VaneB , After several attempts, I managed to create an EVB project that reproduces the application running on my custom board as closely as possible. In particular, I configured all the pins in the same way as in my custom project. I then tested this project on my custom board under 85°C conditions, and the eMIOS ISR issue still occurred: the application continued to get stuck. After that, I tested exactly the same project on the EVB under the same temperature conditions and over (90°C), but I was not able to reproduce the issue—the EVB continued to operate correctly without getting stuck. At this point, what would you recommend as the next steps to identify the root cause of the problem and find a possible solution? Please let me know if you need any additional information, measurements, or debugging data from my side. I have attached a ZIP file containing the complete EVB project and the pictures of the K358 on my custom board and on the EVB. Thank you for your support. BR Simone Re: S32K358 eMIOS ISR stuck at 85°C Hi @simon98  As the issue is observed on your custom board but not on the EVB, it would be worthwhile to investigate whether the root cause could be hardware-related. I recommend comparing your hardware design against the EVB schematic and reviewing the S32K3 Hardware Design Guideline to verify that all relevant recommendations have been properly implemented. Re: S32K358 eMIOS ISR stuck at 85°C Hi @VaneB,   the HW design has been reviewed on our side and no evident hardware issue has been found. Also, the board is not directly comparable with the NXP EVB due to different hardware design and operating conditions.   If a customer observes temperature-related issues on a custom board, how could it be possible to obtain one-to-one support from NXP?   BR, Simon Re: S32K358 eMIOS ISR stuck at 85°C Hi @VaneB  I would like to gently follow up on this topic, as we are still investigating the issue on our side and would appreciate your feedback. In particular, if the root cause were related to RAM corruption (for example, an out-of-bounds write or stack overwrite), which registers or diagnostic information would you recommend checking on the S32K358? Are there any specific fault status registers, ECC/error reporting registers, MPU-related registers, stack monitoring features, or other debug registers that could help identify whether memory corruption has occurred before the eMIOS ISR gets stuck? Any guidance on the most useful registers to inspect during debugging would be greatly appreciated. Thank you for your support. Best regards, Simon Re: S32K358 eMIOS ISR stuck at 85°C Hi @simon98  Since this appears to be a hardware-related issue specific to your board and we can not reproduce it, it is difficult to accurately diagnose the root cause through this support channel. We recommend contacting your distributor or local NXP representative for further assistance,
View full article