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Multicore boot on S32G3 Hello, I would like to boot both M7 and A53.  What are the required packages for this? Is there a documentation I can follow? Regards, Dhafer Re: Multicore boot on S32G3 Hello, @wael_b  Thanks for your clarification. 1. AN13750 is originally released several years ago, which is targeted with S32G2 and specified software packages version. 2. With the specified software version and RDB2, it could be also be regarded as a hands-on guide, however, for S32G3(RDB3 for example), it may not be directly followed since the SW/HW differences. But the operation method/booting steps are the same for S32G3, you may need reference the AN13750 and made some changes to make it compatible to the S32G3 related software packages used. 3. From my experience, I suggest directly referencing the ways/steps provided by AN13750 on your S32G3 case, and try using the following software packages: the Bootloader from GoldVIP1.12, with SW32G_RTD_4.4_4.0.2_HF03,  IPCF4.10, BSP41/42  to have another try. BR Chenyin Re: Multicore boot on S32G3 Hello @chenyin_h , We are working with S32DS 3.5 on S32G399! my application on M7 was made using the SW32G_RTD_4.4_4.0.2_P10_D2405! I followed that pdf and I downloaded SW32G_RTD_4.4_3.0.2_HF01_D2204.exe and installed it and added the updatesite zip to s32ds. I added the plugins from SW32G_RTD_4.4_3.0.2_HF01 and added it to EB tresos plugins! I downloaded and installed Platform_Software_Integration_S32G3_2023_02.exe but when i imported the bootloader project in tresos, when loading the configuration I got plugin not installed error "*_TS_T40D11M40I0R0". If i uninstall Platform_Software_Integration_S32G3_2023_02 and install Platform_Software_Integration_S32G3_2022_12.exe! i got the same errors on modules but with different reference "*_TS_T40D11M30I4R0". the plugins i have in EB Tresos are referenced "*_TS_T40D11M30I2R0" and "*_TS_T40D11M40I2R0" what do you suggest in this case? Many thanks! Re: Multicore boot on S32G3 Hello, @dhafer_benchikha  Thanks for your post. 1. For booting A53 cores, Linux BSP is provisioned by NXP. 2. For M7 usage, the RTD(and also some other related software packages including PFE driver) is provided by NXP. For simultaneously booting the system with both A53 and M7 core brought up. I suggest directly following the way introduced from AN13750 BR Chenyin Re: Multicore boot on S32G3 Hello @chenyin_h, Thank you for your response! I tried with SW32G_RTD_4.4_4.0.2_HF03 and GoldVIP1.13, GoldVIP1.14 and GoldVIP1.15 because I couldn't find GoldVIP1.12 but still facing the same issues in EB Tresos as shown in the screenshots. Also, IPCF4.10 doesn't exist, so I have the IPCF4.11.
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PN7462AU マニュアル RF 送信電力制御(ランタイムコマンド使用) 私はPN7462AUに取り組んでおり、受信したUART/CLIコマンドに基づいて動的に変更可能な3つの設定可能な電力レベル(LOW / MEDIUM / HIGH)を備えた手動RF送信機電力制御を実装する必要があります。 現在、DPCは送信電力を自動的に処理しますが、私の要件はDPCの動作をバイパス/修正し、実行時に送信電力レベルを手動で切り替えることです。 知りたいのは以下の点です。 PN7462AUで送信電力を手動で制御するには、どのRFレジスタを使用するのが推奨されますか? 実行時に送信電力を切り替えるためのAPIは既に存在しますか? よろしくお願いいたします。 NFCリーダー・ライブラリ
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在 S32G3 上启动多核 你好 我想同时启动 M7 和 A53。 这需要什么代码包/软件包? 是否有文件可供参考? 此致, Dhafer Re: Multicore boot on S32G3 你好,@wael_b 谢谢您的澄清。 1。AN13750 最初是在几年前发布的,目标版本是 S32G2 和指定的软件包版本。 2.在指定软件版本和 RDB2 的情况下,它也可被视为上机指南,但对于 S32G3(以 RDB3 为例),由于 SW/HW 不同,可能无法直接照搬。但是 S32G3 的操作方法/启动步骤相同,您可能需要参考 AN13750 并进行一些更改以使其与所使用的 S32G3 相关软件包兼容。 3.根据我的经验,我建议直接参考 AN13750 在你的 S32G3 机壳上提供的方法/步骤,然后尝试使用以下软件包:来自 Goldvip1.12 的 Bootloader,用SW32G_RTD_4.4_4.0.2_HF03、IPCF4.10、BSP41/42 再试一次。 BR 切宁 Re: Multicore boot on S32G3 你好@chenyin_h、 我们在S32G399 上使用的是S32DS 3.5!我在 M7 上的应用程序使用的是SW32G_RTD_4.4_4.0.2_P10_D2405! 我按照 pdf 上的说明下载了SW32G_RTD_4.4_3.0.2_HF01_D2204.exe,并安装了它,还在 s32ds 中添加了 updatesite zip。 我添加了SW32G_RTD_4.4_3.0.2_HF01中的插件,并将其添加到 EB tresos 插件中! 我下载并安装了Platform_Software_Integration_S32G3_2023_02.exe,但在 tresos 中导入引导加载器项目时,加载配置时出现插件未安装错误"*_TS_T40D11M40I0R0" 。 如果我卸载 Platform_Software_Integration_S32G3_2023_02 然后安装 Platform_Software_Integration_S32G3_2022_12.exe! 我在模块上遇到了同样的错误但参考文献不同 " *_TS_T 40D11M 30I4R0 "。 我在 EB Tresos 中的插件被引用了 " *_TS_T40D11M 30I2R0 " 和 " *_TS_T40D11M 40I2R0 " 在这种情况下,您有何建议? 非常感谢! Re: Multicore boot on S32G3 你好,@dhafer_benchikha 谢谢您的帖子。 1.为了启动 A53 内核,Linux BSP 由恩智浦配置。 2。对于M7的使用,RTD(以及其他一些相关的软件包,包括PFE驱动程序)由恩智浦提供。 用于在同时启动 A53 和 M7 内核的情况下启动系统。 我建议直接采用 AN13750中介绍的方法 BR 切宁 Re: Multicore boot on S32G3 你好,@chenyin_h、 谢谢您的答复! 我试用了 SW32G_RTD_4.4_4.0.2_HF03 和GoldVIP1.13、因为我找不到GoldVIP1.12,所以我选择了 GoldVIP1.14和GoldVIP1.15,但在 EB Tresos 中仍然遇到截图所示的同样问题。 另外,IPCF4.10 不存在,所以我有 IPCF4.11。
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QorIQ Tシリーズプラットフォームにおけるパケットプロセッシングパフォーマンスの最適化はどのように行っていますか? QorIQ Tシリーズプラットフォームにおいて、ネットワークトラフィックが増加する状況下でのパケット処理性能の最適化に取り組んだ経験のある方はいますか? 現在、Tシリーズをベースとした連続パケット転送システムのテストを実施していますが、トラフィックの急増が持続的になると、CPU使用率が急速に上昇することに気づきました。プラットフォーム自体は安定しているものの、負荷がかかるとコア間のレイテンシの一貫性にばらつきが生じ始める。 私は特に、他の人がどのように対処しているかを知りたいと思っています。 割り込み配信 キューバランシング マルチコアワークロードチューニング メモリ/キャッシュの最適化 高スループット時のレイテンシ低減 実際の導入事例から得られた、実用的なチューニング方法やパフォーマンスに関する知見をぜひお聞かせください。 Re: How Are You Optimizing Packet Processing Performance on QorIQ T-Series Platforms? こんにちは、 はい、QorIQ Tシリーズ/DPAA1 システムでご指摘いただいたようなチューニングに関するドキュメント化されたガイダンスが LA1224-RDB-BSPUG に記載されており、持続的なバースト時に見られる動作と密接に一致しています。負荷が増加するにつれて、重要なトレードオフはスループットとコアごとのレイテンシの一貫性になります。入手したドキュメントによると、主な制御要素として、割り込みの調整、FQ/チャネルの分配ポリシー、デキュー/QMIの調整、キャッシュのスタッシング/CPCの使用、およびオーダー処理モードの選択の5つが挙げられます。 よろしくお願いします。
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WDOG cannot use 8-bit sequence refresh I am unable to use 4 8-bit writes to refresh the watchdog of S32K144. Both 16 bit and 32-bit are acceptable, but 8-bit is not. I tried the 8-bit writing method in the picture, but it all failedThe original manual is as follows: The refresh write sequence can be • either two 16-bit writes ( 0xA602, 0xB480) or four 8-bit writes (0xA6, 0x02, 0xB4, 0x80) if WDOG_CS[CMD32EN] is 0; • one 32-bit write (0xB480_A602) if WDOG_CS[CMD32EN] is 1. to the CNT register. Both methods must occur before the WDG timeout; otherwise, the watchdog resets the MCU. Re: WDOG cannot use 8-bit sequence refresh Before starting the refresh sequence, disable the global interrupts. Otherwise, an interrupt could effectively invalidate the refresh sequence, if the interrupt occurs before the refresh writes finish. After the sequence finishes, restore the global interrupt control state.  FYI for interrupt checking Re: WDOG cannot use 8-bit sequence refresh I confirm that the switch was interrupted before and after feeding the dog. In the same scenario, only changing the feeding sequence and using the 16 bit feeding method succeeded, but the 8-bit feeding method failed, and adjusting the order of the 8-bit feeding sequence did not work.
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MIMXRT1170 EVKを使用したeMMCの実装 こんにちは。 私はMIMXRT1170 EVKボードを使用しています。SDカードを使った動作する実装が既にあります。今後はSDカードの代わりにeMMCに移行しようと考えています。実装手順を探しています。eMMCをEVKボードに接続できますか?はいの場合、どのピンに接続すればよいですか? eMMCのサンプルが見つからなかったので、その方法を教えてください。 アドバイスや、動作するSDKのサンプルコードなどがあれば、大変ありがたいです。 コアとメモリ
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RW61x 用の BSDL ファイル NXPはRW61x用のJTAG境界スキャンに関するBSDLファイルを公開していますか?見つけられないようです。 製品: WiFi RW6XX Re: BSDL files for RW61x こんにちは、 あなたの調子が良いといいのですが。RTOSまたはZephyrを使用していますか? RTOSの場合、SDKのバージョンは? Zephyrの場合、どのリポジトリを使用しますか? また、モジュールを使用しているかどうかを明確にしていただけますか? よろしくお願いいたします。 リカルド Re: BSDL files for RW61x OSが境界スキャンファイルと何らかの関係を持つ理由がよく分かりません。 私はZephyr 4.4.0を使用しています。 このモジュールはu-blox製ですが、RW610が搭載されています。 Re: BSDL files for RW61x こんにちは、 お使いのチップパッケージの種類を教えていただけますか?BGA/QFNかCSPか? よろしくお願いいたします。 リカルド Re: BSDL files for RW61x 私たちはBGAを使用しています。 Re: BSDL files for RW61x こんにちは。私もrw61xシリーズチップ用のBSDLファイルを探しています。 これらのファイルをダウンロードするための正しい方法を教えていただけますか? ありがとうございます アレックス Re: BSDL files for RW61x NXPの担当者の方、この質問に答えていただけませんか? RW61x用のBSDLファイルはありますか?ある場合、どこからダウンロードできますか? ありがとうございます アレックス・ティッツワース
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S32K324 当 HSE_FW 存在时,PRTN0_CORE0_STAT 中的 WFI 位未设置 我们在 S32K324 MCU 中遇到一个问题,即当 HSE_FW 存在时,PRTN0_CORE0_STAT 中的 WFI 位未设置。 在没有 HSE_FW 的 MCU 上,WFI 设置正确,应用程序运行正常。 安装 HSE_FW 时需要做什么吗? 谢谢! 阿尼尔
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eMMC implementation with MIMXRT1170 EVK Hello. I am using MIMXRT1170 EVK board. I have an working implementation with SD card. Now I am planning to shift to eMMC instead of SD card. I am looking for the implementation steps. Can I interface eMMC with EVK board? If yes then to which pins I should connect it? And I didn't find any eMMC examples so give a approach for it.  Any advice or pointers to working SDK examples would be greatly appreciated. Core and Memory
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WDOGは8ビットシーケンスリフレッシュを使用できません S32K144のウォッチドッグを更新するために、8ビット書き込みを4回行うことができません。16ビットと32ビットはどちらも許容されますが、8ビットは許容されません。写真に示されている8ビット書き込み方法を試しましたが、すべて失敗しました。元のマニュアルは以下のとおりです。 更新書き込みシーケンスは • 2 つの 16 ビット書き込み (0xA602、0xB480) または 4 つの 8 ビット書き込み (0xA6、0x02、0xB4、 0x80) WDOG_CS[CMD32EN]が0の場合。 • WDOG_CS[CMD32EN]が1の場合、32ビット書き込みが1回行われます(0xB480_A602)。 CNT登録簿へ。両方のメソッドはWDGタイムアウト前に実行されなければなりません。そうでない場合、 ウォッチドッグがMCUをリセットします。 Re: WDOG cannot use 8-bit sequence refresh 更新シーケンスを開始する前に、グローバル 割り込み。そうでなければ、割り込みによって事実上無効になる可能性がある 更新シーケンス、更新前に割り込みが発生した場合 書き込み完了。シーケンスが終了したら、グローバルを復元します 割り込み制御状態。割り込みチェックに関する参考情報 Re: WDOG cannot use 8-bit sequence refresh 犬に餌を与える前と後にスイッチが遮断されたことを確認します。同じシナリオにおいて、給紙順序を変更し、16ビット給紙方式を使用した場合のみ成功したが、8ビット給紙方式は失敗し、8ビット給紙順序の調整は効果がなかった。
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HSE_FWが存在する場合、S32K324のWFIビットがPRTN0_CORE0_STATに設定されない S32K324 MCUにおいて、HSE_FWが存在する場合にPRTN0_CORE0_STATのWFIビットが設定されないという問題が発生しています。 HSE_FWを搭載していないMCUでは、WFIは適切に設定され、アプリは正常に動作します。 HSE_FWをインストールする際に、何か特別な操作が必要ですか? ありがとうございます アニル
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LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Hi everyone, I am encountering an intermittent LIN communication issue during prolonged operation and would appreciate your expertise. The system is configured with NXP S32K3xx (EB Tresos 28.2, SW32K3_STD_4.4_2.0.2RD2211) as a LIN master, sending PIDs 0x11 (slave response), 0x14 (slave response), and 0x10 (host request) every 10ms to a motor control board slave. Initial communication operates normally for the first 2 minutes, but after approximately 10 minutes, intermittent timeout errors ("LIN_ID/frame error") occur, accompanied by incomplete frame transmission (only Break Field and Sync Byte observed on the oscilloscope, no PID/data). Debugging revealed that the Lpuart_Lin_ip_FrameIrqHandler interrupt ceases to trigger during failures, leaving the global state structure Lpuart_Lin_ip_apxStateStructureArray oscillating between LIN_TX_BUSY and LINOPTIONAL, indicating a potential TX state machine lock. Notably, the issue arises only after extended runtime, suggesting possible temperature sensitivity, resource conflicts, or peripheral configuration drift. Could this be caused by IRQ flag misconfiguration (e.g., accidental TX Complete IRQ disable), clock instability, or a known silicon errata? Guidance on diagnosing LPUART status registers (LPUART_STAT), IRQ enable bits, or clock integrity checks would be invaluable. Please advise on further steps or required data for analysis.  Std_ReturnType LinMstr_DataChk(uint8 current_frame_index) { Std_ReturnType ret_val = E_NOT_OK; static uint8 linSdu[8] = {0}; static uint8 *linSduPtr = linSdu; Lin_PduType *current_frame = &Lin_Schedule_Frames[current_frame_index]; lin_data.rx_status = Lin_GetStatus(LIN_CHANNEL_0, &linSduPtr); do { if (LIN_OPERATIONAL == lin_data.rx_status) { Lin_SendFrame(LIN_CHANNEL_0, current_frame); lin_state = LIN_STATE_TX_READY; break; } else { /* When send a wakeup signal to LIN BUS, the init state switch to LIN_OPERATIONAL */ } if (current_frame->Drc == LIN_FRAMERESPONSE_TX) { /** * State Machine Transitions: * 1. On entering `LIN_STATE_TX_READY`, the Master initiates frame transmission. * 2. If a Slave response is validated (`LIN_RX_OK`), transition to `LIN_STATE_RX_COMPLETED`. * 3. Automatically advance to the next frame in the schedule table. */ switch (lin_state) { case LIN_STATE_TX_READY: { if (LIN_TX_OK == lin_data.rx_status) { MotMgr_SetMasterE2ECounter(); lin_state = LIN_STATE_TX_COMPLETED; return E_OK; } else { lin_state = LIN_STATE_TIMEOUT_ERROR; } break; } case LIN_STATE_RX_COMPLETED: { /* After send the last frame sucessfully, the next frame shall be send immediately */ Lin_SendFrame(LIN_CHANNEL_0, current_frame); lin_state = LIN_STATE_TX_READY; break; } /* This status depends on the order of the schedule. Now, it won't enter this branch */ case LIN_STATE_TX_COMPLETED: { /* Only Using in the last frame DRC is TX */ Lin_SendFrame(LIN_CHANNEL_0, current_frame); lin_state = LIN_STATE_TX_READY; break; } case LIN_STATE_TIMEOUT_ERROR: { Lin_SendFrame(LIN_CHANNEL_0, current_frame); break; } default: { /* If LIN_FRAME_ERROR, the lin_state is LIN_IDLE, enter this branch to send Frame again.*/ Lin_SendFrame(LIN_CHANNEL_0, current_frame); lin_state = LIN_STATE_TX_READY; break; } } } else if (current_frame->Drc == LIN_FRAMERESPONSE_RX) { switch (lin_state) { case LIN_STATE_TX_COMPLETED: { /** * [Action] Send slave frame header and transition to waiting state(Waiting response from Slave). * - Transmits the header of the RX frame to initiate Slave response. * - State updated to LIN_STATE_RX_WAITING_RESP to monitor response. */ Lin_SendFrame(LIN_CHANNEL_0, current_frame); lin_state = LIN_STATE_RX_WAITING_RESP; break; } case LIN_STATE_RX_WAITING_RESP: { /** * [Polling] Check Slave response status. * - If LIN_RX_OK: Valid response received, transition to completed state. * - Else: Handle timeout or errors (BUSY/NO_RESPONSE). */ if (LIN_RX_OK == lin_data.rx_status) { /* Reveive Data from Buffer */ if (current_frame->Pid == 0x14U) { linmstr_debounce.timeout_cnt_14 = LINMSTR_TIME_BASE; if (linmstr_rte_out.tmout_flag_14 == TRUE) { linmstr_debounce.recovery_cnt_14 += LINMSTR_TIME_BASE; if (linmstr_debounce.recovery_cnt_14 >= LINMSTR_RECOVERY_DURATION) { linmstr_rte_out.tmout_flag_14 = FALSE; } } for (uint8 index = 0U; index < 8U; index++) { lin_data.response_buffer[LINMSTR_PID_14][index] = linSduPtr[index]; } } /* Put the signals of the same message into the same buffer */ else if (current_frame->Pid == 0x11U) { if (linmstr_rte_out.tmout_flag_11 == TRUE) { linmstr_debounce.recovery_cnt_11 += LINMSTR_TIME_BASE; if (linmstr_debounce.recovery_cnt_11 >= LINMSTR_RECOVERY_DURATION) { linmstr_rte_out.tmout_flag_11 = FALSE; } } linmstr_debounce.timeout_cnt_11 = LINMSTR_TIME_BASE; MotMgr_SetSlaveE2ECounter(); for (uint8 index = 0U; index < 8U; index++) { lin_data.response_buffer[LINMSTR_PID_11][index] = linSduPtr[index]; } } else { /* fall-through */ } /* Reveive Data from Buffer */ lin_state = LIN_STATE_RX_COMPLETED; ret_val = E_OK; } else { /** * [Error Handling] Possible states: * - LIN_TX_BUSY: Ongoing transmission blocking new operations * - LIN_RX_NO_RESPONSE: Slave did not respond within timeout * - LIN_RX_BUSY: Receiving data in progress. * - In this state, send a frame to polling the status of Slave. */ /* The Logic implement in LinIf.c */ Lin_SendFrame(LIN_CHANNEL_0, current_frame); lin_state = LIN_STATE_TIMEOUT_ERROR; } /* If enter DIAG schedule table, the state may be stay the LIN_STATE_RX_WAITING_RESP, so we shall consider the condition that the last state is Rx and Lin state is LIN_STATE_RX_WAITING_RESP, to avoid break continuous sending of schedule table */ break; } case LIN_STATE_RX_COMPLETED: { /** * [Re-Initiate] Start next RX frame transaction. * - Previous state validation: Requires LIN_RX_OK as precondition. * - Sends header and transitions to LIN_STATE_RX_WAITING_RESP. * - Timeout period defined by LIN specification or application config. */ Lin_SendFrame(LIN_CHANNEL_0, current_frame); lin_state = LIN_STATE_RX_WAITING_RESP; break; } case LIN_STATE_TIMEOUT_ERROR: { if (LIN_RX_OK == lin_data.rx_status) { lin_state = LIN_STATE_RX_COMPLETED; } else { /* Detect the Time out error */ if (0x11U == current_frame->Pid) { linmstr_debounce.recovery_cnt_11 = LINMSTR_TIME_BASE; if (linmstr_rte_out.tmout_flag_11 == FALSE) { linmstr_debounce.timeout_cnt_11 += LINMSTR_TIME_BASE; if (linmstr_debounce.timeout_cnt_11 >= LINMSTR_DURATION_11) { linmstr_rte_out.tmout_flag_11 = TRUE; } } } if (0x14U == current_frame->Pid) { linmstr_debounce.recovery_cnt_14 = LINMSTR_TIME_BASE; if (linmstr_rte_out.tmout_flag_14 == FALSE) { linmstr_debounce.timeout_cnt_14 += LINMSTR_TIME_BASE; if (linmstr_debounce.timeout_cnt_14 >= LINMSTR_DURATION_14) { linmstr_rte_out.tmout_flag_14 = TRUE; } } } Lin_SendFrame(LIN_CHANNEL_0, current_frame); } break; } default: Lin_SendFrame(LIN_CHANNEL_0, current_frame); lin_state = LIN_STATE_TIMEOUT_ERROR; break; } } } while (0U); return ret_val; } Best regards, Dongxun Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Hi @dongxun, Thanks for the detailed analysis. Based on the behavior observed, I don't believe this stems from a software driver bug or a hardware fault in the UART module. Instead, it aligns with typical embedded system behavior under interrupt-heavy conditions. The root cause appears to be ISR preemption, where the LIN RX/TX interrupt was delayed due to higher-priority interrupts, leading to a buffer overrun (OR bit set in the STAT register). The issue was effectively resolved by raising the priority of the LPUARTLIN-RXTx_IRQ, which prevented further preemption and restored stable communication. This kind of mitigation is a good example of how interrupt prioritization can impact real-time communication reliability. Best regards, Daniel Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Hi, Dan     Thank you for your detailed recommendations regarding the LPUART interrupt prioritization and debugging methodology. Moving forward, we will actively monitor the ​​fix overviews​​ in subsequent RTD releases to align with ongoing optimizations.     Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Hi @dongxun, You're currently using an outdated version of the RTD. Please refer to the release notes for each version, which include detailed lists of Known Issues and Changes.. Consider the following: Ensure the LPUART interrupt is not being masked or delayed by higher-priority ISRs. If possible, assign the highest priority to the LPUART interrupt to guarantee timely handling. Implement debug logging around the LIN ISR and state transitions. Compare logs from successful and failed transmissions to identify anomalies or timing inconsistencies. Capture the values of key LPUART registers (e.g., STAT, CTRL, BAUD) during failure conditions to detect stuck flags or misconfigurations. Test with a reduced LIN schedule (e.g., only PID 0x10) to isolate timing-related issues and simplify debugging. Stack Integrity Check Investigate potential stack overflow issues: Monitor the stack pointer during runtime, Initialize SRAM with a known pattern at startup to detect overflows, consider increasing the stack size. Read-After-Write Serialization Apply read-after-write techniques to ensure register writes are properly completed and synchronized, especially in critical peripheral configurations. Regards, Daniel Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Dear Team, I am writing to report the root cause and resolution of a recurring LIN communication failure observed during data transmission. After thorough investigation, the issue was traced to the ​​LPUART peripheral's status register (STAT)​​. Specifically, the ​​Overrun Error (OR) bit​​ was consistently set in cases where the Protocol Identifier (PID) failed to transmit. This flag indicates that newly received data arrived before the previous data could be processed by the interrupt service routine (ISR), resulting in data loss and communication halts. To resolve this: ​​Immediate Mitigation​​: I cleared the OR bit in the STAT register, which restored normal LIN communication immediately. ​​Root Cause Analysis​​: I suspect that the LIN data processing ISR (​​LPUARTLIN-RXTx_IRQ​​) was interrupted by higher-priority interrupts entering critical sections. This caused delays in ISR execution, leading to buffer overrun conditions. ​​Corrective Action​​: The priority of LPUARTLIN-RXTx_IRQ was elevated to minimize preemption risks. Subsequent stress testing (continuous master-slave communication for >10 hours) confirmed stability under extended operation. Request for Feedback While the current solution is effective, I welcome suggestions for further optimizations, such as: Implementing ​​hardware flow control​​ (if supported by the LPUART peripheral) to prevent overruns. Adding ​​buffer occupancy checks​​ in the ISR to proactively clear data before overflow occurs. Exploring ​​DMA-based data transfer​​ to reduce CPU intervention and interrupt latency    . Please share your insights on enhancing this approach. Best regards, dongxun, Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Hello, as shown in the picture, I think I have also encountered this problem. Could you please tell me how you solved it? Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Hello, I encountered a problem with LIN communication when using the MCU as the slave device. The phenomenon is as follows: After the program was burned, the LIN communication was normal. I used the MCU as the slave device to respond to the frame header from the host. However, during the operation process, after running for a certain period of time, an unresponsive situation would occur. The observed phenomenon was that the host was continuously sending unresponsive frame headers. After seeing this post, I attempted to modify the interrupt priority of LIN, but the phenomenon still persisted. The phenomenon I observed through the oscilloscope was that when there was no response at the frame header, the synchronization interval segment, synchronization segment and PID in the frame header were all present, but the response data part was absent. Could you please tell me where I should look for the cause? I'm looking forward to your reply. Thank you. Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Hi, Aoyng,   I noticed that the unresponsiveness only occurs after a certain period of operation. This suggests that the LIN state machine was initially functioning correctly when the MCU acted as a slave. Have you observed exactly where the internal state machine gets stuck when the MCU stops responding?   Furthermore, have you consulted the reference manual and checked the slave-related error registers to determine if a specific error has triggered? For the S32K312 MCU, the Lpuart_Lin_Ip_StatusFlagType structure contains descriptions for various fault conditions. I’ve personally encountered an issue (while using the MCU as a master) where the LPUART_LIN_IP_RX_OVERRUN flag was set, preventing the MCU from transmitting the Sync segment and subsequent data. You should be able to identify where the slave is failing by inspecting these registers and the state machine status. I believe this should be a straightforward troubleshooting step.  Best regards,  dongxun Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Hi Aoyng,   According to your screenshot, an Overrun Error clearly occurred during MCU data reception, leading to the communication deadlock. You can use the following method to manually clear the error flag and restore communication. As for the specific details of this error, please refer to the datasheet and other reference materials.   if(TRUE == Lpuart_Lin_Ip_HwGetStatusFlag(Base, LPUART_LIN_IP_RX_OVERRUN)) { /* Clear RxOverrun status */ (void)Lpuart_Lin_Ip_HwClearStatusFlag(Base, LPUART_LIN_IP_RX_OVERRUN); } Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Furthermore, when I was looking for a way to clear the overrun, I found that there was a function specifically designed to perform this clearing operation. And this function is executed when an overrun occurs and is detected within the interrupt. What is the reason why my side was not cleared? Looking forward to your response. Thank you. Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID OK, I see that this status is being detected during the interruption. May I perform the aforementioned clearing operation in my own callback function, as shown in the figure below? The communication (both sending and receiving) of my slave program with the host is all triggered within the callback function. Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID I currently plan to incorporate this clearing operation into the interrupt service function for execution. Is this feasible? Or, could you please tell me which scheduling you are referring to? It would be better if there were some code for us to review. I would be very grateful if you could provide it. Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Hi, Aoyng,   It is recommended to include this clearing operation in other scheduling programs, or if you can ensure that the callback function can come in during RX_overrun, you can put it here. Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID OK, thank you for your suggestion. I am using the S32K314 chip. According to the official documentation, I found that the size of the LPUART receive buffer for this chip is 4 bytes. May I understand that when the received data exceeds 4 bytes, an overflow interrupt will be triggered and it needs to be cleared at this time? Can I change the size of the receive buffer? The information I obtained from the above picture is that the default size of the receive buffer is currently 1 byte, but it was initially mentioned as 4 bytes. I am a bit confused about this. Do you have any understanding? Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Sorry dongxun, perhaps the phenomenon I observed yesterday was incorrect. When I was debugging, if the monitoring program encountered a problem in which the program would enter an interrupt state, after receiving the frame header (the current MCU is the slave), it would again enter the interrupt and would enter this function (as shown in the following figure). It did not stop at the LPUART_LIN_IP_RX_OVERRUN state, but what I should do at this point is to receive the data. Then when it enters the interrupt again, it would stop at LPUART_LIN_IP_FRAME_ERR, and then clear the error. But as for why it shows 1 in the OR register, I'm not sure. Do you have any ideas? Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Hi, Aoyng,   To the best of my knowledge, this is a bug. I found the following description in the errata manual of "SW32K3_S32M27x_RDD_R21-11_5.0.0_D2410_Release Notes. pdf". As I am using an older RTD version, it is evident that this bug exists in my 2.00 version. Re: LIN:S32K312 MCU as a Master, Lin Timeout Error whiling waiting for LinID Hi, I placed it in a periodic function of the OS for calling (handwritten code), specifically in the function that calls Lin_SendFrame. It is called every time before sending LIn data You can try and test it to see if there are still any issues.
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How Are You Optimizing Packet Processing Performance on QorIQ T-Series Platforms? Has anyone worked on optimizing packet processing performance on QorIQ T-Series platforms under heavier network traffic conditions? We are currently testing a T-Series based system for continuous packet forwarding and noticed that CPU utilization increases quite quickly once traffic bursts become sustained. The platform remains stable, but latency consistency between cores starts varying under load. I am particularly interested in understanding how others are handling: interrupt distribution queue balancing multicore workload tuning memory/cache optimization latency reduction during high throughput Would appreciate hearing about any practical tuning methods or performance observations from real deployments. Re: How Are You Optimizing Packet Processing Performance on QorIQ T-Series Platforms? Hello, Yes — there is documented guidance for exactly the kinds of tuning you listed on QorIQ T-Series/DPAA1 systems, in the LA1224-RDB-BSPUG and it aligns closely with the behavior you are seeing under sustained bursts: as load rises, the critical tradeoff becomes throughput vs. per-core latency consistency . The retrieved documentation points to five main levers: interrupt moderation, FQ/channel distribution policy, dequeue/QMI tuning, cache stashing/CPC usage, and order-handling mode selection. Regards
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BSDL files for RW61x Does NXP publish BSDL files for JTAG boundary scan for the RW61x?  I can't seem to find them. Product: WiFi RW6XX Re: BSDL files for RW61x Hello, Hope you are doing well. Are you using RTOS or Zephyr? If RTOS, what SDK version? If Zephyr, which repository? Also, could you please clarify if you are working with a module? Regards, Ricardo Re: BSDL files for RW61x I'm not sure why OS would have anything to do with boundary scan files. I'm using Zephyr 4.4.0.   Module is from u-blox, but has an RW610 on it. Re: BSDL files for RW61x We are using the BGA. Re: BSDL files for RW61x Hello, Could you please clarify which chip package are you using? BGA/QFN or CSP? Best Regards, Ricardo Re: BSDL files for RW61x Hello, I am also looking for the BSDL file for the rw61x series chips. Can you please point me in the right direction to be able to download these files? Thanks, Alex Re: BSDL files for RW61x Could someone from NXP actually answer this question?? Is there a BSDL file for the RW61x and if so where can we download it? Thanks, Alex Titsworth
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i.MX95搭載RGB-IRカメラOX05B1S ハイ i.MX Linux リファレンス マニュアルによると、SCH-89961 アダプタ カードを入手する方法を教えていただけますか。私の要望は、RGB-IRカメラをi.MX95に統合することです。または、i.MX95と互換性のある他のRGB-IRカメラはありますか? よろしくお願いします。 Re: RGB-IR Camera OX05B1S with i.MX95 1. OX05B1S + RPI-CAM-MINISAS on FRDM i.MX95 はい、ただしFPCケーブルも必要です。 センサー単体では不十分です。 2. Leopard Imaging LI-OX05B1S-MIPI-137H 既存のi.MX95ドライバと互換性がありますか? はい、ただしISP処理された出力ではなく、RAW MIPI出力モードを使用する場合に限ります。 3. 5MP RGB-IR GMSL2カメラ(Jetson AGX Orinタイプ) これはi.MX95でも動作しますか? いいえ、直接的には違います。お勧めしません。 4. ISPが事前統合されたモジュール i.MX95のISPを無効にする必要はありますか? はい、モジュールが処理済みのビデオを出力する場合は、i.MX95 ISPをバイパスまたは無効にする必要があります。 Re: RGB-IR Camera OX05B1S with i.MX95 こんにちは@yipingwang 迅速なご対応ありがとうございます。下記のご要望について、追加情報をご提供いただけますでしょうか。 1.OX05B1Sセンサを使用したいのですが、センサとRPI-CAM-MINISASを購入すればFRDM i.MX95に統合するのに十分でしょうか?FPCケーブルも必要ですか? 2. ウィル LI-OX05B1S-MIPI-137H - Leopard Imaging Inc.このモジュールは既存のi.MX95ドライバでも動作しますか? 3. では NVIDIA Jetson AGX Orin 用 5MP RGB-IR グローバル シャッター GMSL2 カメラ Leopardとe-ConsystemカメラモジュールにはISPがプリインストールされていますが、これはi.MX95のISPを無効にする必要があるという意味でしょうか? よろしくお願いいたします Re: RGB-IR Camera OX05B1S with i.MX95 SCH-89961 Rev.Bは、 NXP社製のカメラアダプタボードです。 i.MX Linuxリファレンスマニュアルでは、接続に使用されるMIPI-CSIアダプタとして明示的に記載されています。 オムニビジョン OS08A20 オムニビジョン OX05B1S これは市販製品ではありません(Mouser/Digi-Keyでは販売されていません)。 これは、NXPおよび一部のパートナー企業がEVKの検証のために社内で使用しています。 SCH-89961は直接購入することはできません。 NXPは、お客様がSCH-89961を使用することを想定していません。代わりに、i.MX95 EVKでサポートされている標準のmini-SASまたはFPC MIPIアダプタを使用してください。 サポートされている代替手段は以下のとおりです。 アダプタ 目的 RPI-CAM-MINISAS FPCカメラ → mini-SAS IMX-MIPI-HDMI 表示/出力 IMX-LVDS-HDMI 表示/出力 これらは公式のi.MX95カメラソフトウェアパックのドキュメントに記載されています。 RAW MIPI-CSI RGB-IRセンサ(推奨) i.MX95 ISPはRGB-IR融合をネイティブにサポートしています。 最もよく知られている選択肢: センサ ベンダ 備考 OX05B1S オムニビジョン RGB-IR、公式サポート対象 OS08A20 オムニビジョン OX05B1Sと同じドライバーを使用します AR0234 RGB-IR onsemi オートモーティブ ビジョンに使用される OV2312 RGB-IR オムニビジョン グローバルシャッター(移植が必要) OS08A20とOX05B1Sは、i.MX95上で同じカーネルドライバを使用してすぐに動作します。 事前統合型RGB-IRカメラモジュール(より簡単) Linux対応の既製RGB-IRカメラを提供するベンダー: e-conシステムズ RGB-IRカメラモジュール センサーチューニングとISPサポート ご要望に応じて、i.MX95のカスタマイズ対応も可能です。 例: OV2312 RGB-IR AR0830 RGB-IR Re: RGB-IR Camera OX05B1S with i.MX95 こんにちは@yipingwang ご説明いただき、誠にありがとうございます。 もう一つ質問ですが、これは「22ピン/15ピン カメラコネクタ FPC ケーブル」ですか? 別売りで購入可能です。インターネット検索では複数の選択肢が出てくるため、質問させていただきました。 Re: RGB-IR Camera OX05B1S with i.MX95 こんにちは@yipingwang ご確認の上、ご回答いただけますでしょうか?Arrow Electronicsのウェブサイトで、センサの複数の部品番号を確認しました。正確な部品番号とFPCケーブルの部品番号を特定するのを手伝っていただけませんか? https://www.arrow.com/en/search-result.html?keyword=ox05b1s&currPage=1 よろしくお願いいたします Re: RGB-IR Camera OX05B1S with i.MX95 はい、これらの22ピン↔15ピンFPC(CSIカメラ)ケーブルは標準規格で入手しやすく、問題なく個別に購入できます。 Re: RGB-IR Camera OX05B1S with i.MX95 コミュニティ内でカメラの設定に関するスレッドがまだいくつか残っているのを見かけます。もしご存知の方がいらっしゃいましたら、私の質問にお答えいただけますでしょうか?ご協力ありがとうございます。
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PN7462AU 手册 使用运行时命令进行射频发射机功率控制 我正在开发 PN7462AU,需要实现手动射频发射器功率控制,具有 3 个可配置的功率等级(低/中/高),可以根据收到的 UART/CLI 命令动态更改。 目前,DPC 会自动处理 TX 功率,但我的要求是绕过/修复 DPC 行为并在运行时手动切换 TX 功率级。 我想知道 建议使用哪些射频寄存器来手动控制 PN7462AU 的发射功率? 是否有任何应用程序接口可用于运行时 TX 电源切换? 先行致谢。 NFC读卡器库
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S32K312マイクロコントローラ用RTDパッケージの問題(サンプルプロジェクト向け) プロジェクトで s32k312 マイクロコントローラを使用し、通信用のサンプル プロジェクトをコンパイルしようとしましたが、RTD パッケージが互換性がないというエラーが発生しました。別の RTD パッケージを試しましたが、うまくいきませんでした。s32 design studio 3.6 バージョンを使用しています。この問題をどのように解決すればよいでしょうか。
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VS 代码扩展更新破坏了 RTOS 查看器 你好 到目前为止,我们使用的是 1.9.20 版本(旧版)的 vscode 工具,并使用https://marketplace.visualstudio.com/items?itemName=mcu-debug.rtos-views查看 freertos 线程的状态 (RT1189)。更新后,该工具不再工作,只显示"RTOS 检测未完成。下次停止时会恢复。" 有什么建议吗? 谢谢! Re: VS code extension update broke RTOS viewer 您好, MCUXpresso for VS Code 长期以来一直拥有自己的 RTOS 查看器。请查阅https://mcuxpresso.nxp.com/mcux-vscode/latest//html/RTOS-Details.html 此外,还有一项旧的更改,即扩展从使用Microsoft C/C++ 调试适配器迁移到基于 Cortex-Debug 的自有调试适配器。你必须创建一个新的调试配置,它会自动创建一个基于我们调试适配器的配置(你会注意到"mcuxpresso-debug" 作为类型)。 PS.请注意,如果使用 Segger 调试探针,则需要特别启用 RTOS 支持(请参阅 https://mcuxpresso.nxp.com/mcux-vscode/latest//html/Debug-Views.html#enabling-rtos-awareness)。 此致, 克里斯蒂安
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Macau baccarat short-term profit and long-term loss of the core reasons online customer service 15368832624
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USB Host mode Host init error 3 LPC54605J256 Hi friends, I'm having a problem trying to init the usb host.  No matter what I try, it keeps giving error 3 - can't locate driver instance?  Any insight welcome.  thank you. LPC54605J256.  Custom board. I have some parts of the usb seemingly operational - here's the main, and prints of the usb system. I am a newcomer to embedded so I have probably overlooked something, perhaps in the usb numbering, or the extra usb init in main.  I have tried to only use the config tools.  Clocks, pins and peripherals are all looking good, relevant usb pins, host mode, nvic, enabled.  fsl-power.h is included.  USB is taking PLL at 48Mhz.  I have the correct resistor REXT value.  All config tools defined USB pins and USBHSH are defined as demanded by tool. USBID is, not tied in any direction, but that can be forced with portmode as I understood it?  Power is provided to the keypad.  VUSB - 4.5v.  LED lights on the keypad, but as init fails, nothing more happens : ) I have checked the controller ID.  I'm using for High Speed Host. #define CONTROLLER_ID kUSB_ControllerIp3516Hs0 it is declared in host config.h as 1U int main(void) { vPortDefineHeapRegions(xHeapRegions); BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitBootPeripherals(); SEGGER_RTT_Init(); PRINTF("System Booting...\r\n"); /* USB1 HS PHY POWER */ POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* ENABLE USB1 HS HOST CLOCK */ CLOCK_EnableClock(kCLOCK_Usbh1); CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U); /* FORCE USB1 INTO HOST MODE */ USBHSH->PORTMODE &= ~(1UL << 16); USBHSH->PORTMODE |= (1UL << 16); /* Small delay for PHY */ for (volatile uint32_t d = 0; d < 180000; d++) __NOP(); PRINTF("USB PORTMODE = 0x%08lX\r\n", USBHSH->PORTMODE); PRINTF("USBHSH->PORTSC1 = 0x%08lX\r\n", USBHSH->PORTSC1); PRINTF("USBHSH->USBSTS = 0x%08lX\r\n", USBHSH->USBSTS); PRINTF("USBHSH->USBCMD = 0x%08lX\r\n", USBHSH->USBCMD); /* START USB HOST STACK */ usb_status_t usbStatus = USB_HostInit(CONTROLLER_ID, &g_HostHandle, USB_HostEvent); if (usbStatus == kStatus_USB_Success) { PRINTF("USB HOST INIT OK\r\n"); } else { PRINTF("USB HOST INIT FAILED: %d\r\n", (int)usbStatus); } Process: JLinkGDBServerCLExe System Booting... USB PORTMODE = 0x00050000 USBHSH->PORTSC1 = 0x00001000 USBHSH->USBSTS = 0x00000000 USBHSH->USBCMD = 0x00000501 USB HOST INIT FAILED: 3 Starting scheduler... LPC546xx Re: USB Host mode Host init error 3 LPC54605J256 I put in some more print statements to look at the clock.  It's set up right in clocks tool, but seems not to be running normally? /* ====================== MAIN ====================== */ int main(void) { vPortDefineHeapRegions(xHeapRegions); BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitBootPeripherals(); SEGGER_RTT_Init(); PRINTF("System Booting...\r\n"); /* USB1 HS PHY POWER */ // POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* ENABLE USB1 HS HOST CLOCK */ // CLOCK_EnableClock(kCLOCK_Usbh1); // CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U); // status_t status; // status = CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 480000000U); // PRINTF("USB host clock init status = %d\r\n", status); /* FORCE USB1 INTO HOST MODE */ USBHSH->PORTMODE &= ~(1UL << 16); USBHSH->PORTMODE |= (1UL << 16); /* Small delay for PHY */ for (volatile uint32_t d = 0; d < 180000; d++) __NOP(); PRINTF("USB PORTMODE = 0x%08lX\r\n", USBHSH->PORTMODE); PRINTF("USBHSH->PORTSC1 = 0x%08lX\r\n", USBHSH->PORTSC1); PRINTF("USBHSH->USBSTS = 0x%08lX\r\n", USBHSH->USBSTS); PRINTF("USBHSH->USBCMD = 0x%08lX\r\n", USBHSH->USBCMD); PRINTF("\r\n--- USB CLOCK DIAGNOSTICS ---\r\n"); /* USB PLL state */ PRINTF("USBPLLCTRL : 0x%08lX\r\n", SYSCON->USBPLLCTRL); PRINTF("USBPLLSTAT : 0x%08lX\r\n", SYSCON->USBPLLSTAT); /* USB1 clock mux + divider */ PRINTF("USB1CLKSEL : 0x%08lX\r\n", SYSCON->USB1CLKSEL); PRINTF("USB1CLKDIV : 0x%08lX\r\n", SYSCON->USB1CLKDIV); /* Power gating snapshot */ PRINTF("PDRUNCFG : 0x%08lX\r\n", SYSCON->PDRUNCFG); /* SDK-level view */ PRINTF("USB1CLK freq: %lu\r\n", CLOCK_GetFreq(kCLOCK_UsbClk)); PRINTF("--- END USB CLOCK DIAGNOSTICS ---\r\n\r\n"); /* START USB HOST STACK */ usb_status_t usbStatus = USB_HostInit(CONTROLLER_ID, &g_HostHandle, USB_HostEvent); if (usbStatus == kStatus_USB_Success) { PRINTF("USB HOST INIT OK\r\n"); } else { PRINTF("USB HOST INIT FAILED: %d\r\n", (int)usbStatus); } System Booting... USB PORTMODE = 0x00050000 USBHSH->PORTSC1 = 0x00001000 USBHSH->USBSTS = 0x00000000 USBHSH->USBCMD = 0x00000501 --- USB CLOCK DIAGNOSTICS --- USBPLLCTRL : 0x00001017 USBPLLSTAT : 0x00000001 USB1CLKSEL : 0x00000002 USB1CLKDIV : 0x00000005 PDRUNCFG : 0x40000610 USB1CLK freq: 0 --- END USB CLOCK DIAGNOSTICS --- Re: USB Host mode Host init error 3 LPC54605J256 Hi Carlos, thanks for your quick reply.  I'm using SDK 2.14.0 (I tried to use more modern, but it failed on a, I believe also a USB driver actually - IDE stated mismatch between SDK (latest) and needed (older) driver) Sorry I don't remember the details of that now. I'm using a CPU system clock of 180Mhz.  with this -  CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U); status_t status; status = CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U); PRINTF("USB host clock init status = %d\r\n", status); I return - USB host clock init status = 1 does that help? Re: USB Host mode Host init error 3 LPC54605J256 Hi @SOOTY1, Thanks for your post! Could please share which SDK version you are using? Please review the return value of CLOCK_EnableUsbhs0HostClock. You could refer to the USB Host examples at the SDK for the LPCXpresso54608 board but that examples use USB FS instead of HS.  To have high-speed USB operating, the CPU clock must be configured to a minimum frequency of 60 MHz. BR. Re: USB Host mode Host init error 3 LPC54605J256 I tried some more and it seems USB clock is failing to attach properly and run.  It is selected correctly in clock config with 48Mhz input, from USBPLL. int main(void) { vPortDefineHeapRegions(xHeapRegions); BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitBootPeripherals(); SEGGER_RTT_Init(); PRINTF("System Booting...\r\n"); PRINTF("Core clock = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_CoreSysClk)); /* Power and Clock */ POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); // External crystal analog domain POWER_DisablePD(kPDRUNCFG_PD_VD3); // USB PLL domain POWER_DisablePD(kPDRUNCFG_PD_VD5); // USB PHY domain SDK_DelayAtLeastUs(1500, SystemCoreClock); CLOCK_EnableClock(kCLOCK_Usbh1); CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U);  [I don't know should it be 48M or 480M here neither work anyway] PRINTF("USB PLL freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbPll)); PRINTF("USB1CLK freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbClk)); /* Force Host mode - bit 16 */ USBHSH->PORTMODE &= ~(1UL << 16); USBHSH->PORTMODE |= (1UL << 16); PRINTF("USB PORTMODE = 0x%08lX\r\n", USBHSH->PORTMODE); PRINTF("USBHSH->PORTSC1 = 0x%08lX\r\n", USBHSH->PORTSC1); PRINTF("USBHSH->USBSTS = 0x%08lX\r\n", USBHSH->USBSTS); PRINTF("USBHSH->USBCMD = 0x%08lX\r\n", USBHSH->USBCMD); PRINTF("\r\n--- USB CLOCK DIAGNOSTICS ---\r\n"); /* USB PLL state */ PRINTF("USBPLLCTRL : 0x%08lX\r\n", SYSCON->USBPLLCTRL); PRINTF("USBPLLSTAT : 0x%08lX\r\n", SYSCON->USBPLLSTAT); /* USB1 clock mux + divider */ PRINTF("USB1CLKSEL : 0x%08lX\r\n", SYSCON->USB1CLKSEL); PRINTF("USB1CLKDIV : 0x%08lX\r\n", SYSCON->USB1CLKDIV); /* Power gating snapshot */ PRINTF("PDRUNCFG : 0x%08lX\r\n", SYSCON->PDRUNCFG); /* Optional SDK-level view (if available) */ // PRINTF("USB1CLK freq: %lu\r\n", CLOCK_GetFreq(kCLOCK_UsbPll)); PRINTF("--- END USB CLOCK DIAGNOSTICS ---\r\n\r\n"); /* Init stack */ usb_status_t status = USB_HostInit(CONTROLLER_ID, &g_HostHandle, USB_HostEvent); if (status != kStatus_USB_Success) { PRINTF("USB_HostInit failed with status %d)\r\n", status); } gives -  Process: JLinkGDBServerCLExe System Booting... Core clock = 180000000 Hz USB PLL freq = 0 Hz USB1CLK freq = 0 Hz USB PORTMODE = 0x00050000 USBHSH->PORTSC1 = 0x00001000 USBHSH->USBSTS = 0x00000000 USBHSH->USBCMD = 0x00000501 --- USB CLOCK DIAGNOSTICS --- USBPLLCTRL : 0x00000D3F USBPLLSTAT : 0x00000001 USB1CLKSEL : 0x00000002 USB1CLKDIV : 0x00000000 PDRUNCFG : 0x40000610 --- END USB CLOCK DIAGNOSTICS --- USB_HostInit failed with status 3) Is it something in the powerup sequence is incorrect?  I really don't know now. I have tried so long on this.  I think the incorrect driver/not found is also a separate thing. I have even less of an idea with that - I have it registered in the .map, enabled in the host_config, included in the build, present in the workspace . . Re: USB Host mode Host init error 3 LPC54605J256 @carlos_o  I'm still having the problems with the SDK (see thread for more details) I have today changed SDK to 25.06.00 and updated the Config Tools to 26.03 also I still get the USB Host init fail error code 3.  PLL is not starting, even though it seems configured by the book in the config tools clock tree.   Any insight is very welcome. thanks, Re: USB Host mode Host init error 3 LPC54605J256 Hi @SOOTY1  Apologize the late reply and thank you for the detailed testing you have done. Could you please remove the call to CLOCK_EnableClock(kCLOCK_Usbh1); before calling   CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U);   The reason is that the clock enable is already handled inside CLOCK_EnableUsbhs0HostClock(). Additionally, some peripherals must be disabled before changing their configuration, and enabling the clock beforehand may prevent proper reconfiguration.   Let me know your results.  Re: USB Host mode Host init error 3 LPC54605J256 @carlos_o hi, I managed to make the cpp change the divider registers (impossible using the config tool) but I still cannot get past the clock not attaching to USB1.    Please can you post a proper power up sequence, or clock attach sequence or some instruction how to get past this error.  Although I understand the USB is very particular at this point, there is surely a defined way to make this work (which I cannot find in the user manual or on the forum or online) Thanks, Re: USB Host mode Host init error 3 LPC54605J256 @carlos_o  hi, just to show the register value is not changing even after setting with config tools and visible in clockconfig.c generated file - System Booting... Core clock = 96000000 Hz After BOARD_InitBootClocks: USB PLL freq = 0 Hz Clock enable returned: 1 USB PLL freq = 0 Hz USB1CLK freq = 0 Hz USB PORTMODE = 0x00050000 USBHSH->PORTSC1 = 0x00001000 USBHSH->USBSTS = 0x00000000 USBHSH->USBCMD = 0x00000501 --- USB CLOCK DIAGNOSTICS --- USBPLLCTRL : 0x00000D3F USBPLLSTAT : 0x00000001 USB1CLKSEL : 0x00000002 USB1CLKDIV : 0x00000000 PDRUNCFG : 0x40000610 --- END USB CLOCK DIAGNOSTICS --- USB_HostInit failed with status 3 look we can see that, even though the clockconfig.c states USB1CLK is set to MAINCLKSELA - it is not actually changing the register value -  void BOARD_BootClockRUN(void) { /*!< Set up the clock sources */ /*!< Set up FRO */ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally being below the voltage for current speed */ POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /*!< Enable System Oscillator Power */ SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) | SYSCON_SYSOSCCTRL_FREQRANGE(1U)); /*!< Set system oscillator range */ /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) before calling this API since this API is implemented in ROM code */ CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ /*!< Set up SYS PLL */ const pll_setup_t pllSetup = { .pllctrl = SYSCON_SYSPLLCTRL_SELI(16U) | SYSCON_SYSPLLCTRL_SELP(8U) | SYSCON_SYSPLLCTRL_SELR(0U), .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)), .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)), .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)), .pllRate = 180000000U, .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP }; CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source*/ CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */ /*!< Set up AUDIO PLL */ const pll_setup_t audio_pllSetup = { .pllctrl = SYSCON_AUDPLLCTRL_SELI(59U) | SYSCON_AUDPLLCTRL_SELP(31U) | SYSCON_AUDPLLCTRL_SELR(0U), .pllmdec = (SYSCON_AUDPLLMDEC_MDEC(30583U)), .pllndec = (SYSCON_AUDPLLNDEC_NDEC(1U)), .pllpdec = (SYSCON_AUDPLLPDEC_PDEC(5U)), .pllRate = 48000000U, .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP }; CLOCK_AttachClk(kEXT_CLK_to_AUDIO_PLL); /*!< Set audio pll clock source*/ CLOCK_SetAudioPLLFreq(&audio_pllSetup); /*!< Configure PLL to the desired value */ /*!< Set up USB PLL */ const usb_pll_setup_t usb_pllSetup = { .msel = 95U, .nsel = 3U, .psel = 0U, .direct = true, .bypass = false, .fbsel = false, .inputRate = 12000000U, }; CLOCK_SetUsbPLLFreq(&usb_pllSetup); /*!< Configure PLL to the desired value */ /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U) before calling this API since this API is implemented in ROM code */ CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */ /*!< Set up dividers */ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 6U, false); /*!< Set USB0CLKDIV divider to value 6 */ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 0U, true); /*!< Reset USB1CLKDIV divider counter and halt it */ CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Set USB1CLKDIV divider to value 2 */ CLOCK_SetClkDiv(kCLOCK_DivSctClk, 0U, true); /*!< Reset SCTCLKDIV divider counter and halt it */ CLOCK_SetClkDiv(kCLOCK_DivSctClk, 48U, false); /*!< Set SCTCLKDIV divider to value 48 */ /*!< Set up clock selectors - Attach clocks to the peripheries */ CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE_MASK; /*!< Enable ASYNC APB subsystem */ CLOCK_AttachClk(kMAIN_CLK_to_ASYNC_APB); /*!< Switch ASYNC_APB to MAIN_CLK */ CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK); /*!< Switch USB0_CLK to USB_PLL */ CLOCK_AttachClk(kFRO_HF_to_USB1_CLK); /*!< Switch USB1_CLK to MAIN_CLK */ CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM2); /*!< Switch FLEXCOMM2 to AUDIO_PLL */ CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3); /*!< Switch FLEXCOMM3 to AUDIO_PLL */ CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM5); /*!< Switch FLEXCOMM5 to AUDIO_PLL */ CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM7); /*!< Switch FLEXCOMM7 to AUDIO_PLL */ CLOCK_AttachClk(kAUDIO_PLL_to_SCT_CLK); /*!< Switch SCT_CLK to AUDIO_PLL */ /*!< Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; } (from main shown here) int main(void) { vPortDefineHeapRegions(xHeapRegions); BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitBootPeripherals(); SEGGER_RTT_Init(); PRINTF("System Booting...\r\n"); PRINTF("Core clock = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_CoreSysClk)); PRINTF("After BOARD_InitBootClocks:\n"); PRINTF("USB PLL freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbPll)); /* === Recommended Power-up Order === */ POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); // Crystal analog domain - FIRST POWER_DisablePD(kPDRUNCFG_PD_VD3); // PLL domain POWER_DisablePD(kPDRUNCFG_PD_VD5); // PHY domain POWER_DisablePD(kPDRUNCFG_PD_USB_PLL); POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); SDK_DelayAtLeastUs(15000, SystemCoreClock); // 15ms — give crystal time to stabilize /* Force crystal oscillator */ SYSCON->SYSOSCCTRL = 0x00000000; // CLOCK_EnableClock(kCLOCK_Usbh1); status_t clkStatus = CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U); PRINTF("Clock enable returned: %d\r\n", clkStatus); PRINTF("USB PLL freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbPll)); PRINTF("USB1CLK freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbClk)); /* Force Host mode - bit 16 */ USBHSH->PORTMODE &= ~(1UL << 16); USBHSH->PORTMODE |= (1UL << 16); PRINTF("USB PORTMODE = 0x%08lX\r\n", USBHSH->PORTMODE); PRINTF("USBHSH->PORTSC1 = 0x%08lX\r\n", USBHSH->PORTSC1); PRINTF("USBHSH->USBSTS = 0x%08lX\r\n", USBHSH->USBSTS); PRINTF("USBHSH->USBCMD = 0x%08lX\r\n", USBHSH->USBCMD); PRINTF("\r\n--- USB CLOCK DIAGNOSTICS ---\r\n"); /* USB PLL state */ PRINTF("USBPLLCTRL : 0x%08lX\r\n", SYSCON->USBPLLCTRL); PRINTF("USBPLLSTAT : 0x%08lX\r\n", SYSCON->USBPLLSTAT); /* USB1 clock mux + divider */ PRINTF("USB1CLKSEL : 0x%08lX\r\n", SYSCON->USB1CLKSEL); PRINTF("USB1CLKDIV : 0x%08lX\r\n", SYSCON->USB1CLKDIV); /* Power gating snapshot */ PRINTF("PDRUNCFG : 0x%08lX\r\n", SYSCON->PDRUNCFG); /* Optional SDK-level view (if available) */ // PRINTF("USB1CLK freq: %lu\r\n", CLOCK_GetFreq(kCLOCK_UsbPll)); PRINTF("--- END USB CLOCK DIAGNOSTICS ---\r\n\r\n"); /* Init stack */ usb_status_t status = USB_HostInit(CONTROLLER_ID, &g_HostHandle, USB_HostEvent); if (status != kStatus_USB_Success) { PRINTF("USB_HostInit failed with status %d\r\n", status); } Re: USB Host mode Host init error 3 LPC54605J256 @carlos_o hi, no worries, thanks for getting back to me! Ok I removed the clock call as suggested.   It is still failing though. What's strange is that it reports the USB1CLKDIV as 0x0 every time. (its div by 6 derived from 288Mhz USBPLL) but maybe that's because its not running PLL yet?  Even without any of this power up sequence it wasn't starting up PLL.  I do have a 12Mz xtal on the board.  I also tried to change the settings away from USBPLL, to MAINCLKSELA - with 96Mhz divided down to feed USB1CLK, but although I could see Core clock Freq. change to 96Mhz, USBCLKDIV remained 0x0 (selected was /2) and USBCLKSEL 0x00000002. (should have changed value to reflect MAINCLKSELA) I don't know what to make of that. System Booting... Core clock = 180000000 Hz After BOARD_InitBootClocks: USB PLL freq = 0 Hz Clock enable returned: 1 USB PLL freq = 0 Hz USB1CLK freq = 0 Hz USB PORTMODE = 0x00050000 USBHSH->PORTSC1 = 0x00001000 USBHSH->USBSTS = 0x00000000 USBHSH->USBCMD = 0x00000501 --- USB CLOCK DIAGNOSTICS --- USBPLLCTRL : 0x00000D3F USBPLLSTAT : 0x00000001 USB1CLKSEL : 0x00000002 USB1CLKDIV : 0x00000000 PDRUNCFG : 0x40000610 --- END USB CLOCK DIAGNOSTICS --- USB_HostInit failed with status 3 current main is  int main(void) { vPortDefineHeapRegions(xHeapRegions); BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitBootPeripherals(); SEGGER_RTT_Init(); PRINTF("System Booting...\r\n"); PRINTF("Core clock = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_CoreSysClk)); PRINTF("After BOARD_InitBootClocks:\n"); PRINTF("USB PLL freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbPll)); /* === Recommended Power-up Order === */ POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); // Crystal analog domain - FIRST POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); POWER_DisablePD(kPDRUNCFG_PD_VD3); // PLL domain POWER_DisablePD(kPDRUNCFG_PD_VD5); // PHY domain POWER_DisablePD(kPDRUNCFG_PD_USB_PLL); POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); SDK_DelayAtLeastUs(15000, SystemCoreClock); // 15ms — give crystal time to stabilize /* Force crystal oscillator */ SYSCON->SYSOSCCTRL = 0x00000000; // CLOCK_EnableClock(kCLOCK_Usbh1); status_t clkStatus = CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U); PRINTF("Clock enable returned: %d\r\n", clkStatus); PRINTF("USB PLL freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbPll)); PRINTF("USB1CLK freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbClk)); /* Force Host mode - bit 16 */ USBHSH->PORTMODE &= ~(1UL << 16); USBHSH->PORTMODE |= (1UL << 16); PRINTF("USB PORTMODE = 0x%08lX\r\n", USBHSH->PORTMODE); PRINTF("USBHSH->PORTSC1 = 0x%08lX\r\n", USBHSH->PORTSC1); PRINTF("USBHSH->USBSTS = 0x%08lX\r\n", USBHSH->USBSTS); PRINTF("USBHSH->USBCMD = 0x%08lX\r\n", USBHSH->USBCMD); PRINTF("\r\n--- USB CLOCK DIAGNOSTICS ---\r\n"); /* USB PLL state */ PRINTF("USBPLLCTRL : 0x%08lX\r\n", SYSCON->USBPLLCTRL); PRINTF("USBPLLSTAT : 0x%08lX\r\n", SYSCON->USBPLLSTAT); /* USB1 clock mux + divider */ PRINTF("USB1CLKSEL : 0x%08lX\r\n", SYSCON->USB1CLKSEL); PRINTF("USB1CLKDIV : 0x%08lX\r\n", SYSCON->USB1CLKDIV); /* Power gating snapshot */ PRINTF("PDRUNCFG : 0x%08lX\r\n", SYSCON->PDRUNCFG); /* Optional SDK-level view (if available) */ // PRINTF("USB1CLK freq: %lu\r\n", CLOCK_GetFreq(kCLOCK_UsbPll)); PRINTF("--- END USB CLOCK DIAGNOSTICS ---\r\n\r\n"); /* Init stack */ usb_status_t status = USB_HostInit(CONTROLLER_ID, &g_HostHandle, USB_HostEvent); if (status != kStatus_USB_Success) { PRINTF("USB_HostInit failed with status %d\r\n", status); }
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