2400738_en-US

[#1]

RW612 FLEXCOMM3/I2S3 Supporting driver

We are using RW612 FLEXCOMM3/I2S3 with the following fixed hardware wiring:

- GPIO24 = I2S DATA input from PCM6120 SDOUT
- GPIO25 = I2S SCK output to PCM6120 BCLK
- GPIO26 = I2S WS output to PCM6120 FSYNC

The codec is PCM6120 in slave mode.
RW612 is intended to be the I2S master generating BCLK/WS and receiving audio data.

What we have verified:
- GPIO25/GPIO26 can be driven correctly in plain GPIO mode
- FLEXCOMM3 clock source is AUDIO PLL at 12.288 MHz
- I2C communication with PCM6120 is working
- PCM6120 register configuration is accepted

Observed behavior:
1. FLEXCOMM3 configured as I2S RX with kI2S_MasterSlaveNormalMaster does not generate any SCK/WS edges on GPIO25/GPIO26.
2. FLEXCOMM3 configured as I2S TX with kI2S_MasterSlaveNormalMaster also does not work: FIFOSTAT.TXNOTFULL=1, but TXLVL remains 0 after writes to FIFOWR, and no SCK/WS edges appear on the pins.
3. PCM6120 reports missing clocks (ASI_STS=0xFF, DEV_STS1=0x80).

Questions:
1. Is RW612 FLEXCOMM I2S RX in Normal Master mode expected to drive SCK/WS onto external pins?
2. Is a single FLEXCOMM instance supported for the use case “master clock generation + receive data from external codec”, or is a dual-FLEXCOMM architecture (TX master + RX slave with I2S bridge) required?
3. For FLEXCOMM3 I2S TX master, are there additional prerequisites for FIFO writes to be accepted beyond I2S_TxInit(), FIFOWR writes, and MAINENABLE?
4. Is there any known limitation specific to FLEXCOMM3 on GPIO24/25/26 (AON domain) for I2S clock output?

Pls help about the topic

Re: RW612 FLEXCOMM3/I2S3 Supporting driver

Hi @duyhung, hope you are doing well.

Would you please clarify if you are using FreeRTOS or Zephyr to perform the tests? Are you using the FRDM-RW612 board?

Please also provide which version (either SDK or Zephyr) you are using, and if you're taking an example as base for your development.

Additionally, the Reference Manual of RW612 (UM11865) includes a basic configuration guide for I2S peripheral in section 28.2, would you please confirm if you have followed this general steps?