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Mac OS Tahoe 更新 LinkServer 未找到探测器 所以我升级到了 Tahoe 版本,但是在使用 LinkServer 时找不到探测器。所以我把 LinkServer 更新到了最新版本,但它只有在终端里进入目录并手动运行后才能工作。 ./LinkServer 探测 之后就能找到探针,我可以使用MCUXpresso了。这种情况似乎也发生在其他人身上。 https://community.nxp.com/t5/MCUXpresso-General/LPC-Link2-not-found/mp/2200131/highlight/true#M5741 这是 IDE 尝试使用 LinkServer 时出现的错误。 redlink> 探针列表 错误:未找到探针 我也在一家大公司工作,其他更新了操作系统的人也遇到了同样的问题,不得不采取同样的措施。 有没有人知道更好的解决方法? Re: Mac OS Tahoe update LinkServer No Probes found 嗨@davidinsulet , 遗憾的是,这是预装在最新版本 MCUXpresso IDE 中的 LinkServer 版本的当前限制。也就是说,这一限制已被发现并报告给 IDE 团队,以便他们可以在未来的版本中修正 LinkServer 版本。 与此同时,您分享的帖子中描述的解决方法是解决此问题(特别是针对 MCUXpresso IDE)的最有效方法。 或者,您也可以推荐使用MCUXpresso for VS Code ,这是我们最新的开发平台,目前没有像 IDE 那样的限制。 由此造成的不便,敬请谅解。 BR, 埃德温。
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KW47 NBU programming and upgrade Hi: I want to know how to programming and upgrade of KW47 NBU.I hope the steps can be more detailed.  Thank you! Re: KW47 NBU programming and upgrade Hi: Thank you very much for your support. I can now update the nbu firmware through the method you provided.  I see that the method you provided doesn't include the way to update nbu through firmware?  For instance, if my device is launched on the market and I need to update the nbu version, how should I proceed?  Thank you! Re: KW47 NBU programming and upgrade Hello, hope you are doing well. You can refer to AN14796 Migration Guide from the KW45 to the KW47, section 6.2 "Load NBU firmware in KW47". In this document you will find several methods to update the NBU for KW47 (the steps are demonstrated using the KW47-EVK), including blhost, the Secure Provisioning Tool and LinkServer, you can use whichever approach works best for your development. The detailed steps for each method are included as well. Hope this helps! If you have any further question, please let me know. Best regards, Ana Sofia. Re: KW47 NBU programming and upgrade Hello, The ROM Bootloader has a firmware update feature that can be used for updating main flash as well as radio flash firmware. For in-field NBU updates, the workflow typically follows this sequence: the application stores the update image and writes the corresponding metadata into the User IFR0 OTACFG region, then triggers a system reset so the ROM bootloader can take over and perform the radio firmware update. More information is available in the KW47 Security Reference Manual sections 4.2.6 “Firmware update feature” and 4.2.2.3 Over-the-air (OTA) update configuration. Best regards, Ana Sofia.
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S32G274A 实现SHA256+RSA2048算法 Hello NXP Support Team, I am currently evaluating HSE on the S32G274A platform and would appreciate some guidance regarding the recommended implementation path. Current environment: * Device: S32G274A * Core: Cortex-M7 * IDE: S32 Design Studio 3.6 * HSE package: HSE_DEMOAPP_S32G2XX_0_1_0_16 * HSE firmware: HSE_FW_S32G2XX_0_1_0_16 Current progress: * I am following AN14070 ("How to Run HSE Demo Application on Cortex-M7 Core of S32G2"). * The HSE demo project can be imported and compiled successfully. * However, when opening the IVT View, S32DS reports an exception and the IVT view cannot be created: com.nxp.swtools.ivt.views.IVTView (I can provide the complete error log if needed.) Project objective: Currently, our bootloader implements software-based secure boot: 1. Calculate SHA-256 of the application image. 2. Verify RSA-2048 signature using a public key stored in flash. 3. Boot the application only if verification succeeds. We would like to migrate this implementation to HSE-based services on Cortex-M7. Questions: 1. Is AN14070 still the recommended starting point for HSE evaluation on S32G274A with S32DS 3.6? 2. Is the IVT View mandatory for evaluating HSE services such as: * SHA-256 * AES * RSA signature verification Or is it only required for generating the blob image and installing HSE firmware? 3. Once HSE firmware is installed, is there any reference example demonstrating: * SHA-256 calculation through HSE * RSA-2048 signature verification through HSE * Public key import into HSE key catalog 4. Are there any application notes, training materials, or demo projects that demonstrate migrating a software-based secure boot implementation to HSE services on Cortex-M7? 5. For a bootloader that currently performs SHA-256 + RSA2048 verification before jumping to the application, what is the recommended migration path using HSE? Any guidance, reference projects, or recommended documentation would be greatly appreciated. Best regards, Re: S32G274A 实现SHA256+RSA2048算法 我按照步骤操作到3. The IVTView, shown in the following figure, displays the blocks DCD, HSE, Application bootloader, Boot configuration and Automatic Align that are relevant for the generation of the blob image   我的S32 Design Studio for S32 Platform 3.6.0打不开IVT VIEW 报错:Could not create the view: com.nxp.swtools.ivt.views.IVTView   java.lang.Exception at org.eclipse.ui.internal.ViewReference.createErrorPart(ViewReference.java:115) at org.eclipse.ui.internal.ViewReference.createPart(ViewReference.java:101) at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.createPart(CompatibilityPart.java:304) at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.create(CompatibilityPart.java:342) at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method) at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77) at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) at java.base/java.lang.reflect.Method.invoke(Method.java:568) at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:58) at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:976) at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:938) at org.eclipse.e4.core.internal.di.InjectorImpl.internalInject(InjectorImpl.java:138) at org.eclipse.e4.core.internal.di.InjectorImpl.internalMake(InjectorImpl.java:385) at org.eclipse.e4.core.internal.di.InjectorImpl.make(InjectorImpl.java:311) Re: S32G274A 实现SHA256+RSA2048算法 Hi,tom9 Thank you for contacting us. The AN14070 remains a valid starting point for Cortex‑M7 evaluation, but it is recommended to use it together with the HSE Demo App package and HSE FW reference documentation. You can share detail error information with me in your testing. Regarding the application of secure boot on the S32G, you can try to refer to the following content: S32G_Secure_boot chinese/english version. At present, there are no specific documents directly meet your requirements. I will at the internal channels to help you in checking. I will reply to you if I have the results. BR Joey Re: S32G274A 实现SHA256+RSA2048算法 Hi,tom9 Thank you for your reply. The issue should be related the S32DS version. Refer to the HSE_DEMOAPP_S32G2XX_0_1_0_16_ReadMe.pdf, please try to use this recommended version. BR Joey Re: S32G274A 实现SHA256+RSA2048算法 I've finished creating the blob and burned it, but I can't see any print information on the serial port, and Trace32 can't load it either. Where should I start troubleshooting? Please take a look as soon as possible. Re: S32G274A 实现SHA256+RSA2048算法 Hi, tom9 1. Based on AN14070, the blob is created and flashed. It then boots via QSPI to load the HSE firmware and start the M7_0. After QSPI boot, you can try using Trace32 to connect to the M7_0 and check the SRAM contents to see if the app has been loaded to the correct address. 2. Load the HSE demo .elf file only after the application starts normally. Then proceed to the next step in the process, moving to SRAM. BR Joey Re: S32G274A 实现SHA256+RSA2048算法 Your answers never meet my expectations. I can now print information normally, as shown below: HSE FW Version: 0.1.0_1.0.9 HSE FW Image: Pink HSE FW up and running! Status: HSE_STATUS_RNG_INIT_OK HSE_STATUS_INIT_OK HSE_STATUS_CUST_SUPER_USER The program got stuck here and couldn't proceed. After commenting out `DEBUG_LOOP(gZero);`, it was found that it was stuck in `HSE_Config();`. /* Backup primary image */ ASSERT(FLASH_OP_OK == Flash_WriteData_FromFlash(IVT.pSysImage_bck, The code `ITV.pSysImage, MAX_SYS_IMG_SIZE)` gets stuck here. Subsequent code such as `HSE_Aes_Example` also fails to execute. Re: S32G274A 实现SHA256+RSA2048算法 Hi, tom9 Our support system has received your questions. Your request involves many issues, and our internal experts are already providing support and responses. BR Joey
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S32G274A 实现 SHA256+RSA2048 算法 NXP 支持团队您好, 我目前正在 S32G274A 平台上评估 HSE,希望能获得一些关于推荐实施路径的指导。 当前环境: * 设备:S32G274A * 内核:Cortex-M7 * IDE:S32 Design Studio 3.6 * HSE 封装:HSE_DEMO APP_S32G2XX_0_1_0_16 * HSE 固件:H SE_FW_S32G2XX_0_0_16 当前进展: * 我正在参考 AN14070("如何在 S32G2 的 Cortex-M7 核心上运行 HSE 演示应用程序" )。 * HSE 演示项目可以成功导入并编译。 * 然而,在打开 IVT 视图时,S32DS 报告了一个异常,导致无法创建 IVT 视图: com.nxp.swtools.ivt.views.IVTView (如有需要,我可以提供完整的错误日志。) 项目目标: 目前,我们的引导加载程序实现了基于软件的安全启动: 1。计算应用程序映像的 安全散列算法\(SHA\)-256。 2。使用存储在闪存中的公钥验证 RSA-2048 签名。 3.仅在验证成功时启动应用程序。 我们希望将此实现迁移到基于 Cortex-M7 的 HSE 服务上。 问题: 1. 在使用 S32DS 3.6 进行 S32G274A 的 HSE 评估时,AN14070 是否仍是推荐的起点? 2. 评估HSE服务(例如:)时,是否必须使用IVT View? * SHA-256 * AES * RSA 签名验证 还是说这仅用于生成 Blob 映像和安装 HSE 固件? 3.安装 HSE 固件后,是否有任何参考示例演示: * 通过 HSE 计算安全散列算法 (SHA)-256 * 通过 HSE 进行 RSA-2048 签名验证 * 公钥导入 HSE 密钥目录 4。是否有任何应用笔记、培训材料或演示项目可以演示将基于软件的安全启动实现迁移到 Cortex-M7 上的 HSE 服务? 5。对于当前在跳转到应用程序之前执行 安全散列算法(SHA)-256 + RSA2048 验证的引导加载程序,建议使用 HSE 的迁移路径是什么? 任何指导、参考项目或推荐的文档将不胜感激。 顺祝商祺! Re: S32G274A 实现SHA256+RSA2048算法 我按照步骤操作到了第3步。IVTView(如下图所示)显示了与生成 blob 映像 MINYS32 Design Studio for S32 平台 3.6.0打不开IVT 相关的方块 DCD、HSE、应用程序引导加载程序、启动 配置和自动对齐模块VIEW 报错:无法创建视图:com.nxp.swtools.ivt.views.IVTView java.lang. 异常,位于 org.eclipse.ui.internal.ViewReference.createErrorPart(ViewReference.java:115) 异常,位于 org.eclipse.ui.internal.ViewReference.createPart(ViewReference.java:101) 异常,位于 org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.createPart(CompatibilityPart.java:304) 在 org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.create(CompatibilityPart.java:342) 在 java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method) 位于 java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77) 位于 java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) 在 java.base/java.lang.reflect.Method.invoke(Method.java:568) 位于 org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:58) 在 org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:976) 在 org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:938) 在 org.eclipse.e4.core.internal.di.InjectorImpl.internalInject(InjectorImpl.java:138) 在 org.eclipse.e4.core.internal.di.InjectorImpl.internalMake(InjectorImpl.java:385) 位于 org.eclipse.e4.core.internal.di.InjectorImpl.make(InjectorImpl.java:311) Re: S32G274A 实现SHA256+RSA2048算法 你好,tom9 感谢您的联系。 AN14070 仍然是 Cortex-M7 评估的有效起点,但建议将其与 HSE 演示应用程序包和 HSE 固件参考文档一起使用。您可以在测试过程中向我反馈详细的错误信息。 关于安全启动在S32G上的应用,你可以尝试参考以下内容: S32G_Secure_boot 中文/英文版本。 目前,尚无任何文件能直接满足您的要求。我会通过内部渠道协助您进行核查。如果我拿到结果了,我会回复你的。 BR 乔伊 Re: S32G274A 实现SHA256+RSA2048算法 你好,tom9 感谢您的回复。 该问题可能与 S32DS 版本有关。请参阅 HSE_DEMOAPP_S32G2XX_0_1_0_16_ReadMe.pdf,请尽量使用此推荐版本。 BR 乔伊 Re: S32G274A 实现SHA256+RSA2048算法 我现在blob制作完成了,烧录进去后,串口看不到打印信息,trace32也无法加载,该从哪方面开始查呢?麻烦尽快给我看下 Re: S32G274A 实现SHA256+RSA2048算法 Hi,tom9 1.根据AN14070的内容,blob制作完成,烧写后通过QSPI启动,加载HSE相关固件和启动M7_0。QSPI启动后,你可以尝试trace32链接M7_0,检查一下SRAM的内容,看APP是否已经加载到了正确的地址。 2.能够正常启动后再加载HSE demo .elf 到 SRAM,再进行下一步操作。 BR Joey Re: S32G274A 实现SHA256+RSA2048算法 你的回答总是达不到我的预期,我现在已经可以正常打印信息了,打印这些如下: HSE FW Version: 0.1.0_1.0.9 HSE FW Image: Pink HSE FW up and running! Status: HSE_STATUS_RNG_INIT_OK HSE_STATUS_INIT_OK HSE_STATUS_CUST_SUPER_USER    卡在这里不能往后运行了,程序DEBUG_LOOP(gZero);注释之后,发现是卡在HSE_Config();中了,/* Backup primary image */ ASSERT(FLASH_OP_OK == Flash_WriteData_FromFlash(IVT.pSysImage_bck, IVT.pSysImage, MAX_SYS_IMG_SIZE));  卡在这里了。后面HSE_Aes_Example等也都不能执行 Re: S32G274A 实现SHA256+RSA2048算法 Hi,tom9 我们支持系统已经收到了相关的问题,您们的需求涉及的问题较多,内部专家已经在支持和回复。 BR Joey
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LPI2C 从机位错误问题 我使用的是S32K146,手册上说当从设备发送1但总线为0时会触发位错误。然而,在实际测试中,当从设备发送0但总线为1时也会触发位错误。我想知道这种现象是否正确? Re: An issue regarding slave bit errors in LPI2C 嗨@GXY , 是的,没错。当从机驱动 SDA 时,位错误标志会被触发,但采样结果却不同。 值比预期值大,不一定只在发送 1 而读取 0 时才如此。 我的猜测是,寄存器描述只是给出了一个位错误标志置位时的示例。 此致, 朱利安
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PCA9959 异常行为 我实现了一个电路,其中我使用一个控制器(MCU1)向 PCA9959 写入数据,然后使用 SN74CBTLV3257 多路复用器切换 SPI 总线,并使用第二个控制器(MCU2)读取这些值。MCU 之间不进行通信,但实现了轮流进行读写操作的仲裁机制。 只用 MCU1 写入数据而不切换开关时,一切正常。当我在 MCU1 和 MCU2 之间来回切换时,就会出现问题。 在这种情况下,LED驱动器会随机打开/关闭随机排列的LED。奇怪的是,当我使用 MCU1 写入值然后再读取时,寄存器内容似乎没问题。 有什么提示吗?未发现勘误。 开关上的信号: - SDI - 时钟 - SDO - nCS 来自MCU1的其他信号: - nEN - nRESET 非常感谢您的帮助!PCA9959
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How to Utilize VIT Voice Command Results from DSP in CM33 Hello, I am working with Voice Intelligent Technology (VIT) on the MIMXRT700 EVK using the "mimxrt700evk_dsp_xaf_record_cm33_core0" reference example. The VIT voice commands are being recognized on the DSP, and I would like to use the recognized command results in my CM33 application. Could you please let me know how the VIT results can be accessed from the CM33 core?  If there are any reference examples or documentation that explain the communication flow between the DSP and CM33 cores, please share them. Thanks Re: How to Utilize VIT Voice Command Results from DSP in CM33 Hi @arshtg , We have sdk demo on how to establish communication between CM core and DSP core, please kindly refer to https://github.com/nxp-mcuxpresso/mcuxsdk-examples/tree/release/26.06.00-pvw2/multicore_examples/rpmsg_lite_pingpong_dsp for details. Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------
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iMx95 processor frequency and turning off peripherals We would like to know how can we control the power consumption on the iMX95 chip from Yocto Linux. This will be to turn off peripherals we are not using in our application (like SAI3, ENET2, WIFI and so on...), and also by turning down the frequency and voltage of the various processors (like A55, M33 and NPU at a lower speed, and the M7 turned off altogether). I am not used to developing in Linux, but come from a background of embedded MCUs, like the MCX-N94x or the MIMXRT700 series, where we would use an RTOS and directly turn down PMIC voltages, set lower frequency clocks, and turning off peripherals by turning off their clocks, and so on. I would like to know how this is done in Linux, and if we delete a device from the DTS file, does Linux then turn off the peripheral? I also see that we can turn down the frequency of the A55s with the "cpufreq-set" command, but how do we control the frequency of all the other processors? Re: iMx95 processor frequency and turning off peripherals Hi @min-eta, That it is possible using the iMX95-EVK board and we have the AN14449 where we expose some use cases and the power consumption in each use case. But from now this information is shared only with registered customers with NDA. Re: iMx95 processor frequency and turning off peripherals We are interested in measure energy consumption in the chip when we are running ML with eIQ. So we would measure the currents in the VDD_ARM and VDD_SOC power domains, while the components that we need are running (A55s, M7, M33, NPU, GPU depending on if we are running on the CPU and/or NPU and/or GPU, as needed). Ideally we would turn off anything else in these power domains that we don't need, like the VPU, Camera controller, ISP, etc. Also, we would like to test the chip in the three power modes: low drive (0.8V), nominal drive (0.85V) and over drive (0.9V). At each mode, we would turn all the processor frequencies to their highest available at the given drive mode (like at 0.8V, A55=900 MHz, M7=500MHz, etc). Re: iMx95 processor frequency and turning off peripherals Hi @min-eta, Thank you for contacting NXP Support. On the i.MX95 platform, the System Manager is responsible for managing clocks and peripherals. When you use Linux commands to reduce the frequency in the background, the system interacts with the System Manager to adjust the core frequencies and clocks accordingly. Could you please provide more details about what you are trying to accomplish? This will help us guide you more effectively. The i.MX95 processor offers extensive configuration options because it is designed for safety- and security-critical applications. If you are not familiar with the MPU architecture and its functionalities, you might find it easier to work with a simpler MPU such as the i.MX93 or i.MX8MM, which are better suited for less complex use cases. Best Regards! Chavira Re: iMx95 processor frequency and turning off peripherals Hi @min-eta, We would like to do the same thing, and I wonder if you have succeeded to lower the power consumption and also swich between different power modes? /Per
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LPC55S05-EVKのデフォルトクロック設定 みなさんこんにちは、 私はLPC55シリーズを使い始めたばかりで、現在はLPC55S06-EVKを使用しています。私は、LED D4を点滅させるだけの非常にシンプルなベアメタルプロジェクトを持っています。 混乱しているのは、クロック設定コードがないのにMCUが正常に起動して動作していることです。SystemInit() または ResetISR() のいずれかにデフォルトのクロック設定があるはずだと思っていたのですが、そこには何もありませんでした。 ResetISR()の最初の命令でMCUを停止すると、クロックレジスタはすでに設定されています: MAINCLKSELA = 3 MAINCLKSELB = 0 AHBCLKDIV = 1 しかし、ユーザーマニュアルによると、MAINCLKSELAとAHBCLKDIVのリセット値はどちらも0です。 どうしてそんなことが可能なのか?コードの実行開始前に、これらのレジスタはどこで設定されているのでしょうか? よろしくお願いします、 ニコライ LPC55xx
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Sampling issue while streaming for Bayer sensor in iMX95 FRDM Hi Team, We are currently bringing up a Bayer sensor in IMX95 FRDM kit. We initially verified the stream with OS08A20 (reference camera from NXP) we were able to stream. Based on the driver we bringup a driver to support our sensor. It probes fine and media nodes gets generated properly. The media linking is proper which we verified with the media architecture of OS08A20.  We have attached the dmesg log below. Currently we configured the sensor in 8 bit mode (ar0234 sensor) . Current data rate is 800 MBPS per lane .  Data will be out in 4 lane for the sensor . We are able to probe and register. cam -l [0:08:06.049058684] [858]  INFO Camera camera_manager.cpp:340 libcamera v0.0.0+6489-lf-6.18.2-1.0.0 [0:08:06.155690529] [859]  INFO MediaPipeline media_pipeline.cpp:240 Found pipeline: [ar0830 3-0042|0] -> [0|csidev-4ad30000.csi|1] -> [0|4ac10000.syscon:formatter@20|1] -> [2|crossbar] [0:08:06.156726940] [859]  WARN CameraSensorProperties camera_sensor_properties.cpp:586 No static properties available for 'ar0830' [0:08:06.156904446] [859]  WARN CameraSensorProperties camera_sensor_properties.cpp:588 Please consider updating the camera sensor properties database [0:08:06.157054248] [859]  INFO Camera camera_manager.cpp:223 Adding camera '/base/soc/bus@42000000/i2c@42540000/ar0234_mipi@42' for pipeline handler imx8-isi Available cameras: 1: External camera 'ar0234' (/base/soc/bus@42000000/i2c@42540000/ar0234_mipi@42) our camera has been successfully detected , as mentioned above  v4l2-ctl -d 0 -v width=1920,height=1200,pixelformat='GRBG'  --stream-mmap  --verbose VIDIOC_QUERYCAP: ok VIDIOC_G_FMT: ok VIDIOC_S_FMT: ok Format Video Capture Multiplanar:   Width/Height      : 1920/1200   Pixel Format      : 'GRBG' (8-bit Bayer GRGR/BGBG)   Field             : None   Number of planes  : 1   Flags             :    Colorspace        : sRGB   Transfer Function : sRGB   YCbCr/HSV Encoding: ITU-R 601   Quantization      : Limited Range   Plane 0           :      Bytes per Line : 1920      Size Image     : 2304000     VIDIOC_REQBUFS returned 0 (Success)     VIDIOC_CREATE_BUFS returned 0 (Success)     VIDIOC_QUERYBUF returned 0 (Success)     VIDIOC_QUERYBUF returned 0 (Success)     VIDIOC_QUERYBUF returned 0 (Success)     VIDIOC_QUERYBUF returned 0 (Success)     VIDIOC_G_FMT returned 0 (Success)     VIDIOC_QBUF returned 0 (Success)     VIDIOC_QBUF returned 0 (Success)     VIDIOC_QBUF returned 0 (Success)     VIDIOC_QBUF returned 0 (Success)     VIDIOC_STREAMON returned 0 (Success)   We are able to get frames from the camera sensor which we probed with the DSO and verified but the platform is unable to sample it properly. No error comes in the dmesg. Have we missed anything else from the sensor configuration perspective? Also, do the data rate or pixel clock values need to be communicated to the platform through the Device Tree? Specifically, should the following D-PHY parameters be configured in the Device Tree?   cfg-clk-range = <28>; hs-clk-range = <0x2b>;   If these parameters are required, could you clarify on what basis the cfg-clk-range and hs-clk-range values are selected? Are these values derived from the MIPI CSI-2 lane data rate, sensor output resolution, frame rate, or pixel clock? Additionally, what data-rate or pixel-clock range corresponds to the values 28 and 0x2b? Is there a reference table or formula that should be used to determine the correct settings for a given sensor configuration? DMESG LOG [ 104.760033] camera-mipi-clk = 800MHz [ 115.837690] ar0234 3-0042: MIPI Clock = 800, MIPI Lanes = 4 [ 115.837737] ar0234 3-0042: supply avdd not found, using dummy regulator [ 115.837911] ar0234 3-0042: supply dovdd not found, using dummy regulator [ 115.837955] ar0234 3-0042: supply dvdd not found, using dummy regulator [ 115.988087] Current Firmware Version - (11eONO25V6XXX011106014eceGCORAL3) [ 115.988115] Current Firmware Version - (11eONO25V6XXX011106014eceGCORAL3) [ 115.989053] priv->mipi_lane_config is 4 [ 120.297214] SENSOR ID=0x0a56 [ 120.297245] mcu_isp_init [ 125.401238] Detected ar0234 sensor [ 125.453854] ar0234_propagate_fmt is called [ 125.463674] ar0234_propagate_fmt is called [ 125.463959] entering the enum mbus code [ 125.463975] code is 12290 [ 125.463982] entering the enum mbus code [ 125.463989] entering the ar0234_enum_frame_sizes functions [ 125.463995] entering the ar0234_enum_frame_sizes functions [ 125.463999] entering the ar0234_enum_frame_sizes functions [ 125.464004] entering the ar0234_enum_frame_sizes functions [ 125.464033] inside the ar0234_get_selection functions [ 125.464041] inside the ar0234_get_selection functions [ 125.464045] inside the ar0234_get_selection functions [ 126.637118] ar0234_propagate_fmt is called [ 126.637658] entering the enum mbus code [ 126.637681] code is 12290 [ 126.637702] entering the enum mbus code [ 126.637719] entering the ar0234_enum_frame_sizes functions [ 126.637736] entering the ar0234_enum_frame_sizes functions [ 126.637751] entering the ar0234_enum_frame_sizes functions [ 126.637765] entering the ar0234_enum_frame_sizes functions [ 126.637856] inside the ar0234_get_selection functions [ 126.637877] inside the ar0234_get_selection functions [ 126.637892] inside the ar0234_get_selection functions [ 204.157151] audit: type=1006 audit(1782310053.402:28): pid=805 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=4 res=1 [ 204.157191] audit: type=1300 audit(1782310053.402:28): arch=c00000b7 syscall=64 success=yes exit=1 a0=a a1=ffffc191b2d0 a2=1 a3=0 items=0 ppid=1 pid=805 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=4 comm="sshd-session" exe="/usr/libexec/sshd-session" key=(null) [ 204.157211] audit: type=1327 audit(1782310053.402:28): proctitle=737368642D73657373696F6E3A20726F6F74205B707269765D [ 206.826792] ar0234_propagate_fmt is called [ 206.826975] entering the enum mbus code [ 206.826986] code is 12290 [ 206.826994] entering the enum mbus code [ 206.827000] entering the ar0234_enum_frame_sizes functions [ 206.827006] entering the ar0234_enum_frame_sizes functions [ 206.827010] entering the ar0234_enum_frame_sizes functions [ 206.827014] entering the ar0234_enum_frame_sizes functions [ 206.827057] inside the ar0234_get_selection functions [ 206.827065] inside the ar0234_get_selection functions [ 206.827070] inside the ar0234_get_selection functions [ 224.637904] ar0234_propagate_fmt is called [ 224.676405] ar0234_propagate_fmt is called [ 224.676442] entering ar0234_set_fmt [ 224.676447] inside the set format loop if condition [ 224.676451] ar0234->mcu_cam_frmfmt[mode].size.width is 1920 [ 224.676456] ar0234_set_fmt: setting resolution width=1920 height=1200, mode=0 [ 224.680462] priv->mcu_cam_frmfmt[mode].size.width is 1920 [ 224.680476] mc_data[8] = 0x07 (7) [ 224.680480] mc_data[9] = 0x80 (128) [ 224.680484] mc_data[10] = 0x04 (4) [ 224.680487] mc_data[11] = 0xb0 (176) [ 228.270636] ar0234_propagate_fmt is called [ 228.270815] entering the enum mbus code [ 228.270823] code is 12290 [ 228.270832] entering the enum mbus code [ 228.270838] entering the ar0234_enum_frame_sizes functions [ 228.270843] entering the ar0234_enum_frame_sizes functions [ 228.270848] entering the ar0234_enum_frame_sizes functions [ 228.270912] entering the ar0234_enum_frame_sizes functions [ 228.270958] inside the ar0234_get_selection functions [ 228.270965] inside the ar0234_get_selection functions [ 228.270970] inside the ar0234_get_selection functions [ 237.329660] dwc-mipi-csi2 4ad30000.csi: Remote sub-device on pad 1 should implement .get_frame_desc! Forcing VC = 0 and DT = 2a [ 487.004807] ar0234_propagate_fmt is called [ 487.004984] entering the enum mbus code [ 487.005053] code is 12290 [ 487.005065] entering the enum mbus code [ 487.005073] entering the ar0234_enum_frame_sizes functions [ 487.005079] entering the ar0234_enum_frame_sizes functions [ 487.005083] entering the ar0234_enum_frame_sizes functions [ 487.005087] entering the ar0234_enum_frame_sizes functions [ 487.005138] inside the ar0234_get_selection functions [ 487.005146] inside the ar0234_get_selection functions [ 487.005150] inside the ar0234_get_selection functions [ 695.743591] audit: type=1006 audit(1782310544.949:29): pid=869 uid=0 old-auid=4294967295 auid=0 tty=(none) old-ses=4294967295 ses=5 res=1 [ 695.743649] audit: type=1300 audit(1782310544.949:29): arch=c00000b7 syscall=64 success=yes exit=1 a0=a a1=ffffef74ca20 a2=1 a3=0 items=0 ppid=1 pid=869 auid=0 uid=0 gid=0 euid=0 suid=0 fsuid=0 egid=0 sgid=0 fsgid=0 tty=(none) ses=5 comm="sshd-session" exe="/usr/libexec/sshd-session" key=(null) [ 695.743685] audit: type=1327 audit(1782310544.949:29): proctitle=737368642D73657373696F6E3A20726F6F74205B707269765D
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FS32K144UAT0VLLT(RESET)のピン97(PTA5)で三角波レベルが観測されました。 マネージャー: FS32K144UAT0VLLT回路は、5VDC電源、20MHz外部水晶発振器、および10pF整合コンデンサを使用します。外部水晶発振器が発振を開始せず、ホストコンピュータはソフトウェアを使用してこのチップに正常に接続できません。 この32K144UAチップの97番ピンでPTA5(リセット)レベルを測定したところ、周波数1280Hz、振幅3.3Vp-pの三角波が検出された。 下の画像に示すように、原因の分析にご協力をお願いします。LDO電源チップは5Vで正常に動作しているのに、なぜ水晶発振器が発振しないのでしょうか?リセットピンが三角波を生成するのはなぜでしょうか?はんだ付け不良はどこが原因でしょうか?よろしくお願いいたします。 Re: FS32K144UAT0VLLT第97脚PTA5(RESET)出现三角波电平 こんにちは リセットピンは現在コンデンサに接続されているため、三角波が表示されています。まずコンデンサを取り外してリセットピンの波形を確認するか、 S32K1xxシリーズMCUアプリケーションガイドのセクション7「S32K1xxシリーズMCUにおけるロックアップリセットの原因分析と復旧方法」を参照して、具体的な状況を確認してください。 リセットピンは定期的にローレベルに引き下げられ、プログラムが実行されないため、水晶発振器はプログラム内のイネーブルビットに従って発振を開始できません。 以前VDDが3.3Vで動作していたチップで、VREFHが5Vで動作している場合は、そのチップをテストしないでください。チップを再はんだ付けしてから、デバッガを使用してプログラムをダウンロードすることをお勧めします。 よろしくお願いします、 ロビン 回复: FS32K144UAT0VLLT第97脚PTA5(RESET)出现三角波电平 先生方へ: 補充する: 上記のFS32K144UAT0VLLTのリセット回路は、リセットピンに10KΩの抵抗を接続して+5Vにプルアップし、100nFのコンデンサをGNDに接続しています。ありがとうございました! Re: FS32K144UAT0VLLT第97脚PTA5(RESET)出现三角波电平 マネージャー: リセット回路からコンデンサを取り外すと、図に示すようにパルスが発生します。 1. 「 7. S32K1xxシリーズMCUチップのロックアップの解析と復旧方法」を参照。J-llnkはコンピュータに正常に接続できませんが、ST-linkは接続できますが、ソフトウェアがそれをサポートしていません。 2. リセット回路がJ-Linkに正しく接続できません。接続時にリセット回路にコンデンサをはんだ付けする必要があるのでしょうか?現在、リセット回路には5Vへの10kΩプルアップ抵抗、5V電源、GNDに接続された100nFコンデンサがありますが、それでもJ-Linkに接続できません。どのような対策を講じるべきでしょうか? 3. FS32K144UAT0VLLTは新品で、既に2個交換済みです。新しいチップでも暗号化の問題が発生するのはなぜですか? ありがとう! Re: FS32K144UAT0VLLT第97脚PTA5(RESET)出现三角波电平 リセットピンの波形は以下と一致しているようです。 ② RESETピンは周期的なリセットパルス信号を出力します。 a. リセット信号の周期が約118µsで、ハイレベル時間が約660nsの場合、それは方形波信号です。 SWD/JTAGデバッグインターフェースを介して一括消去コマンドを実行することで、MCUの暗号化を解除し、データを復元することができます。 この記事に記載されているBaidu Cloud Driveのリンクにあるスクリプトを使用することをお勧めします。
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PT2000 仅用作低侧驱动器 你好, 我使用 PT2000 驱动一个传统的喷油器(12 欧姆),使用一个 PT2000 的一个通道的高侧和低侧输出(喷油器的两根线都连接到 PT2000),一切都按预期工作。 是否可以将喷油器正极线连接到外部持续 +12V 电源,然后仅通过驱动一个低压侧来打开喷油器?我尝试了不修改微代码的这个解决方案,但它不起作用,我需要对微核进行哪些修改才能使其适应这种拓扑结构?更一般地说,我需要以低侧模式驱动电磁阀,但要控制电流,这有可能吗? 感谢您的支持! 此致
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MCXA174:J-FLASH device list has no MCXA174/3 DEVICE, cannot erase\read\program, how to fix it? I am currently using the MCXA174 chip and need to program code with J-Link. However, when creating a project in J-Flash and reaching the device selection step, there is no available option for the MCXA174/3 chip. I have tried selecting MCXA15X and MCXA344 as alternative devices, but none of them worked. What should I do? Thank you. SEGGER JLINK Software version V9.52 MCXA Re: MCXA174:J-FLASH device list has no MCXA174/3 DEVICE, cannot erase\read\program, how to fix it? I only have a j-link, which is a general-purpose burner. Is there any other way to use it? Can NXP provide the necessary files to add the device, such as .xml, .jlinkscript, and .FLM files? If not, it would be too unfriendly to users. Re: MCXA174:J-FLASH device list has no MCXA174/3 DEVICE, cannot erase\read\program, how to fix it? Hello NXP does not control for when third-party tool vendors add support for specific devices to their development environments; As of the release notes for most recent versions on the tool page, the MCXA174/3 is not listed yet. If you want to program the MCXA174, you could use debuggers from NXP as the MCU Link. Let me know if you need more information on this Best Regards Re: MCXA174:J-FLASH device list has no MCXA174/3 DEVICE, cannot erase\read\program, how to fix it? Hello, I would recommend checking with Segger support to verify a launching version for the support on this device. Additional, I found some links from Segger page that could be helpful for you. J-Link Device Support Kit - SEGGER Knowledge Base Has a section on adding new devices NXP MCX A - SEGGER Knowledge Base has the MCXA family information including MCXA174 Best Regards.
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NXPS32k144へのコード書き込み中に発生する問題 件名:S32K144 EVB - S32 Design Studio 3.5でのデバッグ中のPEmicro接続アシスタントエラー こんにちは、NXPサポートチームの皆さん、 私はS32 Design Studio 3.5を使ってS32K144評価ボード上のアプリケーションのデバッグ中に問題に直面しています。 環境: 基板:S32K144 EVB(必要に応じて、正確な基板部品番号を更新してください) IDE: S32 Design Studio 3.5 デバッグプローブ:搭載OpenSDA(PEmicro) オペレーティングシステム:Windows(バージョンを指定してください) 接続タイプ: OpenSDA USB 問題の説明: デバッグセッションを開始すると、PEmicro接続アシスタントに次のメッセージが表示されます。 「起動設定ダイアログで指定されたインターフェースハードウェアまたはターゲットへの接続中にエラーが発生しました。」 接続アシスタントはOpenSDAプローブを正しく検出します。 USB1上のOpenSDA 名前 = FDC46E50 しかし、デバッガはターゲットのMCUとの通信を確立できません。 観察結果: OpenSDAはPCによって正常に検出されました。 基板の電源LEDが点灯しています。 この問題はデバッグ起動時に発生します。 私は既に以下のことを試しました: デバッグを行う前に、リセットボタンを押してください。 USBケーブルを抜き差しする。 別のUSBケーブルを使用する。 別のノートPC/PCを使っています。 S32 Design Studioの再起動。 同じ問題が依然として続いている。 アプリケーション情報: アプリケーションは以下の通りです: Pins Toolによって生成されたピン構成。 SDKドライバ(PINS_DRV)。 RearWiperControl_Fnモデルコードを生成しました。 main() 関数内で実行されるサンプルコード: PINS_DRV_Init() リアワイパーコントロール_Fn_initialize() リアワイパーコントロール_Fn_step() 質問: ターゲット通信が失敗している間にOpenSDAが検出される原因は何でしょうか? S32DS 3.5と現在のOpenSDAファームウェアの間には、既知の問題はありますか? OpenSDAのファームウェアはアップデートまたは再フラッシュする必要があるでしょうか? S32K144で一括消去または「リセット状態での接続」を行うための推奨手順はありますか? S32K144 EVBには、デバッグのために確認すべきジャンパー設定はありますか? ピンの多重振用設定が間違っていると、プログラム後のSWD通信に干渉する可能性はありますか? 添付: PEmicro接続アシスタントのエラーダイアログのスクリーンショット。 この問題のトラブルシューティングに関するアドバイスをいただければ幸いです。 よろしくお願いします。 Re: Issue facing during flashing code on NXPS32k144 こんにちは、 @Shubham3 さん。 このアプリケーションや例をプログラムする前に、ボードは正しくデバッグされていましたか? アプリケーションがPins Tool / PORTレジスタでPTA4、PTC4、またはPTA5を再設定しているかを確認してください。これらのピンは、S32K144のSWD/リセットに関連しています。 もしそうなら、実際にデバッガの接続を妨げる可能性があります。同様の事例はすでにNXPコミュニティでも報告されています。可能な回復方法や追加の背景については、以下のスレッドを参照してください。 デバイスは安全です、消去から安全でない - NXPコミュニティ 解決済み:S32K144 - PORTA PIN5 CFGとRESET信号の競合 - NXPコミュニティ 解決:S32K118EVB2-Q048でPEmicroデバッガが使えない - NXPコミュニティ よろしくお願いいたします。 パベル Re: Issue facing during flashing code on NXPS32k144 以下の例のコードをフラッシュした後、問題が発生します ADC PALを使って、SWとHWでトリガーされた一連のコンバージョングループを行っています。LPUART上では、各コンバージョングループ実行の平均値を表示します。 その例のドキュメントは、S32 SDKの「Examples and Demos」セクションでご覧いただけます。(/doc/Start_Here.html)
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S32K396 RTD 5.0.0 FlexIO PWM – How is PWM Period Calculated from the "Period [ticks]" Parameter? Hello NXP Team, I am using S32K396 with RTD 5.0.0 and the FlexIO PWM driver. My configuration is: FLEXIO0_CLK = 160 MHz Clock Prescaler = FLEXIO_PWM_IP_CLK_DIV_16 Channel ID = CH_0 Pin ID = PIN_1 Generated configuration: const Flexio_Pwm_Ip_ChannelConfigType Flexio_Pwm_Ip_I0_Ch0 = { /* TimerId */ 0U, /* PinId */ 1U, #if (defined(FLEXIO_PWM_IP_HAS_PRESCALER) && (FLEXIO_PWM_IP_HAS_PRESCALER == STD_ON)) /* Prescaler */ FLEXIO_PWM_IP_CLK_DIV_16, #endif /* Period */ 400U, /* DutyCycle */ 0U, #if (defined(FLEXIO_PWM_IP_HAS_LOW_MODE) && (FLEXIO_PWM_IP_HAS_LOW_MODE == STD_ON)) /* Polarity */ FLEXIO_PWM_IP_ACTIVE_HIGH, #endif /* IrqMode */ FLEXIO_PWM_IP_IRQ_DISABLED, /* IPL callback */ { /* CbFunction */ NULL_PTR, /* CbParameter */ NULL_PTR }, /* HLD callback */ { /* CbFunction */ NULL_PTR, /* CbParameter */ 0 } };   I am trying to understand the exact relationship between: FLEXIO clock frequency Prescaler Period [ticks] Duty cycle [ticks] Output PWM frequency My measurements are: Period Duty Measured Frequency Measured Duty 200 100 20 kHz 50% 300 100 13.3 kHz 33.3% 400 100 27.7 kHz 69.4% 500 100 16.3 kHz 40% The first two measurements seem to indicate: Duty (%) = DutyTicks / PeriodTicks × 100 However, I am unable to derive the exact PWM frequency formula used internally by the FlexIO PWM RTD driver. Could you please clarify: What is the exact formula used by the FlexIO PWM driver to convert Period [ticks] into output PWM frequency? How is the TIMCMP register programmed from the configured Period value? Is there any maximum valid Period value (for example 255 counts due to FlexIO timer limitations)? How can I calculate the required Period value to obtain a desired PWM frequency (for example 10 kHz) when: FLEXIO0_CLK = 160 MHz Prescaler = 16 Is there any application note or reference document explaining the FlexIO PWM timing calculations? Any clarification on the internal timing equation would be greatly appreciated. Thank you. Re: S32K396 RTD 5.0.0 FlexIO PWM – How is PWM Period Calculated from the "Period [ticks]" Hi @Esakki, 1. Your formula is correct. 2. For Period = 200 and Duty = 100 ticks, in Dual 8-bit counters PWM high mode (TIMCTL[TIMOD]): TIMCMP = 0x00006363 High byte = 0x63 = 99 → decremented while the output is low Low byte = 0x63 = 99 → decremented while the output is high 3. Yes, the driver should prevent writing values greater than 256 to either byte when FLEXIO_PWM_IP_DEV_ERROR_DETECT = STD_ON. If this check is disabled, the field will overflow, which is likely the root cause of the issue you are observing. 4. Period in ticks − duty in ticks ≤ 256. It is not possible to achieve 10 kHz with the given input clock in this mode. You need to increase the prescaler. 5. Only the Reference Manual covers this. Regards, Daniel Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.     Re: S32K396 RTD 5.0.0 FlexIO PWM – How is PWM Period Calculated from the "Period [ticks]" Hello Daniel, Thank you for the explanation. I have one follow-up question regarding the Period calculation. From your explanation, I understand that in Dual 8-bit counters PWM high mode: TIMCMP[15:8] = Period - Duty - 1 TIMCMP[7:0] = Duty - 1 and that both fields are limited to 256 counts. Could you please clarify the exact formula used to calculate the output PWM frequency from: FlexIO input clock frequency Prescaler Period value For example, if: FlexIO clock = 160 MHz Prescaler = 256 Period = 63 ticks What should be the expected PWM frequency? Using the formula: PWM Frequency = FlexIO Clock / (Prescaler × Period) I would expect approximately 9.92 kHz. However, when measuring the PWM output, I observe approximately 3.9 kHz. Similarly, with: Prescaler = 16 Period = 200 I measure approximately 20 kHz, which corresponds to an effective PWM clock of about 64 MHz rather than 160 MHz. Could you please explain: The exact PWM frequency equation for FlexIO PWM Dual 8-bit mode. Whether any additional divider or timer scaling is applied internally by the FlexIO PWM driver. Which runtime register or clock source should be checked to determine the actual clock used by the PWM timer. Thank you for your help. Re: S32K396 RTD 5.0.0 FlexIO PWM – How is PWM Period Calculated from the "Period [ticks]" Hi @Esakki, You can derive the equation directly from the driver implementation — see Flexio_Pwm_Ip_UpdatePeriodDuty(): Flexio_Pwm_Ip_SetLowerValue(Base, Channel, (uint8)(DutyCycle - 1U)); Flexio_Pwm_Ip_SetUpperValue(Base, Channel, (uint8)(Period - DutyCycle - 1U)); So the mapping to TIMCMP is: Lower 8 bits = DutyCycle - 1 Upper 8 bits = Period - DutyCycle - 1 From Flexio_Pwm_Ip_GetPeriod(): Period = Upper + Lower + 2 Period = (DutyCycle - 1) + (Period - DutyCycle - 1) + 2 f_pwm = Input_FlexIO_CLK (prescalled) / Period Duty(%) = DutyCycle / Period × 100 Example (FLEXIO clock = 160 MHz, prescaler = 16 → 10 MHz timer clock): Period = 200 ticks -- f_pwm = 10 MHz / 200 = 50 kHz Regards, Daniel   Re: S32K396 RTD 5.0.0 FlexIO PWM – How is PWM Period Calculated from the "Period [ticks]" Hello Daniel, Thank you for the detailed explanation and the frequency formula. According to the formula: f_pwm = FlexIO_Input_Clock (after prescaler) / Period For my configuration: FlexIO Clock = 160 MHz Prescaler = 256 Period = 63 I would expect: f_pwm = 160 MHz / (256 × 63) = 9.92 kHz However, when measured on the oscilloscope, the PWM frequency is approximately 3.9 kHz. Similarly, with: Prescaler = 16 Period = 200 I measure approximately 20 kHz, whereas the formula predicts 50 kHz if the FlexIO clock is 160 MHz. Could you please advise: Is the FlexIO PWM driver using a clock source different from the configured FLEXIO0_CLK? Is there any additional divider or clock scaling applied internally? What is the recommended method to verify the actual runtime clock frequency used by the FlexIO PWM timer? I would like to understand why the measured PWM frequency does not match the frequency calculated using the configured 160 MHz FlexIO clock. Thank you for your support. Regards, Esakki
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在 RT1180-EVK 上使用 VS Code 调试 FreeRTOS 在 evkmimxrt1180_freertos_message_buffers_secondary_core 示例项目中,FreeRTOS 配置如下: #define configMAX_PRIORITIES 56 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 该应用程序可以在 IDE(MCUXpresso IDE)中正常调试。但是,在使用 VS Code 进行调试时,FreeRTOS 启动调度程序后调试器就会退出。 当执行到 vTaskStartScheduler() 中的以下代码时,调试会话终止: xNextTaskUnblockTime = portMAX_DELAY; xSchedulerRunning = pdTRUE; xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 初始化这些变量之后,在调度第一个任务之前,调试器会断开连接,调试会话结束。 您能帮我分别在IDE和VS Code中测试一下,并找到解决方案吗? MCXC Re: FreeRTOS Debugging in VS Code on RT1180-EVK 嗨@yanyanwang , 在功能域文件夹中构建项目后,您应该在该文件夹中找到主核心应用程序和辅助核心应用程序。 如果你点击这两个 .elf 文件的播放按钮对于每个文件,都会启动一个调试会话吗? 如果运行主核心直到它通过 MCMGR_StartCore 函数,是否可以暂停辅助核心的调试会话? 此致, 巴勃罗
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NXP Config Tools 26.06 for i.MX not loading saved configuration Hello, While evaluating the new version of the DDR configuration for the i.MX95, I came across what looks like a bug in the configuration tool. Here is exactly what I did, so the behavior can be reproduced: 1. Installed the Linux version of the tool. 2. Created a new configuration. 3. Selected processor MIMX9596xxxxN. 4. Changed the preset to "LPDDR4X EVK / FRDM 15x15 4000MTs Configuration". 5. Saved the configuration, then closed the tool. 6. Reopened the tool and loaded the saved configuration. At that point the DDR configuration is not displayed at all. At least the 26.03 version was starting with MCU unselected (selecting it manually solves the problem), now there is no way to solve the problem. Thank you very much for your help. Best regards, Emanuele Re: NXP Config Tools 26.06 for i.MX not loading saved configuration Also the windows version of the tool shows the same problem. Attached screenshots.
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REQUEST TO PROVIDE ME UART EAMPLE PROJECT FOR S32K311 USING S32 DS3.6.2 Hello, I am currently working on the S32K311 MCU using S32 Design Studio 3.6.2. Could you please provide me with a UART example project (basic transmit/receive demonstration) compatible with this setup? Having this reference will help me get started with communication on S32K311 and build further applications. Re: REQUEST TO PROVIDE ME UART EAMPLE PROJECT FOR S32K311 USING S32 DS3.6.2 Hello @Kaushal9511 , Thank you for the update. To help isolate the issue, I recommend performing a simple loopback test — connect the TX and RX pins together and send a character. If reception works in this configuration, the issue is likely external (e.g., wiring, terminal settings, or signal integrity). Best regards, Pavel Re: REQUEST TO PROVIDE ME UART EAMPLE PROJECT FOR S32K311 USING S32 DS3.6.2 Hello Pavel, Thank you for your detailed guidance on reusing the LpuartFlexio_Uart_Ip_Example_S32K344 project for the S32K311. I followed your steps and was able to successfully transmit data using LPUART. However, I am facing an issue with receiving data: Transmission works correctly and I can see the output on the terminal. Reception does not seem to work, and no data is being captured by the MCU. Could you please advise me on the correct configuration or additional steps required to enable UART reception on S32K311? Re: REQUEST TO PROVIDE ME UART EAMPLE PROJECT FOR S32K311 USING S32 DS3.6.2 Hello @Kaushal9511 , I'm assuming you're using S32K3 RTD 6.0.0. Unfortunately, there are no pre-existing UART examples specifically for S32K311, but you can easily create one by reusing an example from a similar device. Here's a step-by-step guide: Create a project from an existing example that uses the UART stack, e.g. LpuartFlexio_Uart_Ip_Example_S32K344 Open the Configuration Tool, resolve any issues, and build the project. Now, create a new application project for S32K311 (make sure to attach the RTD version). Open the Configuration Tool for the new project, resolve any issues, and click Update Code. Stay in the Peripherals tab. Go to File → Import → S32 Configuration Tools → Import Configuration (*.mex) Select the .mex file from the previous project, e.g your_workspace\LpuartFlexio_Uart_Ip_Example_S32K344\LpuartFlexio_Uart_Ip_Example.mex Choose "Import the configuration as a new one" Click Finish Some errors will appear - this is expected. In the Peripherals tab, resolve all issues (e.g. missing drivers -> Manage SDK Components). Click on the Pins tab. When prompted to switch the configuration to S32K311, click Yes. Adjust the Clocks to meet the S32K311 requirements (refer to the S32K3 Reference Manual for details). Click Update Code again. Return to the C/C++ editor. Copy the main.c file from the original example LpuartFlexio_Uart_Ip_Example_S32K344  into your new project. Comment out or remove the lines with Exit_Example and #include "check_example.h"   Build the project. This approach allows you to reuse existing examples even for devices that are not directly supported by preconfigured demos.  Best regards, Pavel Re: REQUEST TO PROVIDE ME UART EAMPLE PROJECT FOR S32K311 USING S32 DS3.6.2 I can't attach any SDK (RTD) version. 1. First, I selected the S32K348 MCU, which lacks RTD examples, as a new application project. 2. During the project creation process, I was unable to select an SDK at the section shown in the image above. 3. I also could not find a way to add one later, even after creating the project. How can I attach an RTD? Re: REQUEST TO PROVIDE ME UART EAMPLE PROJECT FOR S32K311 USING S32 DS3.6.2 Hello @Penta7 , You need to select correct GCC version based on S32K3 RTD Release Note. It has been discussed e.g. in this thread: [S32DS 3.6.7] S32K1xx RTD 3.0.0 not detected when creating new project Best regards, Pavel
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将FPGA连接到PCA9617A的B端口。 您好: 我的情况如下:MCU 连接到 PCA9617A 的 A 端口,FPGA(作为 I²C 设备)连接到 B 端口。 根据数据手册,端口 B 的电压偏置约为0.55 V。FPGA 的 VIL 规格为0.8 V。这样就只剩下250 mV 的裕量了。 当从MCU向FPGA传输大量数据时,这个裕量会造成问题吗?为了保证可靠运行,建议的VIL裕量是多少? 顺祝商祺! 马可 Re: Connect FPGA to port B of PCA9617A 你好 Marco_MJ 再会! 我认为你已经达到极限了;推荐范围是 >300mV,所以你使用 250mV 的范围存在很大的风险。 希望这些信息对您有所帮助,如果您还需要其他帮助,请告诉我。 祝你今天过得愉快,一切顺利。
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SPI (Slave) + DMA data reception error When the S32K144 SPI is configured in SLAVE mode and uses DMA, data misalignment occurs during data reception (e.g., the correct sequence should be 1, 2, 3, 4, 5, 6, but the actual received data is 3, 4, 5, 6, 1, 2, indicating a misalignment). Analysis of the communication data sequence using an oscilloscope shows it is normal, and the data received by the SPI during the first communication is also normal. The current communication method is that the master and slave microcontrollers periodically trigger SPI communication. Re: SPI(Slave )+DMA 数据接收异常 IDE:S32 Design Studio for ARM Version 2.2, custom board. Re: SPI(Slave )+DMA 数据接收异常 Hi @GLB  Which software and IDE you are using? Could you please share your code and configuration so I can try to reproduce the issue on my side? Also, are you working with a custom board or an evaluation board (EVB)? BR, VaneB Re: SPI(Slave )+DMA 数据接收异常 Hi @GLB  A possible reason for the observed receive data misalignment could be an incomplete synchronization between the LPSPI RX FIFO state and the DMA RX TCD state before starting a new transaction. The first received frame sequence is correct, but subsequent transfers could become shifted if the RX FIFO still contains pending data. You can try disabling DMA requests, clean the LPSPI FIFOs, clearing SPI and DMA status flags, and reloading the RX/TX DMA TCDs before initiating a new transfer. A similar approach is implemented in the Thread SPI slave DMA chip select restart; although it is not specific to the S32K144 device, it can serve as a useful reference. Additionally, the S32K1 SDK example lpspi_dma_s32k144 can also be used as a reference. Re: SPI(Slave )+DMA 数据接收异常 Hi @GLB  Timing variations can still lead to some misalignment. It could work well as long as both sides stay tightly synchronized. Re: SPI(Slave )+DMA 数据接收异常 The master sends data at a 10ms cycle, and the slave also triggers DMA to move data at a 10ms cycle. Is this communication method reasonable? Even if the FIFO is cleared before the slave DMA moves data, data misalignment is still possible, right? Re: SPI(Slave )+DMA 数据接收异常 I checked the S32K144 manual and found that the SPI only has receive and transmit interrupts, not chip select interrupts, and the DMA only has a transfer completion interrupt. I tried configuring the SPI receive interrupt, but the misalignment still occurs. It seems that SPI itself cannot solve this problem. I think an additional synchronization signal needs to be added between the master and slave to ensure the correctness of the SPI. Do you have any other suggestions? Thank you.
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