Hi team NXP!
From the spec of IMXRT700 it was said to be architected in the 3 domain of media, compute and sense domain, which each of the cores on chip would require their own separate image to run. But it seems that there are only very few documented usage of the EZH-V core.
I have read the application notes AN14614, AN14618 and AN14654, but there are still very few information regarding this core and it roles in graphical processing for RT700. It was said that it is used to implement the smartDMA engine, but in other MCX family MCU there are no mentioning of the existence of this core and the smartDMA can be directly used by the Arm CM33 core via the mcuxpresso sdk provided APIs.
So now I am extremely confused, can I still directly use the smartDMA on iMXRT700 directly or must I build the image for the EZH-V via LLVM as per AN14614 instruction? This seems quite counterintuitive though having to resort to RPMsg for IPC communication as supposed to be directly driven by the Cpu0.
On top of this, I am not aware of any actual demo or use case that has been provided by NXP that explicitly utilized this EZH-V core. I have also review the some of the source headers available, and only some very intuitive basic operations have been provided. May I know what is the usage of the EZH-V?
okay quick update, after taking a look of the smartDMA driver in the mainline Zephyr now I understand the situation.
The smartDMA has always been/planned as a standalone subsystem with its own core that could have the potential to run firmware on its own, but never have been actually presented as a fully standalone RISC-V core.
In the current existing example, the smartDMA has never really touched the custom firmware installation path and only used as a slightly special DMA IP.
So now the question should pivot to if I could still use the smartDMA in the old fashion; directly invoked via the CM33 instead of doing the complex IPC setup, as of time of writing, the smartDMA IP is yet to be exposed as a supported IP of the official maintained mimxrt700_evk.
Hi @mayliu1 ,
Thanks for the quick reply, so you mean the smartDMA is no longer coupled to the CM33 core and therefore must be used via the EZH-V core?
In NXP's other MCU family like MCX the smartDMA is coupled to the CM33 and can be directly invoked via APIs, there are application notes documenting such use cases AN14172, AN14916, and they do not involve building the standalone image for the RISC-V core.
So what is the current architecture on the i.MXRT700? All documents about EZH-V are very ambiguous and I am not aware of any existing demo or guides that have thoroughly covered the usage of EZH-V.
Has NXP revised the architecture of smartDMA so it is no longer part of the core CM33 system and grouped to the RISC-V companion core instead? Can I still invoke the smartDMA directly via the CM33?
Hi @TomC818 ，
Thank you so much for your interest in our products and for using our community.
According to AN14614 and the i.MX RT700 Reference Manual, my understanding is that the SmartDMA functionality on the i.MX RT700 is implemented through the EZH-V RISC-V core rather than as a conventional DMA peripheral such as eDMA.
In general, eDMA is still the preferred solution for standard memory transfer operations and can be configured directly by the CM33 core. However, SmartDMA-related processing, such as certain graphics/data post-processing or data format conversion tasks, is typically implemented by firmware running on the EZH-V core.
Based on AN14614, CPU0 is responsible for loading and booting the EZH-V firmware, after which the actual processing is performed by EZH-V. From this perspective, EZH-V behaves more like a programmable coprocessor than a traditional DMA engine.
Therefore, SmartDMA on RT700 is better viewed as a programmable processing engine running on the EZH-V core, rather than a traditional DMA peripheral directly driven by CM33 alone.
Wish it helps you
Best Regards
May
hey umm... if NXP didn't actually prepare or have any planned support for "With the assistance of the EZH-V, the Cortex-M33 cores can be freed to perform other tasks. While the EZH-V is executing the assigned task, the CM33 cores can execute other tasks in parallel." as per the reference manual described, I think I will be pursuiting a different option from ST or Infineon, considering the fact that RT700 documentations and examples are still extremely unpolished and all over the place. Support for most of the marketted unqiue features of this MCU are very sparse and few between. With such a the complex heterogeneous architecture, such little examples and guides are just abyssal.
On i.MX RT700, SmartDMA is not exposed in the same way as a conventional standalone DMA peripheral directly controlled by the CM33.
The SmartDMA-style capability is provided through the EZH-V engine, so the typical usage model is for the CM33 to load and start the EZH-V firmware, then coordinate with it as needed.
