I am using S32K314 , and recently I got a issue about CAN when I doing the test by short-circuiting of the oscillator ;
after recovery ,I monitored SPI ,ADC ,these modules works OK, but CAN module can not work normally,
the debuger show these information, in this status, CAN can not receive or send any fram,
how could this happened, and how to recover this fault by sw?
Snipaste_2026-08-04_13-32-47.jpg
Hi,
Thanks for your reply .
I try to add some test code in "Mcu_ClockSourceFailure_Notification" , but this notification do not be trigged;
so from software side , how can we notice this issue happened then reset CAN Module?
thanks
Below is the value of the registers you mentioned:
MCR
KidhRobin_0-1785975444257.png
CTRL1
KidhRobin_1-1785975470032.png
CBT:
KidhRobin_2-1785975496485.png
FDCBT:
KidhRobin_6-1785975801928.png
ECR
KidhRobin_4-1785975599003.png
ESR1
KidhRobin_5-1785975618985.png
Hi,
From the provided screenshot, the receive error counter (RXERRCNT) is increasing while TXERRCNT remains 0, which does not fully match a typical transmit-related issue even though ESR1 indicates a transmission attempt is ongoing.
The oscillator short-circuit could potentially have affected the clocking, resulting e.g. in incorrect CAN bit timing after recovery. However, the current information is not sufficient to confirm this.
Could you please provide:
If the FlexCAN module clock and the CAN protocol clock are running and have the expected frequency, you can also try performing a FlexCAN module software reset followed by a complete module reinitialization and check whether communication is restored.
BR, Petr
Hi,
If Mcu_ClockSourceFailure_Notification() is not entered, my first assumption would be that the corresponding MCU interrupt/notification path is not configured or enabled in the project.
Could you please check:
It may also be useful to inspect CMU and RGM status registers after the oscillator short-circuit event to verify that a clock failure is actually being detected.
From the FlexCAN register dump, the module appears enabled and synchronized to the bus (SYNCH=1), while RXERRCNT increases and TXERRCNT remains 0, now without bus activity. I see the bit timing registers shown (CTRL1, CBT, FDCBT) do not contain a valid CAN timing configuration, although this may be expected if Enhanced CAN Bit Timing is used and the actual timing is configured through the respective enhanced CAN bit timing registers.
Therefore, before implementing a CAN reset strategy, it would be good to first verify whether the clock failure event is detected at all and whether the notification mechanism is properly configured.
BR, Petr