2401930_en-US

[#1]

LX2162A USXGMII link never completes

Hey all,

I have an LX2162A SoM manufactured by Solidrun. I'm using a Clearfog devkit but moving to a custom carrier soon. 

Solidrun provides base RCW/DCP/DPL and I've verified functionality. In my case, the DPC for dpmac3 works for the SFP cage and I get an XFI link via SFP DAC cable and various SFP modules.

The RCW "rcw_2000_650_2900_3_11_0_auto" sets to SerDes1=3, SerDes2=11 and I'm using a QorIQ kernel (lf-6.6.52-2.2.0) and mc-utils (10.39.0) but with some Solidrun patched applied to both. Uboot and other things are also patched. All patches come from here: https://github.com/SolidRun/lx2160a_build/tree/develop-ls-6.6.52-2.2.0

I have a MaxLinear GPY245-EKV-1 (and -2) devkit(s) that wants USXGMII over DAC cable to connect the phy to the device. Apparently this is pretty normal. Eventually this phy chip will be integrated into SerDes2=7 Lane6 and Lane7 but I have to use the SFP cage on the Clearfog for testing.

Clearfog SFP (mac3) <-> DAC CABLE <-> GPY245-EVK-2 SFP

I'm only trying to configure dpmac3 to use this USXGMII link via DPC:

mac@3 {
    link_type = "MAC_LINK_TYPE_PHY";
    enet_if = "USXGMII";
};

(I've also tried MAC_LINK_TYPE_BACKPLANE)

Confirmed via "restool dpmac info dpmac.3" shows "DPMAC ethernet interface: DPMAC_ETH_IF_USXGMII".

In Linux, I added the MaxLinear driver and patched a few things:

• gpy_update_interface() fix (LKML, Daniel Golle). This was returning -EINVAL for USXGMII interface, crashing phy_state_machine.
• Patched lynx_pcs_config_usxgmii() in pcs-lynx.c to also write MII_BMCR (BMCR_ANENABLE | BMCR_ANRESTART) via mdiobus_c45_modify(), since the function only ever wrote MII_ADVERTISE and never enabled AN on the Replicator block itself. This gap matches another post on this forum ("LS1028A 10g-qxgmii phy bring-up") which found the identical symptom (MMD31.0/Replicator control register stuck at 0) and got AN to kick in after manually setting bit 12.

This is the DPMAC3 Linux devicetree entry:

&dpmac3 {
    managed = "in-band-status";
    phy-mode = "usxgmii";
    phy-handle = <&gpy245_p0>;
    phys = <&serdes_1 7>;
    status = "okay";
};

where `gpy245_0` is the MDIO node. MDIO traffic to the phy is working.

I added a printout in the lynx_pcs driver which shows the readback:

mdio_bus 0x0000000008c0f000:00: USXGMII:
wrote ADV=0xd601 BMCR=0x1a00
readback ADV=0x6b00 BMCR=0x0800 BMSR=0x0000  LPA=0x0000

Question:

Given writes to MDIO_MMD_VEND2 registers on this PCS instance don't appear to persist, is there a known additional step (SerDes/PCS block enable, protocol-specific initialization, or similar) required before the USXGMII on the LX2162A family SoCs will accept configuration? Is protocol 3 fully validated for USXGMII on dpmac3, or primarily intended/tested for XFI?

Other questions:

Maybe I don't understand GPY245 and USXGMII. I see some folks refer to this as QXGMII and I can't tell if the LX2162A is even capable of that working.

Maybe I need to reach out to Solidrun, but all of their patches do not seem to limit the LX2162A's capability.

Thanks!