2402064_en-US

[#1]

ddr_stress_tester cannot work on some DDRs

I have been using  ddr_stress_tester tools for many years, this year, I found the tool cannot work well on some newer manufacturing process DDRs, (20nm or 25nm DDRs),  we found that the binary will hang when I select cpu frequency. For example, winbond  w631gu6rb and ISSI IS43TR166640C-125JBLI-TR. by the way  CPU model is mx6solo/dl

i.MX6DLRe: ddr_stress_tester cannot work on some DDRs

The symptom is more likely tied to the DDR initialization/MMDC setup or board-level margin than to the DDR die process node itself. I could not find an NXP-documented issue that says the i.MX6Solo/DL ddr_stress_tester hangs specifically because the DDR3 is 20 nm/25 nm, nor anything specific to Winbond W631GU6RB or ISSI IS43TR166640C after checking NXP library/community paths by part number, process node, and “CPU frequency” hang wording.

What I would check first:

• Use the i.MX6/7 DDR Tool flow, not an old fixed script

• The i.MX6/7 DDR tools are intended to generate and test a custom DRAM initialization based on the actual device configuration — density, chip-selects, bus width, board layout/swizzling, etc. — and they explicitly cover i.MX6DL/S devices.

• If you changed DDR vendors or DDR geometry/timing, regenerate the .inc initialization script using the DRAM Register Programming Aid / DDR tool flow; NXP notes that scripts “may need to be modified for your custom board and memory.”

• Do not assume old calibration values still apply

• The stress tool performs write leveling, DQS gating, read/write delay calibration, and stress testing on i.MX6 boards.

• If it hangs right after selecting frequency, the DDR may already be marginal before calibration can complete. NXP community guidance for similar i.MX6 DDR stress hangs points to incorrect MMDC parameters, power brownout, board noise, or layout issues.

• Check DDR voltage/mode and frequency selection

• i.MX6Solo/DualLite DDR pads support LPDDR2 and DDR3/DDR3L modes.

• For DDR3/DDR3L I/O supply, the i.MX6Solo/DL datasheet excerpt gives OVDD as 1.425–1.575 V for DDR3 and 1.283–1.45 V for DDR3L .

• The i.MX6 DDR stress tool supports DDR stress testing between 135 MHz and 672 MHz ; select a conservative DDR frequency first, then work upward after calibration passes.

• Review refresh timing

• There is an i.MX6 case where low-frequency hang was resolved by correcting MMDC0_MDREF , changing tREFI from 3.9 µs to 7.8 µs .

• NXP documentation also points to MMDCx_MDREF as the register controlling DDR refresh behavior, and notes that some DDR3 devices require temperature-dependent refresh changes, e.g. 64 ms refresh period at ≤85 °C and 32 ms above 85 °C.

• Eliminate known tool-environment hang causes

• If running from U-Boot, disable splash screen / IPU or any DMA that may still access DRAM; NXP notes that active IPU/splash access can make the system hang during the DDR stress flow.

• Check whether the watchdog fuse/configuration is enabled; NXP notes that on i.MX6Solo the watchdog can reset the device while DDR_Stress_Tester is doing calibration or stress test.

• If you are using the JTAG version, one reported i.MX6 case stopped after DDR frequency selection, and the guidance was to check JTAG mode/connection and use simple SDK DDR tests plus signal/power probing.

My recommendation: regenerate the DDR init script for each new DDR part, start with a lower MMDC/DDR frequency, verify MDREF /timing values against the DDR datasheet, then rerun calibration. If it still hangs at CPU/DDR frequency selection, scope DDR power rails and clocks during that transition and compare MMDC register values between the old working DDR and the new Winbond/ISSI parts.

The issue should be treated as an i.MX6Solo/DL DDR initialization and margin problem first; I did not find evidence that NXP identifies 20 nm/25 nm DDR3 process itself as a ddr_stress_tester incompatibility.