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MCU P89C52X2BNフラッシュするにはどうすればいいですか? こんにちは、皆さん。 P89C52X2BNとP89C52RD2という2つの古いMCUをプログラムする必要があります。 P89C52RD2については、シリアル経由でISPをサポートしていると理解しています。しかし、ISP/IAPプロトコルをアクティブ化する方法はまだわかっていません。 P89C52X2BNの場合、どのようにファームウェアを書き換えればよいですか?並列プログラマが必要ですか?必要であれば、どのようなプロトコルを使用し、フラッシュモードをアクティブ化すればよいでしょうか? 主にこれら2つのチップ(特にX2BN)の公式プログラミングドキュメントを探しています。正しいフラッシュプログラミングインターフェースとタイミングを参照できるようにするためです。データシートのプログラミングに関するセクション、またはリンクをお持ちでしたら、ぜひ共有してください。 ありがとう! Re: How to Flash P89C52X2BN MCU? Hello ご不便をおかけし申し訳ありません。P89C52ファミリーは現在製造中止で、そのためサポートも終了しており、このファミリーに関する情報はもはや利用できません。 もしあなたに合うなら、89C51の情報があります;重要:この情報がいつ有効か確認・テストすることはできませんし、89C52の申請もできません。 89C51Rx+/Rx2/66xマイクロコントローラの回路内およびアプリケーション内プログラミング よろしくお願いいたします。 Re: How to Flash P89C52X2BN MCU? 申し訳ありませんが、XSP6100Nは非常に高価で、平均的な人の6~12か月分の給料に相当します。だから、ドキュメントを読んで、自分でフラッシュしてみようと思います。XSP6100Nできますが、払えません、ありがとう。 Re: How to Flash P89C52X2BN MCU? このANNはP89C5xRx2に使えますが、P89C5xX2が欠けています。このANは正しいタイプのドキュメントですが、P89C5xX2が欠けているだけです。ありがとう!
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i.mx8mp GPUとGTK4アプリ:GUI/ウィンドウ表示遅延とVivante /dev/galcore ioctlのブロック Vivante GPUを搭載したi.MX8MPでのGTK4ウィンドウ起動遅延(約10秒) デフォルトのGTK4 GLレンダラーを使用する場合: gtk_window_present(window);​ ウィンドウが表示されるまでには約9~10秒かかります。 証拠(添付ファイル参照)は、起動遅延がGTKアプリケーションコードによるものではないことを強く示唆しています。 この遅延は、GLレンダリングパス内のVivante /dev/galcore ioctlのブロッキングと関連しているようです。ソフトウェアレンダリング(GSK_RENDERER=カイロ)はこの問題を回避します。 Vivante GPUスタックを用いたi.MX8MPでのGTK4/OpenGL起動**レイテンシ**に関する既知の問題、デバッグ方法、設定変更、または修正方法について のガイダン スを探しています。 Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl こんにちは、 @jim777さん 詳細な情報を共有していただき、ありがとうございます。最小限で再現可能なGTK4のソースコード例を教えてもらえますか?NXP BSPでさらにテストを実施する必要があります。 よろしくお願いします、 志明 Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl こんにちは、志明さん 迅速なご対応ありがとうございます! テスト用の、骨組みは小さいながらも完全なソースファイルを添付しました。 実行前に設定された環境変数: #!/bin/sh export XDG_RUNTIME_DIR=/run/user/0 export WAYLAND_DISPLAY=wayland-1 export GDK_BACKEND=wayland export GSK_RENDERER=gl weston.ini からの関連情報: root@nitrogen8mp:~# cat /etc/xdg/weston/weston.ini [core] #gbm-format=argb8888 use-g2d=true repaint-window=16 idle-time=0 xwayland=true #enable-overlay-view=1 [shell] panel-position=none [libinput] touchscreen_calibrator=true #[output] #name=HDMI-A-1 #mode=1920x1080@60 #transform=rotate-90 #[output] #name=HDMI-A-2 #mode=off # WIDTHxHEIGHT Resolution size width and height in pixels # off Disables the output # preferred Uses the preferred mode # current Uses the current crt controller mode #transform=rotate-90 [screen-share] command=/usr/bin/weston --backend=rdp-backend.so --shell=fullscreen-shell.so --no-clients-resize #start-on-startup=true [input-method] path=/usr/libexec/ibus-wayland GPUサポートのないデスクトップでのgtk_window_presentの実行時間は数百ミリ秒(<1秒)かかります。そしてi.mx8MPデバイスでは9970ミリ秒かかります: root@nitrogen8mp:~# gtk4-test A: activate: before _present: 47333 ms B: activate: after _present: 57303 ms, takes: 9970 ms C: activate: after idele_add: 57303 ms D: startup_task_cb: 57315 ms ^C root@nitrogen8mp:~# render: nglを試しましたが、画像やウィジェット、動画のにじみが生じてしまい、 Vulkanが重大なエラーを引き起こす:ローダーメッセージ:vkCreateDevice:リスト内の拡張を検証できません;表面の「GdkWaylandToplevel」に対してタイプ「GskVulkanRenderer」のレンダラーを実装できません:必要な機能を持つVulkanデバイスを見つけられませんでした。 私たちのアプリにはGPUサポートが必要で、Wayland/Westonで推奨されているレンダラーはまだGL(UG10159 11.3.2.1 GLレンダラー)なので、解決策を見つける手助けをいただければ幸いです。 よろしくお願いします、 Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl こんにちは@Zhiming_Liu  すでに共有されたこと以外に、この問題を解決するために私にできることはありますか? もしうまくいく方法があれば、起動時間を大幅に短縮してください。例えば設定の変更、環境変数の設定、バージョンの違い、GPUドライバーの修正やパッチについて教えてください。 ありがとうございます。 Re: i.mx8mp GPU and GTK4 app: GUI/window present delay and blocking Vivante /dev/galcore ioctl こんにちは@jim777  GPUチームがこの問題を調査中で、少し時間がかかります。最新情報が入り次第、お知らせします。 よろしくお願いします、 志明
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PCF85263Aをハードウェアクロック(400kHz vs 100kHz)で使用した場合、起動時にI2C読み取りエラーが断続的に発生する。 こんにちは、NXPコミュニティの皆さん、 当社独自のボード(PCF85263A RTCとAM6252を使用)は、初期起動シーケンス中に以下のコマンドを使用してRTC時刻を一度だけ読み取ります。 hwclock -u -s 約1,000回に1回の割合で、RTC値の取得に失敗するという断続的な問題が発生しています。 (ただし、もし失敗してすぐに読み取りコマンドを再試行した場合、問題なく時刻を取得できます。) トラブルシューティングの過程で、全く同じ条件下でI2Cクロック周波数を400kHzから100kHz(400000→100000)に下げました。この変更後、約6,000回のテストを繰り返し実施しましたが、システムは一度も故障することなく完璧に動作しました。 PCF85263Aのデータシートによると、最大I2Cバス周波数400kHz(ファストモード)をサポートしています。 何かアドバイスをいただけますか: PCF85263Aを400kHzで使用した場合に発生する、この断続的なI2C読み取りエラーに関して、既知の問題、エラー、または同様の過去の報告はありますか? 400kHzクロックを維持しつつ解決するために、特定の構成やバスの静電容量/プルアップ抵抗の考慮点、またはデバッグの手順があれば教えてください。 あらかじめサポートに感謝いたします。 Re: Intermittent I2C read failure at boot with PCF85263A using hwclock (400kHz vs 100kHz) こんにちは、伊勢織さん。 PCF85263A自体には、400kHzのI²C動作において、既知の不具合や文書化されたハードウェアの問題はありません。この部品は400kHzまで仕様・生産テストされており、あなたが述べた挙動は、PCF85263Aの欠陥というよりも、ホストコントローラやバス側のタイミング準拠が限界的であることの典型的な症状です。 推奨されるデバッグ手順: - I²Cバスを400kHzでオシロスコープし、SCL/SDA波形をキャプチャします。RTC読み出しトランザクション中に、Tlow ≥ 1.3 µs、Thigh ≥ 0.6 µs、Tr ≤ 300 ns、および Tf ≤ 300 ns であることを確認してください。PCF85263Aのデータシートの表68に記載されているタイミング要件と比較してください。 - AM6252の正誤表を確認し、既知のI²C 400kHz SCL低周期違反がないか確認してください。I²Cクロックが存在する場合は、クロック周波数を375~384kHzに下げてください。これにより、通常は十分なマージンが回復し、実際には400kHz付近を維持できます。 回路図中のプルアップ抵抗の値を確認してください。抵抗値が約2.2 kΩより高い場合は、1 kΩ–2.2 に置き換えてください。kΩで測定し、400kHzで再測定する。 - シングルアクセス読み取りの検証:PCF85263Aはロールオーバー破損を防ぐために、すべてのタイムレジスタを単一のI²Cアクセスで読み取ることを要求しています。 BRs、トーマス
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S32K3 备用 RAM 数据在 Reset_Handler 之前已修改 你好, 当我使用 PE Micro 调试 S32K344 时,我发现了一个数组(__attribute__ ((section(".standby_data")))位于备用 RAM 段中的 volatile uint32_t WkupSourcestatus1[64];) 在进入 main() 时被意外修改。然后,如附图所示,我手动修改了寄存器,重新初始化了备用 RAM 区域。数据已正确初始化为 0,进入 main() 函数后,一切运行正常。但是,RESET 后,当我进入 Reset_Handler 时,WkupSourcestatus1 数组中的数据又被修改了。为什么会发生这种情况?我注意到数组中出现了大量的 0x5AA55AA5 值。这是否与 SBAF_BOOT_MARKER 有关?我在另一块电路板上测试过,现象相同。 8.png8.png8.png8.png8.png 然后我改用 J-Link 进行调试,发现调试过程中 RESET 时没有出现异常。但是,在重新启动调试会话后,备用 RAM 区域中的所有数据都会变成 0xDEADBEEF。这是预期行为吗? S32K344 S32DS3.6.4 RTD700 PE 版本 6.0.8 BR, 杰森 Re: S32K3 Standby RAM data modified before Reset_Handler HI 抱歉回复晚了,最近需要处理的咨询很多。 我建议您参考有关S32K311 待机 RAM 保留的讨论,了解如何使用待机 RAM。 此致敬礼, Robin Re: S32K3 Standby RAM data modified before Reset_Handler RESET 期间备用 RAM 的内容将保持不变,您观察到的值应该是 MCU RESET 前的内容。 ======================================================================================= RAM 由 SRAM 存储器和 TCM 集成而成。部分SRAM内存处于待机状态 模式。这意味着将MCU设置为待机模式后,该存储器中的内容将被保留。这 S32K3产品系列利用了ARM Cortex M7架构的TCM特性,其主要目的是 为核心提供确定性的访问时间,以便访问一些重要数据,避免访问延迟。这 该特性可在实时操作系统中加以利用。 如前所述,由待机功能域提供的存储在待机 SRAM 存储器中的数据在以下情况下会被保留: MCU处于待机模式,唤醒后即可使用。但 Run 提供的 SRAM 中的数据却来自这里。 功能域不可用,需要在唤醒后进行初始化,以避免 ECC 错误。很重要 需要指出的是,唤醒后,待机 SRAM 不需要初始化以避免 ECC 错误,但是 SRAM 的其余部分确实需要它,因此应该在启动代码中进行适当的区分。一个 以下代码示例说明了如何进行这种区分。 Re: S32K3 Standby RAM data modified before Reset_Handler 你好 抱歉回复晚了。 在我的测试中,我没有执行任何睡眠/唤醒操作。我只是通过 S32DS 执行了 RESET,这导致待机 RAM 区域中的数据发生了变化。检查映射文件,该变量确实位于备用 RAM (0x20400000) 中。我查看了您提供的链接,但它似乎与该链接中的问题无关。 BR, 杰森
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i.MX93 パラレルダイアプリインターフェース こんにちは、 私はi.MX93(MIMX9332CVVXMAC)を搭載した基板を設計しており、並列インターフェースを持つRGBディスプレイを駆動する必要があります。設定ツールからは、R,G,Bチャネルを参照せずにデータ0-23のlebelledデータビットが割り当てられています。evb FRDMとTM050RDH03-41も調べてみましたが、残念ながらFRDMのデータは設定ツールと同じで、TM050RDH03-41の回路図は提供されていませんでした。 ピン配置を確認するための回路図を入手することは可能でしょうか? それとも、24ビットがR、G、Bのチャネル間で自由にマルチパクシングできるのか確認できますか? ありがとうございました。 エンリコ Re: i.MX93 parallel diaply interface こんにちは、 NXP Semiconductors製品にご関心いただきありがとうございます。 TM050RDH03-41ディスプレイコネクタの回路図をご覧ください。完全な回路図に興味がある場合は、技術CASEを作成してください。 JosephAtNXP_0-1789574219944.pngJosephAtNXP_0-1789574219944.png よろしくお願いします。
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SE052 采用问题:EdDSA/X25519 可用性、非 FIPS 变体路线图、小程序限制 你好, 我们目前使用的是SE050E2 (小程序 7.2.0,在两个设计中,芯片报告为“SE051”(ATR,AppletConfig 0x3F9F),我们正在评估SE052,以用于下一个硬件版本。在做出决定之前,我们阅读了 SE052 数据表(修订版 1.5)、AN14028、AN14277、AN13904、AN12543(修订版 4.5)和 Plug & Trust MW 文档(AN13030 修订版 2.7),但有几点阻碍了我们做出决定。希望您能澄清一下。 我们的两个应用案例: 一个网状/传输节点(LoRa + 以太网),其标识为 X25519 + Ed25519 在 SE 内部生成和使用的密钥对(通过 ECDH) ECDH生成共享密钥 在 ID_ECC_MONT_DH_25519,通过以下方式签名 EdDSASign 和 ED25519PURE_SHA_512)。 使用签名设备 secp256k1 ECDSA (预先计算的摘要)和 Ed25519 针对不同的目标,使用受用户 ID 保护的会话。 问题: 变体。AN14277 指出 SE052F (OEF B501, FIPS 140-3) 是“唯一发布的变体”,其 GetInfo 显示没有 EDDSA / 没有 DH_MONT。是否有针对非 FIPS SE052 配置(相当于启用 CONFIG_EDDSA 和 CONFIG_DH_MONT 的 SE050E / SE051)的路线图?如果属实,大致时间范围和OEF是多少? 在 SE052F 上启用 EdDSA / Montgomery DH。由于 SetAppletFeatures 需要 RESERVED_ID_FEATURE (0x7FFF0204),而 RESERVED_ID_FEATURE 是 NXP 拥有的,那么客户是否有任何途径在 SE052F 上启用 Ed25519/X25519(例如,通过 EdgeLock 2GO 进行自定义配置),同时接受失去 FIPS 批准模式?或者说,无论小程序功能位如何,FIPS OS 版本都会阻止这些曲线? FIPS 和 EdDSA。FIPS 186-5 批准 EdDSA。未来是否有计划推出支持 Ed25519 和 X25519 且符合 FIPS 140-3 标准的未来 SE052 小程序/操作系统版本(通过 SEMS Lite 或新的 OEF)? APDU吞吐量限制。AN14028 §2.3.1 / AN13904 §8.4 描述了 1,000,000 APDU / 34 天的限制 (SW 66A6) 以及每 500,000 APDU 进行一次 FIPS 自检。这些是否仅与 FIPS 认证有关,在假设的非 FIPS SE052 变体中是否会缺失?通过 RST_N 重置是否足以清除计数器而不会对 NVM 产生影响? 针对签名用例的 Applet 功能路线图。我们在 AN12543 Rev 4.5 中找不到以下任何内容。7.2.x 版本有相关计划吗?一行代码还是未来的小程序? SE 内部强化了子密钥派生(标量加法 mod n,BIP32 风格),因此派生的私钥永远不会离开芯片。 secp256k1 上的 Schnorr 签名 (BIP340)。 确定性 ECDSA nonce(RFC 6979)和/或低 S 归一化。 预哈希 Ed25519 (Ed25519ph) 或流式 EdDSA 模式,因此长度超过 IFSC (0xFE) 的消息不依赖于 T=1 链接。 小程序 7.2.22 中的 UserID 行为。在 SE050E2 (7.2.0) 中,我们观察到,TAG_MAX_ATTEMPTS 耗尽的 UserID 对象无法再被删除(即使在 SCP03 平台上,DeleteSecureObject → 6986),并且尝试计数器属性始终显示为 0。AN14028 表 1 指出,属性现在显示最大尝试次数。2022年7月2日:(a)是否报告剩余/已用计数器?(b)SCP03 平台用户能否删除已耗尽的 UserID? ECDH NVM 磨损(也适用于我们目前的 SE050E2)。AN12543 §4.10.3 指出,当公钥作为字节数组(TAG_2)传递时,MONT_DH_25519 上的 ECDHGenerateSharedSecret 会在每次调用时写入 NVM,但当通过瞬态ECPublicKey 对象(TAG_3)传递时则不会写入 NVM。您能否确认这同样适用于带有 applet 7.2.0 的 SE050E,并且在调用之间使用 WriteECKey 更新瞬态对象的内容本身不会写入 NVM? 长寿。SE050E2 是否在恩智浦的产品生命周期计划范围内?是否有计划中的产品生命周期结束?这将决定我们下一次修订是否继续使用 SE050E2 版本。 提前谢谢您。 SE050 Re: SE052 adoption questions: EdDSA/X25519 availability, non-FIPS variant roadmap, applet limits 嗨@cvaldess , 感谢您的联系!让我逐一解答。 第一季度 — 非 FIPS SE052 变体路线图 正如您正确指出的那样,SE052F (OEF B501) 目前是唯一发布的 SE052 变体,其 AppletConfig 0x26F2 不包含 EdDSA 或 DH_MONT。我们不能在公共论坛上分享具体的路线图时间表,但我建议您联系当地的 Disti/NXP FAE,在签署保密协议 (NDA) 的情况下讨论您的需求,届时可以直接讨论路线图细节。 Q2 — 在 SE052F 上启用 EdDSA / Montgomery DH SE052F 上没有客户路径可以启用这些算法。 RESERVED_ID_FEATURE (0x7FFF0204) 是 NXP 拥有的对象,客户无法修改或删除它——EdgeLock2GO 不是启用它的机制。更根本的是,SE052F FIPS 140-3 OS 版本在认证配置中排除了操作系统/硬件级别的 Twisted Edwards (Ed25519) 和 Montgomery (Curve25519) 曲线支持。即使通过 SEMS Lite 加载自定义小程序也无法重新启用操作系统层中不存在的曲线——而且这样做无论如何都会使模块不符合 FIPS 标准,正如 AN14277 明确指出的那样。 第三季度——未来 SE052 小程序/OEF 将支持 FIPS 140-3 和 EdDSA。 FIPS 186-5(2023 年 2 月)确实批准了 EdDSA,因此标准基础是存在的。但是,任何在新 FIPS 140-3 证书下支持 Ed25519/X25519 的 SE052 OEF 都需要提交完整的 CMVP 重新认证申请。我们不便在公共场合确认相关计划或时间表。请与您当地的 Disti/NXP FAE 联系,就此问题进行保密协议 (NDA) 谈判。 第四季度 — APDU 吞吐量限制(SW 66A6) 是的,1,000,000 APDU / 34 天计数器和 500,000 APDU 定期自检是 FIPS 140-3 合规性要求,专门针对 SE052F。假设存在非 FIPS SE052 变体,则该变体不受这些限制。 关于 RESET:T=1oI2C 芯片 RESET(RST_N 切换或电源循环)是官方记录的恢复路径。APDU 计数器是会话驻留在 RAM 中的值——冷 RESET 时,如果没有 NVM 写入,它将被清除。Plug & Trust MW 包含一个 apdu_throughput_limit 演示,该演示使用 phNxpEse_reset 精确地演示了这种恢复。对于您的网状/传输节点用例,持续每分钟约 340 个 APDU,此限制在实践中应该不会造成问题,但请确保您的主机驱动程序能够通过自动重置优雅地处理 SW_66A6 。 Q5 — Applet 功能路线图(BIP32、Schnorr、RFC 6979、Ed25519ph) 您列出的特性——片上 BIP32 强化子密钥派生、Schnorr/BIP340、确定性 ECDSA nonce(RFC 6979)、低 S 归一化或 Ed25519ph——均未出现在 AN12543 Rev 4.5 或任何当前的 SE05x 文档中,并且在 7.2.x 版本中也没有任何关于这些特性的公开声明。线。我建议您通过您当地的 Disti/NXP FAE 提交正式的产品改进请求,以便我们的产品团队可以跟踪这些请求。 关于 Ed25519 的 T=1 链接问题:该小程序支持 IFSC (0xFE) 之外的 APDU 数据的多块 T=1 链接,因此消息长度在传输层处理,并且不是 EdDSA 操作的功能限制。 Q6 — 小程序 7.2.22 中的 UserID 行为 (a)计数器可读性: GetAttributes 响应返回配置的 TAG_MAX_ATTEMPTS 值(最大值),而不是剩余计数。当前小程序版本中,内部递减计数器并未作为直接可读属性公开。 (b)通过 SCP03 删除已耗尽的用户 ID:您在 7.2.0 版本中观察到的删除锁定用户 ID 时出现的 6986 错误是一个已知的限制。AN13904 没有明确记录在平台 SCP03 删除的背景下,7.2.22 的此行为发生了变化。我建议直接在 SE052F 评估硬件(或运行 7.2.22 的 SE051 样品)上验证这一点。作为一种变通方法,如果锁定的用户 ID 阻止了对象管理,则通过平台 SCP03 上的 RESERVED_ID_FACTORY_RESET 进行恢复出厂设置是已确认的路径——尽管这会清除所有用户对象,因此对象布局规划在这里很重要。 Q7 — ECDH NVM 磨损(SE050E,小程序版本 7.2.0) 确认的。AN12543 明确指出, ECDHGenerateSharedSecret on ID_ECC_MONT_DH_25519 仅当公钥作为字节数组 (TAG_2) 传递时才会导致每次调用写入 NVM。当公钥通过瞬态 ECPublicKey 对象 (TAG_3) 传递时,不会发生 NVM 写入。此行为适用于带有 applet 7.2.0 的 SE050E,因为 SE050E2 使用的是相同的 7.x applet 版本(SE051 芯片和 applet 系列,正如您的 GetInfo ATR 所确认的那样)。 WriteECKey 对瞬态对象进行写入操作时,仅写入 SRAM——在调用之间更新瞬态对象的内容不会造成 NVM 损耗。建议的节点模式是:在启动时分配一个持久的瞬态 ECPublicKey,在每次 ECDH 操作之前调用 WriteECKey (仅限 SRAM),然后调用 ECDHGenerateSharedSecret 并引用该瞬态对象 TAG_3。这样就完全避免了每次通话造成的非易失性存储器损耗。 Q8 — SE050E2 产品寿命 SE050E2于2022年发布。NXP 的产品寿命计划承诺,对于已注册的产品,自上市之日起至少可供货 10 或 15 年。有关 SE050E2 的最终注册状态和使用寿命期限,请查看NXP 产品使用寿命页面(完整表格需要登录)或请您的 NXP FAE 确认。 针对您的两个用例的总体建议 鉴于您的设计依赖于 Ed25519 (EdDSASign) 和 X25519 (MONT_DH_25519 上的 ECDHGenerateSharedSecret), SE052F 目前无法满足您的加密要求。在具有这些算法的 SE052 型号推出之前,SE050E2 / SE051 系列仍然是合适的选择。我们建议您向 NXP FAE 确认 SE050E2 的长期有效状态,并注册对非 FIPS SE052 等效产品的需求。 希望这能帮助您更好地做出决定。如果您还有其他问题,请告诉我。 祝你有美好的一天, 坎 ------------------------------------------------------------------------------- 笔记: - 如果此回复解答了您的问题,请点击“标记为正确答案”按钮。谢谢你! - 我们会持续关注帖子,从最后一条回复发出后持续7周,之后的回复将被忽略。 如果您之后有相关问题,请另开新帖并引用已关闭的帖子。 -------------------------------------------------------------------------------
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S32K358 高速スタンバイ こんにちは、 S32K358で高速スタンバイ機能をテストしたいです。S32DSでIPレイヤーのデモを作成しました。このプログラムは起動後5秒で高速スタンバイ状態に入り、3秒後にRTC-APIによって起動されます。これは問題なく動作します。 そこで、このプロジェクトを参照して、MCALレイヤーのデモを作成するためにEBプロジェクトを設定しましたが、失敗しました。高速スタンバイ状態になってから3秒後、電流が増加した。これはデバイスが起動したことを示唆しているが、メイン機能には移行しなかった。PE Microで接続した後、以下のエラーメッセージが表示されます。 割り込みコマンドを受信しました。執行を停止します。 UsageFault: 無効な EPSR.T または EPSR.IT フィールドで実行された命令。 バスフォールト:不正確な(非同期)データアクセスエラーが発生しました。 ハードフォールト:障害がハードフォールトにエスカレートしました。 ウェイクアップ後のベクトルテーブルを以下に示します。 1.png1.png PCレジスタは0x0です。スタックの内容を確認すると、FastWkup_EntryAddressが入力されており、ハードフォールトはReset_Handlerにジャンプした後に発生します。 2.png2.png 3.png3.png 4.png4.png FastWkup_EntryAddress に while(1) ループを追加しても、ハードフォルトは依然として発生します。 5.png5.png スタンバイモードに入ると、単語が出てきます。 このプロジェクトでは、PMIC_PGOOD_HNDSHK_BYPが有効になっています。この基板には外部水晶発振器が搭載されていないため、コアクロックとしてFIRCが使用されています。 S32K358 RTD6.0.0 S32DS3.6.3 EB29.0 BR、 ジェイソン Re: S32K358 FAST STANDBY こんにちは、@Jason07 さん。 高速スタンバイ起動時、sBAFはVTORをカスタムベクターテーブルアドレスに設定します。 しかし、あなたのベクターテーブルには3つのエントリしか定義されていません。 初期SP、 リセットハンドラ (FastWkup_EntryAddress)、 NMIハンドラー。 つまり、ハードフォールトベクトルが抜けているのです。 何らかの故障が発生すると、CPUは定義されていないハードフォールハンドラーアドレスを取り出し、これがPC値の原因となる可能性があります。 この問題をさらにデバッグするには、ベクターテーブルに適切なハードフォルトハンドラを追加してください。それらが設定されると、ハンドラーが0x0にクラッシュする代わりに呼び出され、スタックされたPC、LR、そして元の故障の構成可能な故障状態レジスタ(CFSR/BFAR)にアクセスできます。 ありがとうございました。 BR、ダニエル
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正在寻找适用于 FRDM-IMX8MPLUS 板的 Robotics Edge Image 1.0.0 大家好, 我正在寻找适用于 FRDM-IMX8MPLUS 板(不是 IMX8MP-EVK)的 Robotics Edge Image 1.0.0 的发布包。 可以找到适用于 IMX8MP-EVK 或 IMX95EVK 的预编译镜像,但没有找到适用于 FRDM-IMX8MPLUS 的镜像。该开发板受支持( https://mcuxpresso.nxp.com/RoboticsEdgePlatform/latest/html/gsd/prebuilt-images.html )。 从源代码(Yocto)构建它简直是噩梦,因为它需要大约 1 TB 的空间,而且在此过程中会出现很多错误。 希望能得到满意的答复。 顺祝商祺! Re: Looking for robotics Edge Image 1.0.0 for FRDM-IMX8MPLUS board 好的,我的错,FRDM-IMX8MPLUS 文件打包在 IMX8M-EVK 压缩包里。 同一个名字,却涉及两个董事会。
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TapLinxを使っている人はいますか? 誰かNXPのTapLinx SDKを使ってMIFAREカードと連携していますか? 最小限のコンソールアプリの例に興味があります。サンプルアプリは、多数の機能を備えたGUIアプリなので、動作させるのに少し手間がかかります。 カードへのデータの読み書き、認証などを行うだけの、最小限の機能しか持たないコンソールアプリを探しています。 Kotlinの例であればなお良いですが、Javaの例でも構いません。 はじめに Re: Anyone using TapLinx? こんにちは、@reid88さん TapLinx SDKはMIFARE DESFire、Plus、Classic、Ultralight、NTAGなどに対応しています。デザインリソースは以下から確認できます: MIFARE、NTAG、ICODE、UCODE用のTapLinx SDK |NXPセミコンダクターズ
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Looking for robotics Edge Image 1.0.0 for FRDM-IMX8MPLUS board Hi everybody, I'm looking for a release package for a FRDM-IMX8MPLUS board (not IMX8MP-EVK) of Robotics Edge Image 1.0.0. It's possible to find a pre-built image for IMX8MP-EVK or IMX95EVK, but nothing was found for FRDM-IMX8MPLUS. The board is supported (https://mcuxpresso.nxp.com/RoboticsEdgePlatform/latest/html/gsd/prebuilt-images.html) Building it from source (Yocto) is a pure pain, as it takes around 1 TB of space and there are plenty of errors during the process. Hope to have a successful answer. Best regards, Re: Looking for robotics Edge Image 1.0.0 for FRDM-IMX8MPLUS board Ok, my bad, FRDM-IMX8MPLUS files are packaged in the IMX8M-EVK zip file.  A single name, but two boards addressed.
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S32K358 FAST STANDBY Hello, I would like to test Fast Standby on the S32K358. I created an IP-layer demo in S32DS where the program enters Fast Standby 5 seconds after startup and is woken up by RTC-API after 3 seconds. This works without any issues. Then I referred to this project and configured an EB project to create an MCAL-layer demo, but it failed. After 3 seconds in Fast Standby, the current increased, which suggests the device woke up, but it never entered the main function. After attaching with PE Micro, the error messages are as follows: Interrupt command received. Halting execution. UsageFault: An instruction executed with an invalid EPSR.T or EPSR.IT field. BusFault: An imprecise (asynchronous) data access error has occurred. HardFault: A fault has been escalated to a hard fault. The vector table after wake-up is shown below: 1.png1.png The PC register is 0x0. Checking the stack contents, I can see that FastWkup_EntryAddress was entered, and the HardFault occurs after jumping to the Reset_Handler. 2.png2.png 3.png3.png 4.png4.png If I add a while(1) loop in FastWkup_EntryAddress, the HardFault still occurs. 5.png5.png If I enter standby mode, it word. In the project, PMIC_PGOOD_HNDSHK_BYP is enabled. Since the board does not have an external crystal oscillator, FIRC is used as the core clock. S32K358 RTD6.0.0 S32DS3.6.3 EB29.0 BR, Jason Re: S32K358 FAST STANDBY Hello @Jason07, On Fast Standby wakeup, the sBAF sets VTOR to your custom vector table address. However, your vector table only defines three entries: Initial SP, Reset Handler (FastWkup_EntryAddress), NMI Handler. So the HardFault vector is missing. When any fault occurs, the CPU fetches the not defined HardFault handler address, which could explain the observed PC value. To debug this further, please add a proper HardFault handler to the vector table. Once those are in place, the handler will be invoked instead of crashing to 0x0, giving you access to the stacked PC, LR, and the Configurable Fault Status Register (CFSR/BFAR) of the original fault. Thank you, BR, Daniel
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S32K3スタンバイRAMデータはリセットハンドラ実行前に変更されました こんにちは、 PE MicroでS32K344をデバッグすると、配列(__attribute__ ((section(".standby_data"))) が見つかりました。スタンバイ RAM セクションにある volatile uint32_t WkupSourcestatus1[64];) が main() に入るときに予期せず変更されます。そして、添付の動画に示すように、スタンバイRAM領域を再初期化するためにレジスタを手動で変更しました。データは正しく0に初期化され、main()関数に入った後はすべて正常に動作しました。しかし、リセット後、Reset_Handlerに入ると、WkupSourcestatus1配列のデータが再び変更されます。なぜこのようなことが起きているのか?配列の中に0x5AA55AA5という値が多数出現していることに気づきました。これはSBAF_BOOT_MARKERに関連していますか?別の基板でも試してみましたが、同じ現象が発生しました。 8.png8.png8.png8.png8.png その後、J-Linkを使ってデバッグに切り替えましたが、リセット中に異常は発生しません。しかし、デバッグセッションを再開すると、スタンバイRAM領域内のすべてのデータが0xDEADBEEFになります。これは想定される動作ですか? S32K344 S32DS3.6.4 RTD700 PE v.6.0.8 BR、 ジェイソン Re: S32K3 Standby RAM data modified before Reset_Handler ハイ 返信が遅くなり申し訳ありません。最近、お問い合わせが多数寄せられており、対応に追われております。 スタンバイRAMの使用方法については、 S32K311のスタンバイRAM保持に関する議論を参照することをお勧めします。 よろしくお願いいたします ロビン Re: S32K3 Standby RAM data modified before Reset_Handler リセット中もスタンバイRAMの内容は残り、あなたが観察した値はMCUリセット前の内容であるはずです ======================================================================================= RAMはSRAMメモリとTCMによって統合されている。SRAMメモリの一部はスタンバイ状態で使用可能です。 モード。つまり、MCUをスタンバイモードに設定した後も、このメモリの内容は保持されます。その S32K3製品ファミリーは、ARM Cortex M7アーキテクチャのTCM機能を活用しており、その主な目的は 重要なデータに対してコアへの決定論的アクセス時間を提供し、アクセスの遅延を防ぎます。これだ この機能はリアルタイムオペレーティングシステムで活用可能です。 前述の通り、スタンバイドメインによってソースされたスタンバイSRAMメモリに保存されるデータは、 MCUはスタンバイモードで、ウェイクアップ後に利用可能です。しかし、Runによって取得されたSRAM内のデータは ドメインが利用できないため、ECCエラーを回避するために、ウェイクアップ後に初期化する必要があります。重要なことです ウェイクアップ後は、ECCエラーを避けるためにスタンバイSRAMを初期化する必要がないことを指摘しますが、 SRAMの他の部分はそれを必要とするため、起動コードで適切な区別を行うべきです。1 この区別を示す例を以下のコードに示します。 Re: S32K3 Standby RAM data modified before Reset_Handler こんにちは 返信が遅くなり申し訳ありません。 私のテストでは、スリープ/ウェイクアップ操作は一切行いませんでした。S32DS経由でリセットを実行しただけで、スタンバイRAM領域のデータが変更されました。マップファイルを確認すると、変数は確かにスタンバイRAM(0x20400000)に存在している。ご提示いただいたリンクを確認しましたが、そのリンク先の問題とは関係がないようです。 BR、 ジェイソン
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Zone Node Software & Hardware Environment 1 Table of Contents • Introduction • Required Software • Required Hardware • References • Conclusion 2 Introduction This article is part of the Zone Node series and describes the software and hardware environment used throughout the project. The purpose of this article is to describe the software and hardware setup required to follow the series and reproduce the results. Before examining communication routing, control logic, or integration challenges, it is important to understand the tools and platforms that support the development and execution of the zonal node application. This article introduces the software components used to develop, configure, and deploy the application, as well as the hardware platforms used to demonstrate the zonal controller functionality. This information provides the foundation required for the remaining articles in the series. Overview of the development flow The zonal node application presented in this series is developed using a combination of Model-Based Design tools, NXP software components, and automotive-grade hardware platforms. At a high level: Application modeling starts in MATLAB® and Simulink®, where communication routing and control logic are implemented graphically. Code generation converts the model into production-ready embedded software using the code-generation tools provided by MathWorks and NXP. Deployment compiles the generated software and loads it onto the target hardware, where it is used to demonstrate communication between multiple vehicle networks. This environment was selected to support rapid development, easier validation, and improved traceability between model design and generated software. By using a Model-Based Design approach, algorithm development, communication integration, and application verification can be performed within a common framework. The software and hardware presented here are used consistently throughout the series and will be referenced when discussing communication routing, system behavior, and integration scenarios. dragostoma_0-1784698703294.pngㅤ Figure 1. Development flow diagram The workflow begins with application development in Simulink. Communication routing logic, control functions, and software configuration are implemented within the model. The NXP Model-Based Design Toolbox (MBDT) provides hardware-specific blocks that enable integration with S32K3 peripherals and communication interfaces. Following code generation, the application is compiled and deployed to the target hardware, where communication routing functionality can be validated. This article is intended for: Engineers interested in reproducing the zonal node demonstration Simulink users developing automotive communication applications Developers evaluating Model-Based Design workflows Engineers working with NXP automotive microcontrollers and evaluation boards By understanding the software and hardware environment early in the series, readers will be better prepared to follow the implementation details presented in subsequent articles. 3 Required Software The following software components are used throughout the project: MATLAB® and Simulink® – model development and simulation Embedded Coder® (required MATLAB toolbox) – automatic code generation from the model Simulink models – the zonal node routing application model referenced throughout the series NXP Model-Based Design Toolbox (MBDT) – S32K3 support and peripheral configuration NXP additional tools – FreeMASTER and S32 Design Studio for build, deployment, and debugging CAN analysis software – monitoring and validating CAN communication LIN analysis software – monitoring and validating LIN communication 3.1 MATLAB® and Simulink® MATLAB® and Simulink® form the foundation of the development environment. They are used to create the zonal node application, implement communication routing logic, configure software behavior, and perform model-based verification activities. The application described throughout this series is developed as a Simulink model and later translated into embedded software using automatic code-generation tools (Embedded Coder®). 3.2 NXP Model-Based Design Toolbox (MBDT) The NXP Model-Based Design Toolbox (MBDT) extends Simulink with hardware-specific support for NXP automotive microcontrollers. For this project, MBDT for S32K3 version 1.8.0 is used. The toolbox provides blocks and configuration interfaces for communication peripherals, timers, digital I/O resources, and other hardware modules available on the target device. It also integrates with the code-generation workflow, allowing Simulink models to be converted into software that can run directly on the S32K3 microcontroller. Note: Installation and configuration instructions are provided in the dedicated article series (How to install .MLTBX). Readers who have not yet installed the toolbox should complete that step before continuing with this series. 3.3 CAN Analysis Software CAN analysis tools are used during development and validation to observe CAN and CAN FD traffic exchanged between the zonal node and other network participants. Typical use cases include: Monitoring transmitted and received CAN frames Verifying CAN-to-CAN routing behavior Measuring message timing and bus utilization Troubleshooting communication issues Examples of commonly used software include PCAN-View, CANalyzer, and CANoe. 3.4 LIN Analysis Software LIN analysis tools are used to monitor communication between the zonal node and LIN-connected edge devices. Typical use cases include: Verifying LIN schedule execution Monitoring frame transmission and reception Validating signal timing and integrity Testing LIN-to-CAN routing scenarios Examples of commonly used software include PLIN-View and LINalyzer. 4 Required Hardware The following hardware components are used throughout the project: S32K344 automotive microcontroller – used to execute the zonal node application S32K344-WB Evaluation Board – used as the development and validation platform CAN analysis hardware – used to monitor and verify CAN/CAN FD communication LIN analysis hardware – used to monitor and verify LIN communication 4.1 S32K3 Microcontroller The S32K3 family provides: Arm® Cortex®-M7 processing cores CAN FD communication interfaces LIN communication support Safety-oriented automotive features Low-power operating modes Rich peripheral connectivity These capabilities make the device suitable for implementing communication aggregation and routing functions within the scope of this project. 4.2 Evaluation Hardware The zonal node application runs on the S32K344-WB Evaluation Board, a development platform based on the NXP S32K344 microcontroller. The board provides access to the communication interfaces and processing capabilities of the target device while offering an integrated platform for software development, debugging, and validation activities. Within the scope of this project, the board is used to execute the routing application and exchange messages with nodes connected through CAN and LIN networks. Its communication interfaces, debugging connectivity, and expansion capabilities make it suitable for evaluating zonal communication architectures and routing scenarios. dragostoma_0-1784547235185.pngㅤ Figure 2. S32K344-WB evaluation board 4.3 Communication Networks The examples presented throughout this series use CAN and LIN networks to demonstrate message forwarding, routing, and protocol translation scenarios. These networks provide the communication backbone between the zonal node, central controller, and edge nodes, and are referenced throughout the upcoming routing and integration articles. 4.4 Network Analysis Hardware Additional hardware tools are used during development and validation to observe network traffic and verify communication behavior. CAN analysis interfaces can be connected to the network to monitor transmitted and received CAN/CAN FD frames, validate routing functionality, and troubleshoot communication issues. LIN analysis interfaces can be used to monitor LIN schedules, frame exchanges, and LIN-to-CAN routing scenarios. These tools provide visibility into network activity and support verification of the communication flows presented in later articles of this series. 5 References Model-Based Design Toolbox (MBDT) Embedded Coder® Documentation MATLAB® and Simulink® Documentation S32K3 Microcontrollers S32K344-WB Evaluation Board 6 Conclusion This article introduced the software and hardware environment used throughout the zonal node project. It presented the development tools, code-generation workflow, and target hardware that support the implementation of the communication routing application. The next article will build on this foundation by examining the internal logic control mechanisms used within the zonal node and how they contribute to communication handling across multiple networks.
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From Simulation to Vehicle Control: Real-Time Decision Making on the S32N55 1 Table of Contents • Introduction • Overview • Context • References • Conclusion 2 Introduction Modern vehicle development increasingly relies on digital validation before physical prototypes are available. Simulation enables rapid testing and iteration, but engineering teams also need to demonstrate how virtual behavior maps to real hardware. In the Hello World demonstrator, this connection is handled by the Main Node application running on the NXP S32N55. The Main Node acts as the central execution point of the demonstrator, transforming vehicle information generated inside MATLAB ® and Simulink ® into decisions and actions that can be observed on physical hardware. By combining Model-Based Design, CAN communication, and centralized decision making, the system creates a bidirectional link between the virtual vehicle and the physical demonstrator. This article explains how the Main Node converts simulation inputs into coordinated vehicle behavior while maintaining synchronization between the digital and physical domains. 3 Overview As introduced in the previous article, the S32N55 functions as the communication hub of the demonstrator, aggregating information from distributed modules and distributing commands throughout the system. Beyond communication, however, the Main Node also serves as the decision-making layer responsible for interpreting vehicle state and translating it into actionable control signals. Developed using the NXP Model-Based Design Toolbox (MBDT), the application is entirely modeled in Simulink and deployed directly onto the target hardware. This workflow enables engineers to focus on vehicle functionality and system behavior while leveraging automated code generation and integrated CAN communication support. The Main Node receives data from simulated and physical sources, maintains a coherent vehicle-state view, runs vehicle-level control logic, and sends commands to the actuator nodes that make up the demonstrator. This centralized architecture reflects the direction of modern software-defined vehicle platforms, where coordination moves from isolated ECUs toward higher-level compute nodes. figure_1_main_node_vehicle_brain_no_header.pngFigure 1. Main Node overview showing how the S32N55 coordinates simulation inputs, vehicle-state processing, and commands to distributed hardware modules. 4 Context The Main Node is positioned between the virtual vehicle environment and the physical hardware modules that form the demonstrator. Driver inputs generated through the Driver-in-the-Loop simulation environment are transmitted over CAN and received by the S32N55, where they are processed alongside feedback arriving from multiple distributed nodes. Commands such as vehicle speed, steering angle, gear selection, braking requests, and lighting controls enter the Main Node from the simulation environment. These inputs are then evaluated by the application and translated into CAN messages that drive the corresponding hardware modules. This architecture enables the physical demonstrator to mirror the behavior of the virtual vehicle. When the simulated vehicle accelerates, the speed command is interpreted by the Main Node and forwarded to the motor control subsystem. Steering-wheel movements are translated into steering-angle commands for the steering module, while lighting commands activate headlights, fog lights, hazard lights, and turn indicators on the physical hardware. figure_2_virtual_physical_synchronization_no_header.pngFigure 2. System context illustrating the Main Node as the bridge between the virtual vehicle environment and the physical demonstrator hardware. The Main Node can be driven either by the Driver-in-the-Loop simulation or by the External Control model. In both cases, the command source publishes the same DBC-defined CAN frames, so the S32N55 receives speed, steering, brake, gear, and lighting commands through the same interface. This allows the same deployed application to be exercised from two sources without changing the Main Node software. This approach is especially useful during integration, demonstrations, and incremental validation. Engineers can exercise the Main Node and the downstream actuator modules even when the complete virtual environment is not active, while still preserving the exact communication contract used by the full system. As a result, the application can be validated against two different input sources without changing the deployed software on the board. Rather than acting as a simple gateway, the Main Node continuously evaluates received information and executes vehicle-level decisions. One example is the processing of motor feedback data, where information from multiple motors is combined to derive a representative vehicle speed used throughout the system. Centralizing this functionality simplifies system coordination while ensuring consistency across all connected modules. Gear selection is handled as part of this centralized decision layer. The incoming gear command is interpreted as a driving mode that affects how the requested speed is applied: Park and Neutral block motion commands, Reverse changes the sign of the velocity reference, and Drive or Sport propagate the requested speed as a forward-driving command. This keeps speed-control behavior aligned with the selected driving mode while preserving the same driver-input signal set. The target-speed command is computed from the requested speed reference, the selected gear mode, the reported vehicle speed, and the effective brake command. Motor feedback is fused into a representative reported speed, which provides the actual-speed reference used during braking decisions. Under normal driving conditions, the requested target speed passes through the gearbox-aware logic and is converted into the motor-speed command sent over CAN. When braking is active, the Main Node bases the outgoing command on the detected speed and brake value, reducing the command until the vehicle is considered stopped. The Main Node also hosts the demonstrator's automated emergency braking functionality. Parking sensor nodes continuously report obstacle distances over CAN. The application evaluates these measurements and determines whether an object has entered a predefined safety zone. When this condition is met, the braking command issued by the driver can be overridden and replaced with an emergency braking request generated by the system. Picture1.pngFigure 3. Parking sensors in action detecting nearby obstacles and providing distance feedback used by the Main Node to support emergency braking decisions. An important aspect of this implementation is that the braking behavior is reflected across both domains. The physical hardware responds to the braking request, while the simulation environment can receive corresponding vehicle-state updates through the same CAN-based loop. This closed-loop behavior demonstrates bidirectional interaction between simulation and embedded execution, allowing safety-related functionality to be validated in a realistic environment before a full vehicle prototype is available. figure_4_aeb_closed_loop_no_header.pngFigure 4. Closed-loop emergency braking flow showing how parking sensor feedback can trigger an automated braking request across both the physical and simulated domains. CAN communication is the key enabler of this architecture. Every subsystem communicates through DBC-defined interfaces, allowing functionality to be distributed across multiple independent nodes while preserving a consistent and scalable communication framework. The shared DBC approach ensures that signal definitions remain synchronized across all parts of the demonstrator. To support this workflow, MathWorks Vehicle Network Toolbox ™ provides direct integration between MATLAB ® , Simulink ® , and CAN communication interfaces. DBC files can be used directly throughout the development process, simplifying signal management and ensuring consistency across the virtual vehicle, the Main Node, and all peripheral modules. As the demonstrator grows to include additional functionality, the same network definition can be reused across all participating systems, reducing integration effort and helping accelerate development. Note: The combination of NXP Model-Based Design Toolbox and MathWorks Vehicle Network Toolbox creates a workflow in which vehicle behavior, communication interfaces, and deployed software remain aligned from modeling through system integration. figure_5_shared_dbc_workflow_no_header.pngFigure 5. CAN and DBC workflow showing how shared signal definitions keep the virtual vehicle, Main Node, and distributed hardware modules synchronized. 5 References NXP Model-Based Design Toolbox (MBDT) NXP S32N Vehicle Super-Integration Processors Vehicle Network Toolbox ™ NXP Model-Based Design Toolbox Community 6 Conclusion The Main Node demonstrates how a centralized compute platform can act as more than a communication gateway. Running on the NXP S32N55, it combines signal aggregation, decision making, and command distribution into a single application that coordinates the entire demonstrator. By transforming simulation-generated inputs into physical vehicle behavior and feeding real-world information back into the virtual environment, the Main Node creates a practical closed-loop development platform. Together, NXP Model-Based Design Toolbox, MathWorks Vehicle Network Toolbox, and CAN-based communication enable rapid iteration, simplified integration, and efficient validation of vehicle functionality across simulated and physical domains.
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Zone Node Logic Control (Main model overview) 1 Table of Contents • Introduction • Black-Box Overview • Simulink Model Overview • Inputs • Algorithm • Outputs • References • Conclusion 2 Introduction This article explains the internal behavior of the Zone Node by opening the component "black box" and describing how information flows through the application. The objective is to provide a functional understanding of the model, starting from the incoming inputs, continuing through the internal processing logic, and concluding with the generated outputs. The Zone Node acts as an intermediary between the Central Controller and the Edge Nodes located within a vehicle zone. While previous articles introduced the component and the development environment, this article focuses on the application's behavior and the responsibilities performed by the embedded software. This article focuses on the functional behavior of the Zone Node and explains how information flows through the component. Detailed aspects such as CAN routing implementation, LIN scheduling mechanisms, peripheral configuration, and communication stack integration will be covered in dedicated articles later in the series. 3 Black-Box Overview From a system perspective, the Zone Node behaves as a communication gateway and data aggregation component. It receives information from different communication networks, processes that information according to predefined routing rules, and forwards the resulting data to other parts of the system. At a high level, the component can be represented as: dragostoma_1-1784789757571.pngㅤ Figure 1. Black-Box Overview The Zone Node does not implement vehicle-level control strategies. Functions such as braking decisions, steering calculations, or vehicle state management remain the responsibility of higher-level controllers. Instead, the Zone Node focuses on: Receiving messages from the Central Controller Receiving messages from Edge Nodes Acquiring data from local LIN-connected devices Routing information between networks Aggregating and forwarding data Providing monitoring and diagnostic information The result is a reusable communication component that can be deployed in different vehicle zones while maintaining the same overall behavior. 4 Simulink Model Overview The Zone Node functionality is implemented as a Simulink model organized around communication, routing, scheduling, and diagnostic subsystems. From a model perspective, the application can be divided into four logical areas: Input handling Routing and processing Communication scheduling Outputs and diagnostics dragostoma_6-1784790002961.pngㅤ Figure 2. Main Simulink Application The input layer receives information from CAN and LIN communication interfaces and makes it available to the application logic. The processing layer evaluates incoming messages and determines how they should be handled. The scheduling layer manages periodic communication activities, while the output layer is responsible for forwarding messages and generating diagnostic information. This separation helps keep the model modular and makes it easier to extend the application with additional communication paths or Edge nodes without changing the core routing behavior. 5 Inputs The Zone Node receives information from three main categories of inputs. 5.1 CAN Network Inputs CAN communication represents the primary source of information processed by the Zone Node. Messages can originate from: Central Controller Lighting modules Steering modules Motor control modules Other Edge Nodes within the zone Typical examples include: Vehicle commands Status reports Diagnostic information Fault indications Actuation requests The exact set of messages depends on the specific Edge Nodes connected to the zone. 5.2 LIN Device Inputs The Zone Node also acquires information from LIN-connected devices. In the reference implementation, LIN communication is used to retrieve parking sensor information. The Zone Node periodically requests data from the LIN device and receives measurement values in response. Examples include: Front parking distances Rear parking distances Other LIN-based sensor information From the perspective of the Zone Node, LIN data behaves similarly to any other external input source. 5.3 Configuration Inputs Before normal operation begins, the Zone Node initializes its communication interfaces and loads the required configuration information. Examples include: CAN interface configuration LIN interface configuration Communication schedules Routing rules These parameters define how the application interacts with the surrounding networks. 6 Algorithm Internally, the Zone Node performs three main processing activities. 6.1 Message Reception The first step consists of collecting incoming communication data. Whenever a message arrives, the application captures: Communication source Message identifier Data payload Message length This information becomes available to the routing and aggregation logic. dragostoma_0-1784789836990.pngㅤ Figure 3. CAN Reception Pipeline 6.1.1 Model Representation of Message Reception Within the Simulink model, message reception is implemented using communication interface blocks and dedicated processing subsystems that capture incoming network events and make the received information available to the rest of the application. dragostoma_7-1784790035889.pngㅤ Figure 4. CAN Reception Main Flow dragostoma_8-1784790056735.pngㅤ Figure 5. CAN Reception Subsystem At a high level, the reception subsystem performs three actions: Detects incoming communication events Stores the received information Makes the information available to the routing logic This allows the routing algorithm to operate independently from the physical communication interface. 6.2 Message Routing Message routing represents the primary responsibility of the Zone Node. The routing logic determines the origin of each incoming message and forwards it to the appropriate communication interface. The behavior can be simplified as: dragostoma_1-1784789857331.pngㅤ Figure 6. Bidirectional CAN Routing Messages received from the Central Controller are forwarded toward the Edge Nodes, while messages originating from Edge Nodes are routed back toward the Central Controller. The routing mechanism remains independent of the actual application payload, allowing the same software architecture to support different message sets and vehicle functions. 6.2.1 Model Representation of Routing Logic The routing functionality is implemented as a dedicated subsystem responsible for deciding where each received message should be forwarded. dragostoma_9-1784790120286.pngㅤ Figure 7. Message Routing Main Flow dragostoma_10-1784790141963.pngㅤ Figure 8. Message Routing Subsystem The routing subsystem evaluates the origin of the received message and selects the appropriate destination interface. At this level, the application does not interpret individual signal meanings; it simply ensures that information reaches the correct communication network. This approach keeps the routing layer independent from application-specific functionality and allows the same architecture to be reused across different deployments. 6.3 LIN Scheduling and Data Acquisition In parallel with CAN routing, the Zone Node periodically acquires data from LIN-connected devices. The sequence follows a simple request-response model: dragostoma_2-1784789896373.pngㅤ Figure 9. LIN Parking Acquisition Cycle This mechanism allows information originating on a LIN network to become available to the rest of the vehicle through CAN communication. 6.3.1 Model Representation of LIN Scheduling Periodic LIN communication is implemented using a dedicated scheduling subsystem. dragostoma_11-1784790193540.pngㅤ Figure 10. LIN Scheduling Main Flow The scheduler periodically requests data from LIN-connected devices, waits for a response, and updates the application data used by the rest of the system. Depending on the communication requirements, the scheduler may manage one or more request-response sequences while maintaining a deterministic execution pattern. 6.4 High-Level Data Flow The internal data flow implemented by the Zone Node can be summarized as follows: dragostoma_3-1784789923452.pngㅤ Figure 11. Zone Node Data Flow 7 Outputs The Zone Node produces several categories of outputs that are consumed by different parts of the vehicle architecture and by development tools used during validation and debugging. 7.1 Routed CAN Messages The primary outputs of the Zone Node are CAN messages forwarded between communication networks. Examples include: Commands sent from the Central Controller to Edge Nodes Status information returned from Edge Nodes Diagnostic messages Fault reports Configuration updates By routing these messages between communication domains, the Zone Node maintains communication between the central controller and the devices located within its assigned vehicle zone. 7.2 Aggregated Device Data In addition to forwarding CAN traffic, the Zone Node generates CAN messages containing information acquired from locally connected devices. One example is parking sensor data collected through a LIN interface and republished on CAN. This allows the Central Controller to access the information without requiring direct interaction with the LIN-connected device. The process can be summarized as: dragostoma_4-1784789955066.pngㅤ Figure 12. LIN-to-CAN Data Path This approach creates a unified communication interface while hiding the complexity of the underlying network topology. 7.3 Diagnostic Outputs The Zone Node generates diagnostic information that is useful during development, system integration, and troubleshooting activities. Examples include: Communication counters Status variables Network activity indicators Communication statistics Device data used for monitoring purposes These outputs provide insight into the current behavior of the application and can be accessed through development tools such as FreeMASTER. 7.4 Visual Indicators In addition to communication outputs, the Zone Node drives visual indicators available on the evaluation hardware. The on-board LEDs provide immediate feedback regarding: Message reception activity Message transmission activity LIN communication activity Application execution status Although these indicators are not used by the vehicle itself, they simplify application bring-up and validation by providing a quick visual confirmation that the software is operating correctly. 7.5 Output Destinations The outputs generated by the Zone Node are consumed by several different system components. Central Controller Receives: Status information from Edge Nodes Aggregated sensor data Diagnostic information generated within the zone Edge Nodes Receive: Commands originating from the Central Controller Configuration and control messages forwarded through the Zone Node Local Devices Receive: Periodic requests issued by the Zone Node Communication messages required to acquire local measurements Development Tools Receive: Monitoring variables Communication statistics Diagnostic information used for debugging and validation 7.6 High-Level Output Flow dragostoma_5-1784789974523.pngㅤ Figure 13. System Topology This output structure allows the Zone Node to act as a communication intermediary while simultaneously providing visibility into the behavior of the system during development and validation. 8 References NXP Model-Based Design Toolbox (MBDT) S32K3 Microcontroller Documentation S32K344-WB Evaluation Board Documentation 9 Conclusion This article described the internal behavior of the Zone Node by examining its inputs, processing logic, and outputs. By presenting the component as a functional black box, it explained how information is received, routed, aggregated, and distributed throughout the system without focusing on implementation-specific details. The next articles in the series will build upon this foundation by examining individual communication paths in more detail, including CAN-to-CAN routing, LIN-to-CAN routing, and the techniques used to validate and troubleshoot communication behavior.
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Ara2_Model_Zoo_Compilation_Deployment_Testing_Guide This document provides an end-to-end example for setting up the Ara2 compilation environment, compiling the YOLOv8L ONNX model with the Model Zoo, deploying the compiled model to an i.MX95 target, running inference and performance tests, and reviewing the key YAML fields that must be updated when adapting the flow to another model of the same type.
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Demystifying the PCIe and CPU address space translation in Linux lspci output on iMX95EVK as PCIe RClspci output on iMX95EVK as PCIe RC Please take a good look at the snippet above. It is taken from the console of iMX95 after executing 'lspci' on a specific PCIe device[iMX8MM as PCIe EP] that gets enumerated as BDF[Bus Device Function] 01:00.0. This blog attempts to debunk the mystery revolving around the "Memory at " info of the lspci output. We will discuss what this address is, why it is used and its relevance in the PCIe world. This blog will focus on the following agendas: - 1. PCIe parent and child relationship in Linux Device Tree 2. What is CPU and PCIe address space and the need for address space translation?  3. Assigning resources to a PCIe device in Linux 4. How is address space translation carried out in Linux PCI Subsystem?   PCIe parent and child relationship in Linux Device Tree In the Linux device tree, PCIe parent and child relationship defines how PCIe Root Complex and Endpoints are positioned in the system. A PCIe parent node in the device tree represents a PCIe controller (Root Complex / Host-Bridge). Taking reference from a PCIe node present in the device tree source of imx95: -   pcie@4c300000 {                         compatible = "fsl,imx95-pcie";                         reg = <0x00 0x4c300000 0x00 0x10000 0x00 0x4c360000 0x00 0x20000 0x00 0x60100000 0x00 0xfe00000>;                         reg-names = "dbi\0atu\0config";                         #address-cells = <0x03>   …  } pcie@4c300000 represents a Designware PCIe controller Root Complex which is a parent to the devices/bridge that will be connected to it. -- 'compatible' property identifies the specific PCIe controller. Its corresponding driver resides in drivers/pci/controller/dwc/pci-imx6.c -- 'reg' property specifies the memory mapped registers of the PCIe controller. Child nodes under PCIe RC represent devices on the PCIe bus. They can be fixed function devices like Wi-fi, Ethernet, NVMe or they can be PCIe bridges which further can have devices connected to it. Taking reference from 'arch/arm64/boot/dts/freescale/imx95.dtsi'   pcie_4ca00000: pcie@4ca00000 {                         compatible = "pci-host-ecam-generic";                         reg = <0x0 0x4ca00000 0x0 0x100000>;                         /* Must be 3. */              …              …              enetc_port0: ethernet@0,0 {                                 compatible = "fsl,imx95-enetc";                                 reg = <0x000000 0 0 0 0>;                                 clocks = <&scmi_clk IMX95_CLK_ENET>,                                          <&scmi_clk IMX95_CLK_ENETREF>;                                 clock-names = "ipg_clk", "enet_ref_clk";                                 nvmem-cells = <&eth_mac0>;                                 nvmem-cell-names = "mac-address";                                 status = "disabled";                         }; }   ethernet@0,0 is a PCIe device at bus 0, device 0, function 0. It is a child of PCIe RC which is memory mapped at 0x4ca00000   These child devices/bridges can either be dynamically discovered using PCI enumeration or they can be statically described in a device tree as seen in the device-tree snippet above in which "ethernet@0,0" entry statically tells the RC that the ethernet child device is connected to it. These child nodes are nested within a PCI parent node of the device tree as seen in the above example.   What is CPU and PCIe address space and the need for address space translation ? CPU address space is the system's physical memory map as seen by the processor. Example of CPU Physical Address Space viewed by Cortex-A55 on iMX95:-   Start address      End address    Module 0x48000000       0x4812FFFF    GIC Programming registers 0x4AA00000      0x4AAFFFFF    Neutron SRAM 0x4AC10000      0x4AC1FFFF    Camera domain block control 0x4E080000       0x4E08FFFF    DDR Controller This address space is kind of a global system view which is managed by system firmware/OS. These addresses are fixed by hardware-design. On the other hand, PCIe address space is local to PCI bus, managed by PCIe subsystem. The  addresses in this space are dynamically assigned. An example of PCIe address space that could look like the following:- 0x00000000   -    0x0FFFFFFF 0x10000000   -    0x1FFFFFFF 0x20000000   -    0x2FFFFFFF It is evident from the above explanation that CPU and PCIe address space operate in a separate and independent address domains. So the CPU cannot access the space of PCIe device unless a translation mechanism is in place. In one of the upcoming sections we will get to that as well but please spare a few minutes and ponder the question below:- Question : Why do you need separate address spaces for CPU and PCIe? Answer : One of the major reasons is modularity. We have separate spaces so that PCIe devices can be designed independently of the CPU architecture. Same card will work in different system. It will always have the flexibility of CPU remapping the PCIe space as and when needed. Also, different address spaces prevent devices to access arbitrary system memory. Based on the discussion in this section, it is evident that the PCIe address space is inherently different from the CPU address space and truth be told- it has its advantages. Therefore we need an entity to translate to/fro these address spaces. Here comes 'iATU' - Internal Address Translation Unit. On iMX SOCs, these hardware units are responsible for carrying out the address translation. These units are a part of Synopsys DesignWare PCIe Controller, providing programmable address translation windows for inbound and outbound transactions. For the readers who are uninitiated on the inbound and outbound transactions in pcie, please spare some time go through this technical blog - Understanding PCIe Outbound/Inbound windows with a use-case - NXP Community Note: - Address translation simply ensures that the CPU can access a PCIe device's memory and vice-versa. Up until here, the readers must have got a basic picture of PCIe Address Translation. Before jumping into the nitty-gritty of this translation in the Linux PCI subsystem, let's discuss how the resources are assigned to a PCIe device.   Assigning resources to a PCIe device in Linux PCIe devices do not have a direct CPU instruction interface so they communicate through memory-mapped regions. Devices need memory for DMA operations or for MSI/MSIX interrupts. Different devices have different needs, so resources in PCIe could be MMIO where device registers are mapped or memory regions needed for DMA transfer. In linux, pci_assign_resource function of PCI subsystem is responsible for assigning IO and memory resources to the PCIe devices during system initialisation after PCIe devices are enumerated. It is called for all the devices on a PCI bus and based on the PCI devices' resource requirement, it assigns them. But how does the PCI subsystem in linux figure out what resources does the PCIe devices need ? - Every PCIe device has a configuration space defined by the PCIe specification. This includes   BAR[Base Address Registers] - To indicate what type of resource[IO/Mem] does  the device needs and the size of resource. Capabilities - To broadcast the device capabilities such as MSI Interrupts, ASPM low power states etc. Reading the BARs from the PCIe device will tell us what kind and size of the resources are needed by the device. // To determine the size of resource from the BAR of PCIe device:- Step-1: Write all 1's to the target BAR register. Step-2: Read back the value and clear the lower 4 bits (for a memory BAR) or 2 bits (for an I/O BAR), as these are status bits, not part of the size calculation Step-3 Perform Bitwise NOT on the value and add 1 to it. Step-4: The returned value indicates the size. Taking an example to understand this:- Let's assume that after reading back the value in Step-2 above, the BAR returns 0xFFFFF000. The lower 4 bits are already cleared. Step-3  we perform bitwise NOT on the value -> ~(0xFFFFF000) = 0x00000FFF Adding 1 to it : 0x00000FFF + 1 = 0x00001000 The obtained value 0x1000 = 4096 bytes indicates the size, meaning the BAR requires a 4KB memory region. // To determine the type of resource from the BAR of PCIe device:-   A Base Address Register (BAR) in PCI configuration space: Bit 0 → Resource type: 1 = I/O space 0 = Memory space For memory BARs: 00 = 32-bit 10 = 64-bit Bits 1–2 → Addressing type: Bit 3 → Prefetchable flag Interpreting the value 0xFFFFF000, we get:-   Bit 0 = 0 → Memory space Bits 1–2 = 00 → 32-bit address Bit 3 = 0 → Prefetchable Upper bits → Base address (after masking)   pci_read_bases [drivers/pci/probe.c] in linux PCI subsystem is responsible to figure out the BAR memory size and type requirement during device enumeration. Needless to say, the above sequence of writing to the Endpoint's BAR and identifying the size and type of resource is executed on the PCIe RC. We have the following setup :- iMX95 <------> iMX8MM [RC]                     [EP] After PCIe RC has the size of the BAR that is required, the pci_assign_resource function allocates a memory range and then sets up translation from this memory range to the PCIe address space. we started this blog with a snippet, that shows the following lspci log:-   2.png2.png Referring to the above, please note that the RC driver has allocated: - 0x910100000 - 0x910110000 as the non-prefetchable memory address range, size=64KB The above memory address range is in the PCIe 1 Outbound space memory mapped on iMX95 SoC: -   3.png3.png The range 0x910100000 - 0x910110000 will be mapped to the PCIe address space of the End-point. This essentially means that if the cpu generates any address in between this range [inclusive of start and end-address], a PCIe TLP will be sent by the PCIe controller on the RC to the End-point on the bus. It could be a read or write to the memory of Endpoint. The address to write/read would be decided based on the address space translation. We shall discuss in-detail how this translation is exercised in the linux kernel in the next section.   How is address space translation carried out in Linux PCI Subsystem?   We start with some important questions: - Where is the range 0x910100000 - 0x910110000 specified ? How does the kernel know that it has to map the PCIe 1 Outbound space and not PCIe2 Outbound space or any other address space for that matter? -- Like all good things in Linux, this also starts with a 'device tree binary'. A dtb is passed by Uboot to the kernel so that it could get the hardware description of our board. Since we are using Torradex 's Verdin iMX95 EVK Board as Root Complex, this is the dtb that we are using - imx95-19x19-verdin-adv7535.dtb I will be attaching a working dtb with this blog so that the readers can use it if needed. This dtb includes - arch/arm64/boot/dts/freescale/imx95.dtsi Let's have a look at a particular pcie node of interest: -   4.png4.png 'ranges' property is the answer to the questions that were asked in this section earlier.  - This property defines the address translation rules between the parent's address space and the child PCI address space.   Note:- This blog focuses only on 'ranges' property since it is relevant to our discussion. So the readers are advised to look elsewhere if they want to understand other device-tree properties of the PCIe node.  Let's decode the ranges property : It has the following format:-      3 cells               2 cells             2 cells             So one entry will have 7 cells. In our dtsi we have 2 entries. 1st is for IO space translation and the 2nd is for Mem space translation. Referring to the second entry  :-   0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000 |------PCI address---------------| |-CPU address-| |---PCI size---|   The above gives us the following info: - MEM Space prefetchable <   0x82000000 0x00 0x10000000   // PCIe address: 0x10000000   0x09 0x10000000              // CPU/system address: 0x910000000   0x00 0x10000000              // Size: 256MB >; 0x82000000 = 1000 0010 0000 0000 0000 0000 0000 0000   Bits 31–30 (10) → Configuration space type: This indicates memory space. Bit 29 (0) → Non-relocatable Bit 28 (0) → Non-prefetchable  (0 means non-prefetchable) Bits 27–24 (0010) → Address space type = Memory So, 0x82000000 means: PCI memory space Non-prefetchable 32-bit address space Note:- For those of you wondering why lspci output mentions [size=64K] and dts says 256 MB. This is because 256MB is the maximum address space available for the PCIe devices. It is upto the Endpoint device, how large address space does it require and accordingly it gets allocated. Similary IO space translation is also created from the 1st entry in 'ranges':- < 0x81000000 0x00 0x00 → PCI I/O address: 0x00000000 0x00 0x6ff00000 → CPU/system address: 0x6ff00000 0x00 0x100000 → Size: 1MB >;   we observe the same in the dmesg output of iMX95 Verdin EVK Linux console:-   5.png5.png So the MEM Space mapping is from CPU Address 0x910000000 - 0x091fffffff translated to PCIe Address 0x10000000 - 0x1fffffff It is only fair that we mention the driver that uses the 'ranges' property. The 'ranges' property get parsed in "pci_parse_request_of_pci_ranges -> devm_of_pci_get_host_bridge_resources" of "drivers/pci/of.c" devm_of_pci_get_host_bridge_resources, for each range automatically  manages the memory allocated for these resources. It ensures that the resources are freed when the device is detached or the driver is removed. We have got the answer what & why is the cpu and pci address range the way it is. But in the lspci, you see 0x910100000 and not 0x910000000 which is what the intended start range is supposed to be as per the dtb. Why is that ? To answer this - we need to go back to the PCIe device enumeration. During PCIe enumeration, in the linux PCI driver the bar resources were determined like we had discussed earlier and then the PCI core driver may assign addresses keeping alignment requirements in mind that is why EP's BAR0 was assigned a PCI bus address as 0x10100000 with a 1MB[0x100000] offset from 0x10000000. And keeping the device tree pci translation window in mind:- 0x10100000 translates to 0x910100000 This translation doesn't happen on its own. Device tree binary just mentions the translation window specifics such as the CPU address space to translate to and the PCI address space to translate from. The actual translation is done via iATU. This is done in the dw_pcie_iatu_setup function of drivers/pci/controller/dwc/pcie-designware-host.c by creating the outbound window using dw_pcie_prog_outbound_atu function. Translation is configured on the RC successfully but there is still something missing. .. .. Inbound window !! Without an inbound window on the Endpoint i.e iMX8MM, the writes/reads to 0x910100000 would be meaningless. On iMX8MM we are using PCI Endpoint test driver which is quite popular in linux community and I would urge the readers to visit this page if they want more info - 9. PCI Endpoint Framework — The Linux Kernel documentation pci_epc_map_addr function in drivers/pci/endpoint/pci-epc-core.c creates inbound window by mapping PCI address [0x10100000] to physical address in EP's memory. That's how the reads and writes go through. If there's no Inbound window configured, something like this unfolds in case of read:-   6.png6.png So now everything is set up. Translation windows are configured in the PCI drivers and you are at linux console. The following sequence unfolds when the CPU issues a memory read:-   7.png7.png In case of memory writes:- 8.png8.png The following happens on the Endpoint: - 9.png9.png The beauty is that this entire translation happens transparently in hardware - your driver just reads/writes to the CPU address, and the PCI host controller handles all the translation automatically! -- How do we test the Address Translation ?   To test reads and writes, either we can make some changes in the driver itself or use devmem5 user-space binary. We are going to make minor driver side changes on iMX8MM and use devmem5 on the RC. iMX8MM is the PCIe Endpoint and we are using end-point test driver to configure it as such. If  you want to do the same, please follow this blog - Enabling PCIe End-point framework on iMX95 torradex board and iMX8MM EVK - NXP Community On the contrary if you want to make iMX95 as RC and iMX8MM Endpoint, feel free to follow this blog - How to configure iMX95EVK as PCIe Endpoint and test it using PCIe Endpoint Test Framework - NXP Community Two things we are going to do next: - 1. On iMX8MM EP, we are going to write some random values  in the drivers/pci/endpoint/pci-epf-core.c, make the following changes in pci_epf_alloc_space function: -     10.png10.png 'space' is the virtual address and 'phys_addr' is the physical address that is contiguous. Please note that it is a crude way to test this translation. There are better ways to do it. Build the kernel after the changes and boot the board with it. Make iMX8MM an Endpoint using PCI Endpoint Test Framework. 2. On iMX95 Verdin EVK [PCIe RC], we are going to read the address 0x910100000 using devmem5 to verify that we can observe the same data on the RC.   11.png11.png That's it for today. This was a long blog and if you feel overwhelmed by the details, please feel free to drop in the DMs or comments so that I can try to make it easier. Until next time! Gaurav Sharma   IMX95EVK
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LPC55S28 CASPER ECC 乗算実行時間 以下のコードが計測時間内に実行されることが想定されているのか、それとも設定に何か問題があって実行が非常に遅くなっているのかを突き止めようとしています。このコードは、kCASPER_ECC_P256を使用して指定された秘密鍵から公開鍵を生成する関数の一部です。 以下のコードは、GPIOトグルを使用して実行時間を計測します。Set および Clear GPIO 呼び出しの間には 337 ミリ秒かかります。これは、この演算におけるハードウェアアクセラレーションによる計算処理としては遅いように思われる。これは想定内のことでしょうか?私のMCUのコアクロックは148MHzです。CASPERエンジンのクロックソースを選択して処理速度を向上させる方法はありますか? /* Base Generator Point G(x, y) for secp256r1 in 32-bit Little-Endian word arrays */ static const uint32_t G_x_le[8] = { 0xD898C296, 0xF4A13945, 0x2DEB33A0, 0x77037D81, 0x63A440F2, 0xF8BCE6E5, 0xE12C4247, 0x6B17D1F2 }; static const uint32_t G_y_le[8] = { 0x37BF51F5, 0xCBB64068, 0x6B315ECE, 0x2BCE3357, 0x7C0F9E16, 0x8EE7EB4A, 0xFE1A7F9B, 0x4FE342E2 }; uint32_t scalar_le[8]; uint32_t Q_x_le[8]; uint32_t Q_y_le[8]; /* Copy Big-Endian private scalar and convert to Little-Endian for CASPER */ memcpy(scalar_le, key_buffer, 32); swap_endian_32((uint8_t *)scalar_le); /* 1. Initialize CASPER coprocessor */ CASPER_Init(CASPER); CASPER_ecc_init(kCASPER_ECC_P256); HW_DB_PinSet(); /* 2. Compute Q = d * G using CASPER hardware */ CASPER_ECC_SECP256R1_Mul( CASPER, Q_x_le, Q_y_le, G_x_le, G_y_le, scalar_le ); HW_DB_PinClear(); 回复: LPC55S28 CASPER ECC Multiply Execution Time こんにちは、 @guitardenver 同じ操作を、150MHzで動作するLPC55S28 EVK上でMCUXpresso SDK CASPER例を用いて測定しました。CASPER_ECC_SECP256R1_Mul() を 1 回呼び出すのに約 2410 万 CPU サイクルが必要で、これは約 160 ミリ秒の実行時間に相当します。 この結果に基づくと、アプリケーションで測定された337msは、特に追加のキーフォーマット、データ変換、初期化、デバッグビルドのオーバーヘッドが含まれれば、不合理とは思えません。 CASPERは、ユーザーが設定可能な別のクロックソースを提供していません。実行時間は主にCASPARアクセラレータを利用したECCソフトウェア実装によって決定されます。 BR ハリー
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KW47: Relationship between WDOG Wait/Stop modes and Power Modes (Sleep/Deep Sleep) Hello, I am reading the KW47 Reference Manual and I am confused about the relationship between the WDOG low-power modes and the system power modes. In the WDOG chapter, the Control and Status register contains the following bits: - WAIT: "Enables WDOG to operate when the chip is in Wait mode." - STOP: "Enables WDOG to operate when the chip is in Stop mode." The WDOG chapter also states that: - The selected WDOG clock source must remain active in Stop mode. - For Debug and Stop modes, a clock source other than the bus clock must be used. On the other hand, the Power Modes chapter describes: Sleep mode: - CPU execution halted - Core clock gated off - System clock and bus clock may continue running Deep Sleep mode: - Core clock gated off - System clock gated off - Bus clock gated off Based on these descriptions, it seems reasonable to interpret: - Wait mode ≈ Sleep mode - Stop mode ≈ Deep Sleep mode However, I have not been able to find any explicit statement in the Reference Manual confirming this mapping. My questions are: 1. Does WDOG Wait mode correspond to the Power Mode Sleep mode on KW47? 2. Does WDOG Stop mode correspond to the Power Mode Deep Sleep mode on KW47? 3. Or are Wait/Stop WDOG-specific CPU states that are different from the SoC power modes? 4. Is there any Reference Manual section or Application Note that explicitly describes this relationship? Thank you for your help. Re: KW47: Relationship between WDOG Wait/Stop modes and Power Modes (Sleep/Deep Sleep) Hello, hope you are doing well.   The terminology used in the KW47 Reference Manual is consistent with interpreting the WAIT and STOP fields in the WDOG control register as references to chip/core low-power states, rather than as WDOG-specific CPU states. I would describe the relationship as functional correspondence rather than a strict equivalence. In that sense, WDOG WAIT corresponds to the Wait/Sleep class condition, where CPU execution is halted but the system and bus clocks may remain available. WDOG STOP corresponds to the Stop/Deep-Sleep class condition, where the core, system, and bus clocks are gated and the watchdog can continue only if it is configured to use a clock source that remains active in that mode.   Best regards, Sofia. Re: KW47: Relationship between WDOG Wait/Stop modes and Power Modes (Sleep/Deep Sleep) Hello Sofia, Thank you for your previous explanation. Based on your reply, my understanding is: - WDOG WAIT corresponds to a Wait/Sleep-class low-power condition. - WDOG STOP corresponds to a Stop/Deep-Sleep-class low-power condition. - The relationship is a functional correspondence rather than a strict one-to-one mapping. After reviewing the KW47 Reference Manual again, I found the following section: 28.4 Module operation in low power modes Table 225: Cortex M33 core module operation in low power modes For WDOGx, the table shows: - Sleep : ON - Deep Sleep : Optional - Power Down : Optional - Deep Power Down : OFF From this table, I interpreted that WDOG operation can be configured in at least Deep Sleep and Power Down modes. To better understand the behavior, I performed a test using a KW47-Loc evaluation board. Test conditions: - WDOG enabled - WDOG refresh is performed from vApplicationIdleHook() - PWR_EnterLowPower() is executed from FreeRTOS vPortSuppressTicksAndSleep() - Observe whether a watchdog reset occurs after entering the low-power state Test results: Case 1 WAIT=0, STOP=0 → No watchdog reset occurred Case 2 WAIT=1, STOP=0 → Watchdog reset occurred Case 3 WAIT=0, STOP=1 → No watchdog reset occurred My interpretation is that when a watchdog reset occurred, the device entered a low-power state where vApplicationIdleHook() was no longer executed while the watchdog continued running and eventually timed out. However, a watchdog reset occurred only when WAIT=1 and STOP=0, while no watchdog reset occurred when STOP=1. Because of this result, I am having difficulty understanding how the WAIT and STOP bits are actually applied to watchdog operation during low-power modes. Could you please clarify the following points? 1. When the device enters a low-power mode through PWR_EnterLowPower(), is WDOG operation controlled by the WAIT bit or the STOP bit? 2. Does the observed result indicate that the device is actually entering Sleep mode rather than Deep Sleep mode, or should it be interpreted as entering Deep Sleep mode? 3. Does the STOP bit correspond to the Deep Sleep mode described in the Power Modes chapter, or does it refer to a different low-power state? 4. How should the following entries in Table 225 be interpreted with respect to the WDOG WAIT and STOP control bits? - WDOGx : Optional (Deep Sleep) - WDOGx : Optional (Power Down) Thank you for your support. Re: KW47: Relationship between WDOG Wait/Stop modes and Power Modes (Sleep/Deep Sleep) @sofiaurueta  I performed some additional testing and updated the post with my findings above. Could you please let me know if my interpretation is correct? Thank you. Re: KW47: Relationship between WDOG Wait/Stop modes and Power Modes (Sleep/Deep Sleep) Hi @hyama , I apologize for the late reply.   Are you testing with any example from the SDK? How are you confirming that the device is entering Deep Sleep mode? From the behavior you described, it is possible that the device is only entering Sleep mode. If the device were entering Deep Sleep, the results would be the opposite: STOP=1 (Case 3) should have caused the timeout, and WAIT=1 (Case 2) should have had no effect. The fact that it is WAIT=1 that triggers the reset is consistent with the device entering Sleep mode, not Deep Sleep.   Answering your questions: 1. When the device enters a low-power mode through PWR_EnterLowPower(), is WDOG operation controlled by the WAIT bit or the STOP bit? CS[WAIT] and CS[STOP] are independent controls for independent modes where CS[WAIT] controls WDOG operation in Sleep mode, and CS[STOP] controls WDOG operation in Deep Sleep mode. In the case that the device enters Sleep mode, CS[WAIT] is the active control. CS[STOP] has no effect here because Deep Sleep is not entered. If the device were instead configured to enter Deep Sleep, CS[STOP] would be the active control.   2. Does the observed result indicate that the device is actually entering Sleep mode rather than Deep Sleep mode, or should it be interpreted as entering Deep Sleep mode? The results are consistent with Sleep mode entry and are inconsistent with Deep Sleep. Based on the three test cases, Sleep mode is being entered.   3. Does the STOP bit correspond to the Deep Sleep mode described in the Power Modes chapter, or does it refer to a different low-power state? Based on the documentation, CS[STOP] corresponds to Deep Sleep, and the behavior observed in the tests is consistent with this (assuming that Deep Sleep was not entered).   4. How should the following entries in Table 225 be interpreted with respect to the WDOG WAIT and STOP control bits? The "Optional" for Deep Sleep means the WDOG can operate in Deep Sleep if CS[STOP]=1 and a clock source other than the bus clock is configured. For Debug and Stop modes, a clock source other than the bus clock must be used. Using the bus clock the watchdog can be "enabled" architecturally but its clock is gone, unless a different clock source is selected, for example, 32K_CLK. Best regards, Sofia. Re: KW47: Relationship between WDOG Wait/Stop modes and Power Modes (Sleep/Deep Sleep) Hi @sofiaurueta  Thank you for your previous explanation. >Are you testing with any example from the SDK? How are you confirming that the device is entering Deep Sleep mode? Regarding your question, the test was not performed on an SDK example project. It was performed on our application based on the NXP SDK. To verify whether the device enters Deep Sleep mode, I performed some additional investigation and found that the following path is executed when entering low-power mode: vPortSuppressTicksAndSleep() -> PWR_EnterLowPower() -> PM_EnterLowPower() -> PM_EnterLowPowerMode() -> CMC_EnterLowPowerMode() In CMC_EnterLowPowerMode(), the SDK sets the SLEEPDEEP bit in the SCB->SCR register before executing WFI. Our understanding is that setting the SLEEPDEEP bit and executing WFI means that the device enters Deep Sleep mode. Could you please confirm whether this understanding is correct for KW47? I am asking because my WDOG test results appear to depend on the WAIT bit rather than the STOP bit. Thank you for your help.
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マイクロセーフティマニュアルへのアクセス こんにちは、 2026年12月6日時点で、私はS32K3のセキュアなリソースを閲覧できる状態になっているはずです。 S32K358のセーフティマニュアルを探しているのですが、まだ全く見つかりません。 ここ https://www.nxp.com/products/S32K3#myDocument の安全なドキュメントやMy NXPアカウントの「Secure Resources」>で試しましたが、見つかりませんでした。 どなたか助けていただけますか? ありがとう、 サイモン Re: Accessing Micro Safety Manual こんにちは、 @simon98さん お客様のアカウントおよび内部記録を確認しましたが、S32K3セーフティマニュアルの過去のリクエストは見つかりませんでした。この文書を取得するために、より高いアクセス権限を申請する手助けをいただけますか? BR、VaneB Re: Accessing Micro Safety Manual こんにちは、 @VaneB さん。 セーフティマニュアルのアクセスをどう申請すればよいか教えていただけますかS32K358? 安全な資源(2006年12月にキャンプされたもの)にアクセスできると思っていましたが... BR、 サイモン Re: Accessing Micro Safety Manual こんにちは、 @simon98さん 役立つかもしれない「 NXPのセキュアアクセス権初回ユーザー登録ガイド」をご覧ください。 Re: Accessing Micro Safety Manual こんにちは、 @VaneBさん すでに安全なリソースへのアクセスはできていますが、セーフティマニュアルは安全なリソースのセクションで見つかりませんでした。 私は自分のニーズを具体的に明記した、より上位の権限要求を申請しようと試みました。それは正しいですか? ありがとうございます サイモン
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