1. Background When an embedded device is being upgraded, due to external factors such as power outage and forced interruption, the new firmware can‘t be written completely into flash, which causes problems when the system is started. Or if the image file is damaged during device is currently running, the system will break down and the device cannot run. To solve these problems, you can use the dual image, which ensures that at least one image file can be started and works properly at any time. If anything goes wrong, the bootloader detects and uses the alternate image file. 2. Principle LPC5536 ROM supports the dual image boot for internal flash, that means, in the flash region, two boot images can be placed there; ROM decides to boot which image based on the image version, boot the one with the newer image version first, if fail, boot the older one. During power-on and startup, the ROM first detects the location and size of the relocated image file in the CMPA, and then detects the version number of the two images. Therefore, when the dual image is used,  mainly need configure the relocation address and version number of the image files. The internal flash boot flow for dual image is as follows:   2.1 Relocating Image File The LPC5536 internal flash supports remapping. When set the remap offset, Internal FLASH memory AHB access will change the access address adding the offset as the below figure shows. For example, when the offset is set to 128K(0x20000), the access to 0x0 will be remapped to 0x20000. Via this IP feature, ROM can implement a dual image boot with two images. The offset and the remap size of the image is set in CMPA region by the user. This is an illustration of two image files stored in internal FLASH. The offset and remap size of the second image is set by the user in the CMPA area to let ROM know the location of the second image.   2.2 Configuring Image Version The image version is the image header offset 0x24; bit 10 shows whether the image contains the image version for not; if bit10 is 0, that means the image has no image version; ROM will take the image version as 0.   3、Implementation 3.1 Configuring CMPA 1) Configure Data Values in the CMPA Use blhost to write the modified bin file to CMPA to configure the image1 offset and remap size. The procedure is as follows: First, open an all “0” cmpa.bin and change the data at 0x3E23C to 0x20000, as shown in the figure below:   Then, modify the remap size. The data at address 0x3E238 is changed to 0x1d800, as shown in the following figure:   Modify and save, rename as cmpa_new.bin, save as \blhost_2.6.7\blhost_2.6.7\bin\win. 2) Download cmpa_new.bin Blhost 2.6.7 is a command-line tool, that use it to program cmpa_new.bin. Check whether the communication between blhost and development board is successfully. Firstly, check the port number for connecting between development board and computer from  device manager.   Secondly, short 3 and 4 of jumper J43 on lpc55s36-evk to enable ISP boot. Thirdly, press the reset key to reset board, input connection test command “blhost-p com12 -- get-property 1” Check whether communication is normal. If connection is successful, the message will be displayed as below:   Program modified bin file into CMPA. Write CMPA by using command “blhost-pcom12 -- write-memory 0x3e200 cmpa_new.bin”as shown below:   Read back CMPA data after writing. To confirm the accuracy of the data, run command “blhost-pcom12 -- read-memory 0x3e200 512” to view the configured CMPA data, as shown in the following figure:   3.2 Setting Dual Image Version To observe experimental effect, Image0 function is the RED light on LPC5536-evk development blinking, Image1 function is BLUE light blinking. In Image0 project, set version number to 1, in Image1 set version number to 2: Open the project of red light blinking and change the header file to 0x10400 at offset 0x24.   Open the project of blue light blinking and change the header file to 0x20400 at offset 0x24.   3.3 Remap Flash For users, LPC5536JBD100 has a total of 246K internal flash available, so Image0 is assigned to the address range 0x00000-0x1FFFF and Image1 is assigned to the address range 0x20000-0x3D7ff. If using MCUXpresso ID, the Settings are as follows: Right-click Selected Project -> choose Properties ->MCU settings, set the Location (start address) and Size, click  Apply button when finished. The red light blinking project are modified as follows:    The blue light blinking project modified as follows:   Re-compile the project.  3.4 Functional Testing Test application is two lighting projects, namely red light blinking and blue light blinking. The red light blinking is image0, version 1, and the blue light blinking is image1, version 2. Therefore, if test result is blue light blinking, dual image function works successfully.. Download Images: Using GUI Flash Tool in MCUXpresso IDE, download two image files to the development board:   Open, and the following view pops up. Select download File in "File to program", then click run button, image will be downloaded to flash.   When the download is complete, click OK.   Download another image in the same way. Note that "mass erase" cannot be checked when programing the second image. If you use other tools to program, also should disable the same function as "mass erase", avoid erasing the first image file. Test result： After downloading the program and reset, the blue light blinking. Further test: Change the version number of red light blinking project to 3, that is, modify 0x10400 to 0x30400. Then downloading the image file again. The red light blinking. 4、Summary Dual image function increases the security for boot and firmware update of embedded devices. It is necessary to pay attention to the way of setting image offset, remapping size and configuring image version in the CMPA area when using it, and also pay attention to the flash configuration in the two projects.   Attachment is test application project.

Continuously reducing the power consumption of integrated circuits is a constant topic in the development of integrated circuits. Reduced power consumption helps save power, extend standby time and reduce product heat, etc. Needless to say, low power consumption has become one of the important factors to measure product performance.   We usually recommend customers to refer MCUXpresso SDK power_mode_switch_lpc demo as low power design reference code. With this demo, customers can use serial terminal to control MCU to enter four low power consumption modes：Sleep mode，Deep Sleep mode，Power Down mode and deep power down mode. Meanwhile, user can also choose a variety of wake-up methods to wake up MCU through UART command.   However, when customers take use of power_mode_switch_lpc demo to measure lower power static characteristics, they find discrepancies with data sheet. Take example with LPCXpresso845MAX board. In power down mode, the demo board current reaches to around 100uA in debug mode. But data sheet states the typical current value is 1.5uA, no more than 10uA (see the Table below). Where is the problem? The purpose of the power_mode_switch_lpc demo is to demonstrate several low power modes and multiple wake-up methods to customers. We can’t get similar low power current value with default demo board as spec shows, but let's walk through a step-by-step demonstration and modify the routine to get the data sheet values.   LAB ENVIRONMENT: Demo Board: LPCXpresso845MAX SDK: SDK_2.11.0_LPCXpresso845MAX Demo Code: power_mode_switch_lpc IDE：MCUXpresso IDE v11.5.0   STEP: 1. Download power_mode_switch_lpc to LPC845 development board and run it. The serial port selects low power mode, press (SW2 button) to wake up. The program runs into power down mode, with debugger connected, the measured Idd is 99.5uA To enter low power mode, the following code is used: POWER_EnterPowerDown(DEMO_ACTIVE_IN_DEEPSLEEP); In order to wake up, parameter DEMO_ACTIVE_IN_DEEPSLEEP is configured with PDSLEEPCFG. BOD and watchdog oscillator power domains are turned on. All these setting results in potential current loss, causing power supply current higher than expectation.   2. In this step, we will remove wakeup initialization code // DEMO_InitWkt(); Replace this line of code //POWER_EnterPowerDown(DEMO_ACTIVE_IN_DEEPSLEEP); //enter power down mode with BOD and watchdog osc with POWER_EnterPowerDown(0); //power down BOD and watchdog osc   The modification is to turn off BOD power domain and watchdog clock in power down mode, compile and download the code again and enter the power down mode. At this time, the measured Idd is 57.3uA   In this way, Idd is significantly reduced. However, 57.3uA is still far from the typical value of 1.5uA stated in the data sheet. This is due to MCU debug power domain is turned on by IDE debugger, which leads to extra current consumption.  3. Thus we disconnect debugger and let the development board work in stand-alone mode (power off and re-power on). After power on, LPC is in power down mode. At this time, the measured Idd is 1.4uA. This is quite similar as the current value in datasheet. Consider GPIO configuration: The spec data shown in datasheet are tested under a dedicated test board with almost no external peripheral devices, and unused pins are basically in a floating state. For custom board or  LPCXpresso804 EVK. Some of its IO pins have external pull-up resistors and LEDs. If the GPIO is configured to output low power, the small light will be lit, resulting in additional power consumption. So we configure all pins as pull-up inputs for low power measurement.   Consider package: The test is based on LPCXpresso845MAX equipped LPC845 64pin package. It also applies to LPC845 48pin package. 33 package doesn't have VDDA pin. Due to VDD and VDDA pin design are not exactly the same as other package, for instance, 33pin low power consumption in power down mode is slightly higher than 64/48pin, but no more than 10uA as our spec in DS. Summary: Low power current parameters of the data sheet are measured with all MCU oscillators and analog domains off. Besides, reasonable configuration of GPIO can further reduce MCU power consumption. Before entering the low power consumption mode, it is recommended to set the unused GPIO as a pull-up input according to the actual situation (It can also be set to output low when the pin is floating). In applications with high requirements for low power consumption, users need to carefully optimize the code design to obtain the best low power consumption design.

A vulnerability (CVE-2022-22819) has been identified on select NXP processors by which a malformed SB2 file header sent to the device as part of an update or recovery boot can be used to create a buffer overflow. The buffer overflow can then be used to launch various exploits. Refer to the attached bulletin for more information.   09/26/2022 - Bulletin updated to include fix datecode information. 11/01/2022 - Bulletin updated with clarification that mixed datecodes are RT600 only.    

Contents 1. Introduction 1 2. USB Demo based on MCUXpresso SDK 1     2.1 Update USB device demo: USB0->USB1 2     2.2 Update USB host demo: USB0->USB1 2     2.3 Update USB ROM demo: USB0-> USB1 3 3. USB Demo based on LPCOpen 3 4. Notes and Recap 4  1.     Introduction Most of LPC devices integrate USB module. NXP LPC currently integrates full-speed USB (FS, Full Speed, 12Mbps) and high-speed (HS, High Speed, 480Mbps) USB. Specifically, for the LPC series: - Some LPCs such as LPC55xx and LPC54xxx integrate both HS USB and FS USB. Usually USB0 is FS USB and USB1 is HS USB. - Some LPCs such as LPC43xx and LPC18xx integrate two HS USBs, so USB0 and USB1 are both HS USBs. The two most well-known NXP software packages for LPC series are MCUXpresso SDK and LPCOpen. MCUXpresso SDK is mainly for LPC products launched in recent years, while LPCOpen is used for earlier LPC derivatives. The USB demos included in these two packages run on USB0 by default. Most of NXP USB demos are for USB0 by default. This article is to introduce how to switch a USB0 demo to USB1 demo based on different software packages. 2.     USB Demo based on MCUXpresso SDK (e.g. LPC54XXX, LPC55XX) The MCUXpresso SDK USB demo codes are categorized as: - USB as Device: e.g. usb_device_cdc_vcom, usb_device_hid_generic, etc. - USB as Host: e.g. usb_host_hid_mouse, usb_host_msd_fatfs, etc. - USB demo based on USB ROM API: e.g. usb_rom_device_audio,usb_rom_device_cdc, etc. 2.1  Update USB device demo: USB0->USB1 Taking usb_device_cdc_vcom demo as an example. To switch to USB1, simply change the corresponding code in usb_device_config.h file as follows. /*! @brief LPC USB IP3511 FS instance count*/ #define USB_DEVICE_CONFIG_LPCIP3511FS (0U) /*! @brief LPC USB IP3511 HS instance count*/ #define USB_DEVICE_CONFIG_LPCIP3511HS (1U) After the change, recompile the program to run. The program was updated to USB1 device demo. 2.2   Update USB host demo: USB0->USB1 Taking usb_host_hid_mouse demo code as an example, to switch to USB1, modify the macro definition in usb_host_config.h as follows: #defineUSB_HOST_CONFIG_KHCI (0U) #defineUSB_HOST_CONFIG_EHCI (0U) #define USB_HOST_CONFIG_OHCI (0U) #define USB_HOST_CONFIG_IP3516HS (1U)   The program is recompiled and run. The program was updated to USB1 host demo. 2.3  Update USB ROM demo: USB0-> USB1 ( e.g. LPC54XXX Series) USB ROM demo calls the USB ROM API, there is no way to switch the default USB0 to USB1 by modifying macro definitions. In order to update code to USB1 demo, the recommended steps are as below: -USB HS DEVICE and USB PHY clock configuration -Change to use USB HS ISR -Locate the related buffer into USB RAM. -Set the USB ROM handle to be HS If user has difficulties in revising the code by self, user can apply demo code from NXP LPC online support team by creating a private case. 3.     USB Demo based on LPCOpen (e.g. LPC43XX, LPC18XX) Some legacy LPCs run on LPCOpen, such as LPC43xx series, LPC18xx series. Their USB0 and USB1 are both high-speed. The default USB demo is for USB0 as well. To switch to USB1, we can uncomment #define USE_USB1 and comment #define USE_USB0 in app_usbd_cfg.h. // #define USE_USB0  #define USE_USB1 Taking usbd_rom_cdc_uart demo as an example:   Recompile and run, the program is updated to USB1 demo. 4.     Notes and Recap The focus of this article is on software modification of converting USB0 to USB1 on NXP SW package. Regarding the hardware, customer needs to check the specific demo board user guide. For example, when we use HS USB, it may be necessary to provide an external power supply, and the jumper also needs to be adjusted to build a well hardware environment for HS USB operation. I will not dwell on them here. This article summarizes methods of switching USB0 to USB1 for several commonly used LPC series on MCUXpresso SDK and LPCOpen package. customers who need USB1 demo code can find the corresponding modification methods in this article for their own software and chips. Official routines are only used for demo board demos and chip learning. If for commercial usage, user needs to learn USB in depth and be responsible for own application.  

经常有客户在使用LPC55S69的过程中遇到读 Flash进入异常HardFault中断的现象。如果在Flash Mass Erase之后从未对Flash扇区进行过写操作，直接用指针通过AHB读Flash地址会导致程序跳入HardFault 中断而无法继续正常运行。 原因    刚出厂的LPC55Sxx FLASH处于全零的全擦除状态，没有设置ECC。当芯片通过LinkServer 和MCUXpresso IDE建立连接时，先擦除要下载代码用到的扇区，再把代码下载到对应位置，并对相应存储区的ECC值同时进行更新。代码以外的区域仍然是无ECC设置的擦除状态。 当LPC55Sxx 通过AHB总线直接读取Flash内存区域时（例如，mytemp = *(uint32_t*)0x4000）要对Flash ECC进行校验。这一指令对于读有效代码区是没有问题的， 因为这一区域的ECC在下载代码时早已设置好。但是一旦读取没有代码的扇区，由于没有检测到正确的ECC，导致Flash读取失败，并跳转到下图中的HardFault_Handler()异常中断：   我们在Sector Erase后通过AHB读取Flash内存内容，也会遇到同样的HardFault异常跳转，出问题的原因都是一样的。 解决方法 针对这一问题我们有如下两种解决方法： 先执行Flash写操作，再读取Flash 与Flash 擦除操作不同，执行Flash写操作后对应的ECC值也同步更新。这样，ECC校验通过后，通过下面的代码就可以对Flash直接进行AHB读取。 volatile uint32_t mytemp; …… mytemp = *(uint32_t*)0x1000;//read memory content 0x1000 to mytemp 请注意：0x1000必须是一个已经写过的地址。 如果Flash的某个扇区处于被擦除的状态，我们只需要在通过AHB总线读取内存区域之前对该区域执行写操作，这样ECC校验位更新正确后，就可以正常读Flash。 Flash的写操作可以参考MCUXpresso SDK自带的flashiap例程，函数FLASH_Program。   使用Flash控制指令读取Flash区内容 使用Flash控制指令进行读操作不会导致硬件错误（请参阅UM11126 “Command listing (CMD)”章节）。这是用户手册中推荐的读Flash正确打开方式。 请注意：CPU只有在频率低于100MHz时，才能进行Flash操作（读，写，擦除，校验，等等），当CPU频率超过100MHz时是不能实现上述操作的。 目前，官方没有提供上用控制指令读取Flash内容的例程，因此需要您根据下面步骤创建自己的读Flash程序。 开发环境： IDE: MCUXpresso IDE v11.1.0 SDK MCUXpresso SDK v2.7.0 步骤： 在MCUXpresso IDE中导入一个基础例程，如led_blinky 在下图所述选项中添加iap组件   选择iap1,点击OK   点击完OK之后，fsl_iap_ffr.h, fsl_iap.c, fsl_iap.h文件将自动添加到工程中   在source文件夹中添加附件中的memory.h和memory.c文件   4) 使用Flash 控制指令时，需要在源文件中添加memory.h, fsl_iap.h   5) 调用memory初始化和memory读取函数   6）调试，单步执行（step over）到memory_read()，查看结果  

Contents     The default storage address space of code and data. 1     Customize Flash and RAM partitions. 2     Place the data in the specified address space. 3     Place the function in the specified address space. 4     Place the specified file in the specified address space. 5   During MCU development, placing data, function, and file in the specified memory address according to actual requirements is important for the memory usage. We Combine customer’s frequent ask questions, explain how to operate these features step by step. 1.     The default storage address space of code and data Take the hello world demo in LPC54628 as an example, and the development environment: MCUXpresso IDE. After building, the memory allocation is as shown in the following console window:   The relationship between .text, .data, .bss, .dec and Flash and RAM is as follows:   2.     Customize Flash and RAM partitions In order to place the data, function or file in the specified address space, we split some new partitions. Open the project property setting interface, and split MY_FLASH and MY_RAM address spaces in the MCU settings option for testing. The size of these two address spaces can be customized, as follows:   After configuring Flash and RAM, click ‘Apply and Close’ button and you will see Flash2 and RAM2 in the project column, as follows: 3.     Place the data in the specified address space 1)The default storage address space of variables and constants View the default address space of variables and arrays, as follows: Initialized variable：uint16_t value1 = 1; Uninitialized array：char data_buffer1[1024]; Constant array：   const char data_buffer2[1024] = "hello nxp"; View storage address space of arrays using the Image Info window in MCUXpresso IDE, as follows:   Readable and writable variables and arrays are stored in RAM (0x20000000-0x20014000) named "SRAM_UPPER" by default, and const arrays are stored in Flash (0x0-0x40000) named "PROGRAM_FLASH".  2) Place the specified variables and constants in the specified address space To place the array in custom Flash and RAM, you need to call the C language: __attribute__ ((section(#type #bank))) For example, place the data in .text of Flash2: __attribute__ ((section("text_Flash2" ".$Flash2"))) + data declaration The NXP official has encapsulated this and defined it in cr_section_macros.h. __DATA(RAM2) means that the readable and writable array is placed into the .data section of RAM2, and __RODATA(Flash2) means that the read-only array is placed into the .rodata section of Flash2. __DATA(RAM2) char data_buffer3[1024]; __RODATA(Flash2) const char data_buffer4[1024] = "hello nxp"; Note that you must #include "cr_section_macros.h".   Global variables and arrays are placed in custom RAM2 (0x20014000-0x20028000) named "MY_RAM", and const arrays are placed in custom Flash2 (0x40000-0x80000) named "MY_FLASH". 4.      Place the function in the specified address space 1)The default storage address space of functions The code is placed in the Flash (0x0-0x40000) named "PROGRAM_FLASH" by default, and the following function is defined: int hello1(void) {         return 1; } 2)Place the specified function in the specified address space To place the function in custom Flash, you need to call the C language: __attribute__ ((section(#type #bank))) For example, place the function in .text of Flash2: __attribute__ ((section("text_Flash2" ".$Flash2")))+function declaration The NXP official has also encapsulated this and defined it in cr_section_macros.h. The method to change the address space of the function is as follows, and place the function in a custom Flash named "MY_FLASH" (0x40000-0x80000). __TEXT(Flash2) int hello2(void) {                return 2; }   5.      Place the specified file in the specified address space When there are many functions that need to be placed in the specified Flash, it is a little clumsy to use the __TEXT(Flash) method to set each function. If you need to place all the functions in the c file in the specified Flash, you only need to place the compiled .o file in the specified Flash. Split a new partition named "MY_FLASH_O" , create a new hello.c under the source folder, compile and generate hello.o, and configure Linker Script to place hello.o in the partitioned Flash, as follows:   Reference: https://mcuoneclipse.com/2021/05/26/placing-code-in-sections-with-managed-gnu-linker-scripts/ Relocating Code and Data Using the CW GCC Linker File for Kinetis .pdf  

Recently I found some customers have a bit of problem when porting project from one MCU to another, so this article using simple steps demonstrates how to change MCU with MCUXpresso. There is also a video demonstrated the detail steps in attachment. Pay attention, as MCUXpresso User Guide says: All projects are associated with a particular MCU at creation time. The target MCU determines the project memory layout, startup code, LinkServer flash driver, libraries, supporting sources,launch configuration options etc. etc. so changing a project’s associated MCU should not be undertaken unless you have a total grasp of the consequence of this change. Therefore rather than changing a project’s associated MCU, it is strongly recommended that instead a new project is generated for the desired MCU and this new project is edited as required. However, on occasion it may be expedient to reset a project’s MCU (and associated SDK) and this can be achieved as follows. For example, changing lpc55s69 to lpc55s06, we need install SDKs for lpc55s69 and lpc55s06 before all the below steps. 1 - Change MCU & Package 1.1 – Change MCU Right click “MCU” under Project tree, choose “Edit MCU” Uncheck ”Preserve memory configuration”(it is checked by default)->choose LPC55S06->there is a warning, choose Yes. We can see the Memory details changed to lpc55s06, then click ”Apply and close”. 1.2 – Change Package 2 - Change Compiler Definitions In Properties view->Settings->MCU Compiler ->Preprocessor, change the definition for CPU from LPC55S69JBD100 to LPC55S06JBD64 as below: 3 – Change/add SDK driver for LPC55s06 Selected project, then click ”Manage SDK components”, choose the drivers our application used, for example, clock, power, usart. Click “OK”, then click “Yes” to update. Delete LPC55S69 device related files: Add “system_LPC55S06.c” and “system_LPC55S06.h” files: 4 - Change startup file. Delete LPC55s69 startup files, add “startup_lpc55s06.c”, we can find the startup file in any SDK demo. 5 - Change board related files. Refer to our own new board, change files under “board” folder, for example pins, uart number, here directly copy from SDK demo for LPCxpresso55s06 board. 6 - Test the project  function with new board Build project until no compile error, download and run it, result as below.        

The series of LPC540XX chips are flashless, only LPC54018JXM and LPC54S018JXM integrate internal QSPI Flash. The typical part numbers are LPC54018J2(4)M and LPC54S018J2(4)M. Some customers have questions about the concept of SPIFI interface and clock configuration when using this series of chips. This article mainly explains this. Introduction to SPIFI SPIFI (SPI Flash Interface) is an SPI Flash interface that can help microcontrollers replace large-size, high-cost parallel Flash with small-size, low-cost serial Flash. Using SPIFI technology, the external serial FLash can be mapped to microcontroller memory to achieve on-chip memory read effect, that is, cost can be optimized and Flash size can be increased while ensuring the operating speed. The electrical interface of SPIFI is as follows:   In the LPC540XX series of chips, if the part number includes M, QSPI Flash is integrated inside chip; if the part number does not include M, the QSPI Flash is externally connected to chip. The following picture shows the comparison of LPC54S018JXM and LPC54S018 in SPIFI structure:   SPIFI clock frequency description Taking LPC54S018J4M as an example, the SPIFI clock frequency is described below in the UserManual. SPIFI supports 1/2/4bit transmission mode. In 4bit transmission mode, the maximum transmission rate is SPIFI_CLK/2 bytes per second. The data transmission rate is up to 52Mbytes /s, that is, it takes two clock to transmit one byte. If you want to configure the SPIFI transmission rate to 52Mbytes /s, it needs to be in 4bit mode, so SPIFI_CLK is configured to 104M.     The SPIFI clock source is as follows in LPC54S018J4M Datasheet. By default, the SPIFI clock source is FRO96. For example, when the SPIFI clock is configured to 96M, in 4bit transmission mode, the transmission rate is 96/2=48Mbyte/s.   The LPC54S018J4M uses W25Q32JV-DTR as the internal SPIFI Flash. The figure below shows the maximum clock frequency it supports. In 4bit transmission mode, the maximum transmission rate is 133/2=66.5Mbyte/s, which is greater than SPIFI's maximum transmission rate of 52Mbyte/s. It shows that the maximum data transmission rate of W25Q32JV can meet the requirements of LPC54S018J4M QSPI Flash interface for communication rate.   3．Change SPIFI clock frequency The description of the SPIFI clock frequency in UserManual is as follows. In setup_lpc54s018m.c, the SPIFI clock frequency is defined on the address with an offset of 0X1C (the macro is defined as IMG_BAUDRATE), and the initial value is 0. According to the following table, when IMG_BAUDRATE=0, the SPIFI clock frequency is 24M. Since the default SPIFI clock source is the internal clock FRO96M, the SPIFI clock can be configured up to 96MHz in the following table by modifying the value of IMG_BAUDRATE.          There are two ways to modify the SPIFI clock.   3.1 Modify the SPIFI clock through IMG_BAUDRATE Before the main function runs, IMG_BAUDRATE is obtained by BOOT ROM to set the SPIFI clock frequency. If the requirement for the SPIFI clock rate is less than or equal to 96M, it is recommended to directly change the macro definition of IMG_BAUDRATE in setup_lpc54s018m.c to change the SPIFI clock frequency, as follows:   3.2 Modify the SPIFI clock through system config Another method is to modify the SPIFI clock frequency by changing the SPIFI frequency division coefficient in user code, as follows:   The result is as follows. The SPIFI clock frequency is set to 96M.   If you want to configure a higher SPIFI working clock, such as 104M, you must use a higher frequency external clock source to adjust the PLL coefficient and SPIFI frequency division coefficient in order to achieve the required clock frequency.

Symptoms Many LPC55 users experienced connection failure when using ISP USB0 for firmware update. In practice, we don’t suggest user updating firmware via ISP USB0 for LPC55(S)6x/ 2x,LPC55(S)1x/0x parts. Diagnosis LPC55 USB0 is Full Speed USB port. The default setting of CMPA turns off the USB0 port. Some users may reconfigure CMPA to enable ISP USB0 in order to use ISP USB0 BOOT, but this is not recommended in practice. LPC55 ISP USB0 uses internal FRO as clock source. According to LPC55 data sheet, the FRO accuracy is only +-2%, while the FS USB data rate tolerance specification is +-2500ppm(+-0.25%). Obviously, the LPC55 FRO spec can’t meet the USB0 clock accuracy requirement. See below extraction from NXP manuals. Fig 1. The accuracy of FRO ( Extracted from LPC55S69 Datasheet )   Fig 2. The accuracy requirement of USB FS( Extracted from TN00063 )  Some users may wonder why USB0 can use internal FRO as clock source in the user application?  Whenever internal clock source FRO is used as USB0 clock source, we must calibrate FRO in source code for communication. That’s to say, trim FRO to an accurate frequency. We can see FRO trim in many MCUXPressoSDK USB demos. When using FRO as the USB0 clock source, in order to ensure the USB0 clock accuracy, we must use the USB0 SOF frame synchronization to calibrate the FRO in order to ensure the accuracy of FS USB clock source (reference design of TN00063, TN00063-LPC5500 Crystal-less USB Solution). Unfortunately, the BOOT ROM of LPC55 does not support USB SOF calibrating FRO. As a result, even if we enable ISP USB0, the FRO clock drift can still cause USB0 communication failure under non-room temperature conditions. Solution Since ISP USB0 is not recommended for firmware update, the user manual no longer announces the enablement bit of ISP USB0 in CMPA. If you need to use USB0 for firmware update, we recommend using ISP USB1 (High Speed USB), because USB1 uses accurate external clock source which can ensure the ISP USB1 working stable. In addition, the communication protocol of ISPUSB complies with BLHOST specification. For details, see:  blhost User's Guide - NXP  

This article mainly introduces how to use CTIMER measuring pulse-width in LPC845, in fact, it can applies to all LPC products  including CTIMER modules. 1  CTIMER has below features: A 32-bit timer/counter with a programmable 32-bit prescaler. Four 32-bit match registers that allow interrupt generation on  match. The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge.(This article mainly use this feature.) Up to four match registers can be configured for PWM operation.   2 Introduction There is neither pulse-width measurement nor input capture demo under SDK, so write this article and related code for this topic. The principle is clearing the timer and prescaler on the leading edge of an input and capturing the timer valued on the trailing edge.   3  Main steps   Step1 Choose CAP input channel, capture edge, and enable interrupt if needed. Using “Capture control register”. The Capture control register is used to control whether one of the four capture registers is loaded with the value in the timer counter when the capture event occurs, and whether an interrupt is generated by the capture event. Setting both the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. In the description below, n represents the timer number, 0 or 1. In this example, choose capture channel 0 as input channel, falling edge as capture edge, and enable capture interrupt. SDK code: CTIMER_SetupCapture(CTIMER,CTIMER_CAP0_INT,  CTIMER_CAP_FALL,TRUE); Step2 Select which capture input edge will cause the timer and pre-scaler to be cleared. Using “Count control register”. The Count Control Register (CTCR) is used to select between timer and counter mode, and in counter mode to select the pin and edge(s) for counting. When counter mode is chosen as a mode of operation, the CAP input (selected by the CTCR bits 3:2) is sampled on every rising edge of the APB bus clock. After comparing two consecutive samples of this CAP input, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in the level of the selected CAP input. The timer counter register is incremented only if the identified event occurs and the event corresponds to the one selected by bits 1:0 in the CTCR register. Effective processing of the externally supplied clock to the counter has some limitations. Since two successive rising edges of the APB bus clock are used to identify only one edge on the CAP selected input, the frequency of the CAP input cannot exceed one half of the APB bus clock. Consequently, duration of the HIGH/LOWLOW levels on the same CAP input in this case cannot be shorter than 1/APB bus clock. Bits 7:4 of this register are also used to enable and configure the capture-clears-timer feature. This feature allows for a designated edge on a particular CAP input to reset the timer to all zeros. Using this mechanism to clear the timer on the leading edge of an input pulse and performing a capture on the trailing edge, permits direct pulse-width measurement using a single capture input without the need to perform a subtraction operation in software. In this example, we choose timer mode, configure Channel 0 rising edge clearing the timer, enable clearing of the timer and the pre-scaler. SDK code:   CTIMER->CTCR = CTIMER_CTCR_CTMODE(0)|CTIMER_CTCR_SELCC(1)   |CTIMER_CTCR_ENCC_MASK ; Step3 Read pulse-width value from “Capture register”. Each Capture register is associated with one capture channel and may be loaded with the counter/timer value when a specified event occurs on the signal defined for that capture channel. The signal could originate from an external pin or from an internal source.   SDK code: CTIMER_GetCAPCounter(HW_CTIMER0, HW_CTIMER_CH0); We can read capture value on capture interrupt. Detail code please refer to attached project, it based on MCUXpresso IDE v11.3, SDKv2.9, LPCxpresso845MAX board.   4  Test Result Input a signal as below into channel 0 (P1_0), pulse width is 10us. Print the measurement results on Console view of MUXpresso IDE:        

There are two ways to program LPC chips using Flash Magic, ISP mode and  Single Wire Debug (SWD) mode. ISP mode support COM port, USB, CAN and Ethernet. SWD support LINK2(LPC1800/lpc4300) bridge and LPC11u35 bridge. This article uses four demonstrations to show these programming methods.   1. ISP mode   1.1 UART ISP Mode Demonstration   1.2 USB ISP Mode Demonstration 2. Single Wire Debug(SWD) Mode   2.1 SWD over Link2 Bridge     2.1.1 Introduction     2.1.2 Demonstration  2.2 SWD over LPC11U35    2.2.1 Introduction    2.2.2 Demonstration    2.2.3 Recover board   Download Flash Magic tool from: https://www.flashmagictool.com/ Pay attention use the new version Flash Magic v13.10 or later.   About detail steps please refer to attachment. Thanks!

This document describes the different source clocks and the main modules that manage which clock source is used to derive the system clocks that exists on  LPC’s devices. It’s important to know the different clock sources available on our devices, modifying the default clock configuration may have different purposes since increasing the processor performance, achieving specific baud rates for serial communications, power saving, or simply getting a known base reference for a clock timer. The hardware used for this document is the following: LPC: LPCXpresso55S69 Keep in mind that the described hardware and management clock modules in this document are a general overview of the different platforms and the devices listed above are used as a reference example, some terms and hardware modules functionality may vary between devices of the same platform. For more detailed information about the device hardware modules, please refer to your specific device Reference Manual. LPC platforms The System Control Block (SYSCON) facilitates the clock generation in the LPC platforms, many clocking variations are possible and the maximum clock frequency for an LPC55S6x platform is @150MHz. For example, the LPC55S69 device supports 2 external and 3 internal clock sources. ·    External Clock Sources   Crystal oscillator with an operating frequency of 1 MHz to 32 MHz.   RTC Crystal oscillator with 32.768 kHz operating frequency.   ·    Internal Clock Sources Internal Free Running Oscillator (FRO). This oscillator provides a selectable 96 MHz output, and a 12 MHz output (divided down from the selected higher frequency) that can be used as a system clock. These 96MHz and 12MHz output frequencies come from a Free Running Oscillator of 192MHz. The 12MHz output provides the default clock at reset and provides a clean system clock shortly after the supply pins reach operating voltage. Note that the 96MHz clock can only be used for a USB device and is not reliable for USB host timing requirements of the data signaling rate.  32 kHz Internal Free Running Oscillator FRO. The FRO is trimmed to +/- 2% accuracy over the entire voltage and temperature range. This FRO can be enabled in several power-down modes such as Deep-Sleep mode, Power-Down mode, and Deep power-down mode, also is used as a clock source for the 32-bit Real-time clock (RTC).  Internal low power oscillator (FRO 1 MHz). The accuracy of this clock is limited to +/- 15% over temperature, voltage, and silicon processing variations after trimming made during assembly. This FRO can be enabled in Deep-Sleep mode, used as a clock source for the PLL0 & PLL1, and for the WWDT(Windowed Watchdog Timer). The LPC55S69 can achieve up to 150MHz but the clock sources are slower than the final System Clock frequency (@150MHz), inside the SYSCON block two Phase Loop Locked (PLL0 & PLL1) allow CPU operation up to the maximum CPU rate without the need for a high-frequency external clock. These PLLs can run from the Internal FRO @12 MHz, the external oscillator, internal FRO @1 MHz, or the 32.768 kHz RTC oscillator. These multiple source clocks fit with the required PLL frequency thanks to the wide input frequency range of 2kHz to 150 MHz. The PLLs can be enabled or disabled by software. The following diagram shows a high-level description of the possible internal and external clock sources, the interaction with the SYSCON block, and the PLL modules.    Figure 1. General SYSCON diagram   SYSCON manages the clock sources that will be used for the main clock, system clock, and peripherals. A clock source is selected and depending on the application to develop the PLL modules are used and configured to perform the desired clock frequency. Also, the SYSCON module has several clock multiplexors for each peripheral of the board i.e(Systick, FullSpeed-USB, CTimer), so each peripheral can select its source clock regardless of the clock source selection of other peripherals. For example, the following figure shows these described multiplexers and all the possible clock sources that can be used at the specific module.  Figure 2. Source clock selection for peripherals   For more detailed information, refer to “Chapter 4. System Control (SYSCON)” from the LPC55S6x User Manual.  Example: Enabling/Disabling PLLs The Clock tools available in MCUXpresso IDE, allows you to understand and configure the clock source for the peripherals in the platform. The following diagram shows the default PLL mode configured @150MHz, the yellow path shows all the internal modules involved in the clock configuration. Figure 3. Default PLL mode @150MHz at Reset of LPC55S69   For example, you can use the Clock tools to configure the clock source of the PLL to use the clk_in coming from the internal 32MHz crystal oscillator, the PLL is configured in bypass mode, therefore the PLL gets inactive resulting in power saving. Figure 4. Bypass of the PLL For more detailed information about PLL configuration, refer to “Chapter 4.6.6. PLL0 and PLL1 functional description” from the LPC55S6x User Manual.  Example: The next steps describe how to select a clock source for a specific peripheral using Clock Tools. 1.1 Configure clock for specific peripheral To configure a peripheral as shown in figure 17, Clock Tools is also useful to configure the clock source for the desired peripheral. For example, using the CTimer0 the available clock sources are the following: Main Clock PLL0 Clock FRO 96MHz Clock  FRO 1MHz Clock MCLK Clock  Oscillator 32KHz Clock No Clock(Inactive)                  Figure 5. CTimer0 Clock Source Selector Select CTIMERCLKSEL0 multiplexor and then switch to one of the mentioned clock sources, for example, the main_clk(Main Clock @150MHz) the clock multiplexor gets active and the yellow path is highlighted as shown in the following image.    Figure 6. CTimer0, Main Clock attached 1.2 Export clock configuration to the project After you complete the clock configuration, the Clock Tool will update the source code in clock_config.c and clock_config.h, including all the clock functional groups that we created with the tool. This will include the clock source for specific peripherals. In the previous example, we configured the CTimer0 to use the main_clk; this is translated to the following instruction in source code: “CLOCK_AttachClk(kMAIN_CLK_to_CTIMER0);” inside the “BOARD_BootClockPLL150M();” function.                      Figure 7. API called from clock_config.c file Note. Remember that before configuring any internal register of a peripheral, its clock source needs to be attached, otherwise, a hard fault occurs. References LPC55S6x/LPC55S2x/LPC552x User Manual Also visit RT's System Clocks Kinetis System Clocks

Previously, I wrote two articles about LPC55xx AHB read ( How to fix AHB Read HardFault Error) and LPC55xx FLASH alignment (Why FLASH Program cannot Success? ). In this article, we will go on investigating LPC55xx erased memory state. For most of NXP MCU, the erased FLASH state is 0xFF. Writing action is to change 1 to 0. However for LPC55, when we perform mass erase or section erase, we see the related memory turns to all 0 in MCUXpresso IDE debugger Memory view. This all-0-erased-status confuses many LPC55 beginners. Is this real memory state? The answer is yes, IDE debugger display is correct. LPC55xx FLASH uses 0x00 as erased value, which is opposite to most of the other FLASH devices which use 0xFF as erased value) There is no way to verify the erased FLASH state with code in runtime. NXP enhanced LPC55xx FLASH with ECC added. This means that there is now a functional block between the read entity (for example the CPU) and the FLASH itself. When erasing, both the erased FLASH and its ECC are set as 0. The reading can’t be successful if the erased memory and its ECC don’t match. Thus we can’t read memory in erased state. AHB read hardfault error is produced if do so.  Because of ECC mechanism, you can't read FLASH until you have written to it. see  How to fix AHB Read HardFault Error The User's Manual mentions the reading and writing operation in UM11126 chapter 5.7.13: When writing, parity is automatically computed and stored alongside user data. When reading, data and parity are used to reconstruct correct data, even in the case of a 1-bit error. When reading an erased location, an uncorrectable error is flagged. Use the “blank check” command to test for successful erase. The LinkServer debug in MCUXpresso IDE takes some precautions to avoid this problem while programming the FLASH before starting a debug session. That’s the reason we can see erased memory state in debugger memory view window, Admittedly, this is something not really pre-eminent in the documentation. The only reference we could spot is in UM11126. See below: “ The selected pages are checked for the erased condition (all 0 including parity)”   Thanks for the valuable comment from Radu Theodor Lazarescu.

LPCXpresso804 board has a on-board debugger developed with LPC11U35. Old batches of the board uses the old firmware for LPC11U35 debugger. The old firmware has some issues such as that when you send a string through the debug COM port the LPC804 only can receive the first byte. The solution is easy. We can download the newest firmware for LPC11U35 and update the firmware for LPC11U35. Download the fimware. The firmware and driver can be download from this link. Update the firmware.(Details can be found in UM11083: User Manual for LPCXpresso804 Board) Hold down the reset button and keep it held down while applying power to the board. Release reset. Using File Explorer (or equivalent on Mac/Linux platforms), look at the available drives on your system. A device called CRP_DISABLED will appear. Delete the firmware.bin file on the CRP_DISABLED drive. Drag and drop the firmware.bin file you downloaded from nxp.com on to the CRP_DISABLED drive. Re-power the board. The board should now enumerate on your system - allow 20-30 seconds for this to complete.

The documentation is only valid for the LPC55xx and LPC55Sxx families. In power down mode, some of peripherals for LPC55xx are power off, which means that the peripherals lose it’s power in power-down mode, so it is required to reinitialize the peripherals after waking-up from  power down mode. The DOC lists the peripherals which lose power in power down mode and are required to initialize, introduces the procedure to enter the power down mode, and  the procedure to reinitialize the peripherals after waking-up from power down mode. The doc is attached and power scheme is also attached.

Flashing and Installing the new firmware and drivers for LPC11U35 debug probes   We recently released a new set of debug firmware and Windows 7 drivers for our boards that feature the LPC11U3x MCU as a debug probe (so all the "MAX" boards). The new firmware can be found under the Software & Tools tab of the board page or it can download directly from this link:  Firmware and drivers for LPC11U35 debug probes The intention is for this firmware to be used instead of the mbed-based firmware and driver that has been used up until now, if you are not going to use MBED (you can continue to use the MBED version if you so wish however). Some reasons to consider the new firmware & driver: - The CMSIS-DAP implementation is newer, so a little more robust and faster. - The VCOM / serial port driver supports autobaud, with speeds up to 115200. - The VCOM driver has a cleaner installation (mbed serial port driver needs board to be plugged in to install, which is a little unusual). - The firmware auto-detects if a target serial port connection is present and enumerates a driver if they are. - The new firmware gives a unique ID per board, allowing multiple board connections at once. To install the windows drivers follow these steps: 1) Unzip the Firmware and drivers and double click on the LPC11Uxx_Debug_Probe_VCOM_v1.0.0 executable:     2) The installation wizard will show up, click on Next: 3) Choose the install location, the driver is installed by default in C:\Users\[USER]\AppData\Local\NXP Semiconductors\LPC11Uxx_VCOM\ but you can override this: 4) You will be asked to install the drivers, click on Install (These drivers were developed by www.ashling.com and are the intellectual property of NXP): 5) Finally click on Finish: The next step is to update the debug probe (LPC11U3x) firmware: 1) Unplug the usb connector. 2) Hold down the reset button and plug in the usb connector. 3) The board will appear on your system as a disk called CRP DISABLD. 4) Delete the file called firmware.bin on this disk. 5) Drag and drop the new binary image. 6) Connect and re-connect usb, you will have an additional VCOM port shown in Windows Device Manager: Hope it helps! Best Regards, Carlos Mendoza Technical Support Engineer

MCUXpresso SDK for LPC55xx uses FLASH API to implement FLASH drivers. Some user may meet issue when executes FLASH program code, for instance: status = FLASH_Program(&flashInstance, destAdrss, (uint8_t *)s_bufferFF, 8); After execution this code, nothing changed in the destination address, but error code 101 returns: This error code looks new, as it doesn’t commonly exist in other older LPCs. If we check FLASH driver status code from UM, code 101 means FLASH_Alignment Error: Alignment error Ah ha? ! Go back to the definition of FLASH_Program, status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes); New user often overlooks the UM description of this API “the required start and the lengthInBytes must be page size aligned”. That’s to say, to execute FLASH_Program function, both start address and the length must be 512 bytes-aligned. So if we modify status = FLASH_Program(&flashInstance, destAdrss, (uint8_t *)s_bufferFF, 8); To status = FLASH_Program(&flashInstance, destAdrss, (uint8_t *)s_bufferFF, 512); FLASH_Program can be successful.   ！！NOTE: In old version of SDK2.6.x, the description of FLASH_Program says the start address and length are word-aligned which is not correct. The new SDK2.7.0 has fixed the typo.  Keep in mind: Even you want to program 1 word, the lengInBytes is still 512 aligned, as same as destAdrss! PS. I always recommend my customer to check FLASH driver status code when meet problem with FLASH API. We can find it in UM11126, Chapter 9, FLASH API. I extract here for your quickly browse:   Happy Programming

This article is about how to use MCUXpresso Config Tool to create a USB project from start. The method is the same to all MCUXpresso Config Tool supported MCUs Demo: Creating USB composite HID mouse + keyboard project. Prequisities: LPCXpresso55S69-EVK MCUXPresso IDE 11.1.1 SDK package for LPCXpresso55S69 ,SDK_2.7.1_LPCXpresso55S69. The SDK has to be imported into MCUXPresso IDE (in Installed SDKs). Step by step guide is attached. Enjoy it :-).

The documentation discusses how to generate phase-shift PWM signals based on SCTimer/PWM module, the code is developed based on MCUXpresso IDE version 10.3 and LPCXpresso5411x board. The LPC family has SCTimer/PWM module and CTimer modules, both of them can generate PWM signals, but only the SCTimer/PWM module  can generate phase-shift PWM signals. In the code, only the match registers are used to generate events, I/O signals are not used.  The match0 register is set up as (SystemCoreClock/100), which determines the PWM signal frequency. The the match1 register is set up as 0x00, which generate event1. The the match2 register is set up as (SystemCoreClock/100)/2;, which generate event2. The duty cycle is (SystemCoreClock/100)/2-0x00= (SystemCoreClock/100)/2, which is 50% duty cycle, the cycle time is (SystemCoreClock/100). The event1 sets the SCT0_OUT1, event2 clears the SCT0_OUT1, so SCT0_OUT1 has 50% duty cycle. The the match3 register is set up as (SystemCoreClock/100)/4;, which generate even3. The the match4 register is set up as 3*(SystemCoreClock/100)/4, which generate event4. The duty cycle is 3*(SystemCoreClock/100)/4  -  (SystemCoreClock/100)/4= (SystemCoreClock/100)/2, which is 50% duty cycle. The event3 sets the SCT0_OUT2, event4 clears the SCT0_OUT2, so SCT0_OUT2 has 50% duty cycle. The phase shift is (SystemCoreClock/100)/4 - 0x00= (SystemCoreClock/100)/4, which corresponds 90 degree phase shift. PWM initilization code: //The SCT0_OUT1 can output PWM signal with 50 duty cycle from PIO0_8 pin //The SCT_OUT2 can output PWM signal with 50 duty cycle fron PIO0_9 pin //The SCT0_OUT1 and SCT0_OUT2 PWM signal has 90 degree phase shift. void SCT0_PWM(void) {     SYSCON->AHBCLKCTRL[1]|=(1<<2); //SET SCT0 bit     SCT0->CONFIG = (1 << 0) | (1 << 17); // unified 32-bit timer, auto limit     SCT0->SCTMATCHREL[0] = SystemCoreClock/100; // match 0 @ 100 Hz = 10 msec     SCT0->EVENT[0].STATE = 0xFFFFFFFF; // event 0 happens in all states     //set event1     SCT0->SCTMATCHREL[1]=0x00;     SCT0->EVENT[1].STATE = 0xFFFFFFFF; // event 1 happens in all states     SCT0->EVENT[1].CTRL = (1 << 12)|(1<<0); // match 1 condition only     //set event2     SCT0->SCTMATCHREL[2]=(SystemCoreClock/100)/2;     SCT0->EVENT[2].STATE = 0xFFFFFFFF; // event 2 happens in all states     SCT0->EVENT[2].CTRL = (1 << 12)|(2<<0); // match 2 condition only     //set event3     SCT0->SCTMATCHREL[3]=(SystemCoreClock/100)/4;     SCT0->EVENT[3].STATE = 0xFFFFFFFF; // event 3 happens in all states     SCT0->EVENT[3].CTRL = (1 << 12)|(3<<0); // match 3 condition only     //set event4     SCT0->SCTMATCHREL[4]=3*(SystemCoreClock/100)/4;     SCT0->EVENT[4].STATE = 0xFFFFFFFF; // event 4 happens in all states     SCT0->EVENT[4].CTRL = (1 << 12)|(4<<0); // match 4 condition only     //PWM output1 signal     SCT0->OUT[1].SET = (1 << 1); // event 1 will set SCT1_OUT0     SCT0->OUT[1].CLR = (1 << 2); // event 2 will clear SCT1_OUT0     SCT0->RES |= (3 << 2); // output 0 toggles on conflict     //PWM output2 signal     SCT0->OUT[2].SET = (1 << 3); // event 3 will set SCT1_OUT0     SCT0->OUT[2].CLR = (1 << 4); // event 4 will clear SCT1_OUT0     SCT0->RES = (3 << 4); // output 0 toggles on conflict     //PWM start     SCT0->CTRL &= ~(1 << 2); // unhalt by clearing bit 2 of the CTRL } Pin initialization code: //PIO0_8 PIO0_8 FC2_RXD_SDA_MOSI SCT0_OUT1 CTIMER0_MAT3 //PIO0_9 PIO0_9 FC2_TXD_SCL_MISO SCT0_OUT2 CTIMER3_CAP0 - FC3_CTS_SDA_SSEL0 void SCTimerPinInit(void) {     //Enable the     SCTimer clock     SYSCON->AHBCLKCTRL[0]|=(1<<13); //set IOCON bit     //SCTimer pin assignment     IOCON->PIO[0][8]=0x182;     IOCON->PIO[0][9]=0x182;     IOCON->PIO[0][10]=0x182; } Main Code: #include <stdio.h> #include "board.h" #include "peripherals.h" #include "pin_mux.h" #include "clock_config.h" #include "LPC54114_cm4.h" void SCT0_Init(void); void SCTimerPinInit(void); void P1_9_GPIO(void); void SCT0_PWM(void); int main(void) {       /* Init board hardware. */     BOARD_InitBootPins();     BOARD_InitBootClocks();     BOARD_InitBootPeripherals();     printf("Hello World\n");    // SCT0_Init();    // P1_9_GPIO();     SCTimerPinInit();     SCT0_PWM();     /* Force the counter to be placed into memory. */     volatile static int i = 0 ;     /* Enter an infinite loop, just incrementing a counter. */     while(1) {         i++ ;     }     return 0 ; } The Yellow channel is PIO0_8 pin output signal, which is SCT0_OUT1 PWM output signal. The Bule channel is PIO0_9 pin output signal, which is SCT0_OUT2 PWM output signal.

Description This application provides a human interface via terminal (UART1) menus and numbered selections to select and play audible medical alerts that are generated algorithmically on the NXP LPC23xx. The medical alarms are designed to comply with the IEC 60601-1-8 standard for audible medical alarms. The IEC standard seeks to improve patient safety by standardizing medical audible and visual alarms. The audible portion of the standard specifies high, medium, and low priority alarms, and these are provided via a menu system. In addition, a test menu is added to facilitate analysis of the quality of the alarms generated and their compliance with the standard. Many previous applications used playback techniques to use pre-recorded alarm sounds for the alerts. An algorithmic approach provides a much more efficient, high-quality implementation compared to the pre-recorded sounds. Plus, the sounds can be customized to differentiate equipment while still staying within the parameter limits of the standard. Block Diagram Documentation     IEC Alarm Detailed Documentation Products Below are recommended microcontrollers for use in implementing this design to a system. Comparison Table Product Pins On-Chip Flash On-Chip RAM Comments LPC2364 100 128KB 34KB 128KB flash/34KB RAM version of LPC2368, no SD/MMC LPC2366 100 256KB 58KB 256KB flash version of LPC2368, no SD/MMC LPC2368 100 512KB 58KB + 8KB 100-pin version of LPC2378, no external bus LPC2378 144 512KB 58KB + 8KB 144 pin, similar to LPC2368 but more pins and a MiniBus (8-bit) LPC2387 100 512KB 98KB LPC2368 with 98KB SRAM LPC2388 144 512KB 98KB LPC2378 with 98KB SRAM and USB Host/OTG LPC2458 180 512KB 98KB + 8KB LPC2468 with 16-bit External Memory Interface LPC2460 208 0KB 98KB + 8KB Flashless LPC2468 LPC2468 208 512KB 98KB Host/OTG/device, 32-bit ext. bus, 512KB flash/98KB RAM, 208 pin package LPC2470 208 0KB 98KB + 8KB LPC2460 with XGA LCD controller LPC2478 208 512KB 98KB + 8KB LPC2468 with XGA LCD controller More Information Example Code IEC Alarm Example Code Disclaimer This design example shows possible hardware and software techniques used to implement the design. It is imperative that the viewer use sound engineering judgment in determining the fitness of this design example for any particular application. This design example may include information from 3rd parties and/or information which may require further licensing or otherwise. Additional hardware or software design may be required. NXP Semiconductors does not support or warrant this information for any purpose other than an informational design example. documentation.pdf 395.85 KB example.code_.zip 255.55 KB