Dear Community User, We recently migrated content from the LPCWare.com forums into this community site. Migrated content can be found in the following two locations: LPCXpresso IDE for content from the LPCXpresso folder on the LPCWare.com forum, and LPC for all other content. All imported content will appear as posted by "LPCWARE" and will have the following message displayed at the top of each thread with the original username and date posted in LPCWare: If you wish to find the content you created in LPCWare you must: 1.-  Open the search box at the top right side of your community near your avatar. 2.- Type in the username you had set up in LPCWare and the results should automatically appear. All responses to postings in the original LPCWare.com forums are also preserved, so if you are looking for a response you or another particular user posted then you should also be able to locate those responses using the same search mechanism. All FAQs have been migrated to the NXP Community site. Several forum postings include references to FAQs and re-directs are in place to take you to their new location from those postings.

Flashing and Installing the new firmware and drivers for LPC11U35 debug probes   We recently released a new set of debug firmware and Windows 7 drivers for our boards that feature the LPC11U3x MCU as a debug probe (so all the "MAX" boards). The new firmware can be found under the Software & Tools tab of the board page or it can download directly from this link:  Firmware and drivers for LPC11U35 debug probes The intention is for this firmware to be used instead of the mbed-based firmware and driver that has been used up until now, if you are not going to use MBED (you can continue to use the MBED version if you so wish however). Some reasons to consider the new firmware & driver: - The CMSIS-DAP implementation is newer, so a little more robust and faster. - The VCOM / serial port driver supports autobaud, with speeds up to 115200. - The VCOM driver has a cleaner installation (mbed serial port driver needs board to be plugged in to install, which is a little unusual). - The firmware auto-detects if a target serial port connection is present and enumerates a driver if they are. - The new firmware gives a unique ID per board, allowing multiple board connections at once. To install the windows drivers follow these steps: 1) Unzip the Firmware and drivers and double click on the LPC11Uxx_Debug_Probe_VCOM_v1.0.0 executable:     2) The installation wizard will show up, click on Next: 3) Choose the install location, the driver is installed by default in C:\Users\[USER]\AppData\Local\NXP Semiconductors\LPC11Uxx_VCOM\ but you can override this: 4) You will be asked to install the drivers, click on Install (These drivers were developed by www.ashling.com and are the intellectual property of NXP): 5) Finally click on Finish: The next step is to update the debug probe (LPC11U3x) firmware: 1) Unplug the usb connector. 2) Hold down the reset button and plug in the usb connector. 3) The board will appear on your system as a disk called CRP DISABLD. 4) Delete the file called firmware.bin on this disk. 5) Drag and drop the new binary image. 6) Connect and re-connect usb, you will have an additional VCOM port shown in Windows Device Manager: Hope it helps! Best Regards, Carlos Mendoza Technical Support Engineer

Recently I have several customers experience HardFault error when perform AHB FLASH memory read on LPC55S69. If a FLASH sector has never been programed after mass erase, performing AHB reads of the FLASH memory contents will cause a hardware fault if an unrecoverable error is detected. Why? LPC55Sxx parts are delivered from the factory mass erased with ECC unset. When MCUXpresso IDE connects a chip via LinkServer, it will firstly erase the sectors that will be used for the image being programed, then program the code with a correct ECC set. The sectors beyond the end of the image will be left unchanged, which keep in “erased” states without ECC set on them.   When LPC55Sxx executes FLASH read code ( for example, mytemp = *(uint32_t*)0x4000 ) through AHB bus, it checks FLASH ECC while AHB read. No issue to read programed sectors because ECC has already set. But, read unprogrammed sectors with invalid ECC values leads to fail to read and go to HardFault_Handler as below: If performing AHB reads of the flash memory contents AFTER a sector erase, we will have the same HardFault issue. Solutions There are two solutions to fix the error. 1. Read FLASH Content after Programing the FLASH Sector Unlike mass erasing, programing FLASH updates the related ECC value. Thus with a successful ECC check, read AHB can be realizable by below code. volatile uint32_t mytemp; …… mytemp = *(uint32_t*)0x1000;//read memory content 0x1000 to mytemp‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍ NOTE: 0x1000 MUST be a “programed” address. If the unused FLASH sector is in “erased” state, in order to read it, we need manually program it before AHB read. FLASH programming demo code can be referred in flashiap demo under MCUXpresso SDK package. See function FLASH_Program. 2. Read FLASH Content Using FLASH Controller Command Read operations using FLASH controller commands (See UM11126 Section “Command listing (CMD)”) will not cause hard fault. This is the UM recommended method of read FLASH content. Note: Flash operations (erase, blank check, program) and reading a single word can only be performed for CPU frequencies of up to 100 MHz. These operations cannot be performed for frequencies above 100 MHz. So far I haven’t found a FLASH read demo code. Please follow below steps to create your demos. Environment: IDE: MCUXpresso IDE v11.1.0 SDK MCUXpresso SDK v2.7.0 Steps: See attached document. Thanks for the suggestion from Alex Yang and andybeeson‌

This is a quick introduction that shows how to interface the LPC845 Breakout Board with an OLED display based on the popular SSD1306 controller, using SDK drivers for SPI. With this application, you can print a text string or draw a bitmap image.   SPI Protocol The Serial Peripheral Interface (SPI) protocol is asynchronous serial data standard, primarily used to allow a microprocessor to communicate with other microprocessors or ICs such as memories, liquid crystal diodes (LCD), analog-to-digital converter subsystems, etc.   The SPI is a very simple synchronous serial data, master/slave protocol based on four lines:       • Clock line (SCLK)       • Serial output (MOSI)       • Serial input (MISO)       • Slave select (SS)   Adafruit Monochrome OLED Graphical Display This display is made of 128x64 individual white OLED pixels, each one is turned on or off by the controller chip. Because the display makes its own light, no backlight is required. This reduces the power required to run the OLED and is why the display has such high contrast; we really like this miniature display for its crispness!     OLED Display Example NXP provides an example package for the LPC845 Breakout that includes projects to use the principal's peripherals that the board include: ADC, I2C, PWM, USART, Captouch, and SPI   What we need: LPC845 Breakout Board MCUXpresso IDE V10.3.0 SDK_2.5.0_LPC845 NXP example package OLED Display from Adafruit (also available via NXP distributors) LCD assistant software to convert bitmaps Micro USB cable   Once downloaded, we import the library project into the workspace using the ''Import project(s) from file system... from the Quickstart panel in MCUXpresso IDE: Figure 1. Import Projects.   Then browse the examples packages archive file: Figure 2. Select Example Package.   Press next, and see that are a selection of projects to import, in this case, only keep select the LPC845_BoB_OLED how it looks in the picture below: Figure 3. Select the OLED Project.   Press finish and the project example shows up in the workspace: Figure 4. OLED Project in workspace. Create Bitmaps Bitmap (BMP) is an image file format that can be used to create and store computer graphics. A bitmap file displays a small dots in a pattern that, when viewed from afar, creates an overall image. A bitmap image is a grid made of rows and columns where a specific cell is given a value that fills it in or leaves it blank, thus creating an image out of the data. First, you have to create the image using any kind of graphics software such a paint, Photoshop, etc and save the picture as Monochrome Bitmap (bmp), make sure that the image size match whit the OLED size.       Figure 5. Save picture as Bitmap.   Now inside the LCD software assistant, this program will help us to convert an image from Bitmap to data array, we have to load the image by click on file >> load image, and select the appropriate size.   Figure 6. LCD Assistant    To import the array go to file >> save the output, choose the place where are going to save. Then inside the example, go to fsl_Font5x7.h and paste the array.   Figure 7. Data Array.      *Note: Inside the example, the array for the NXP logo is already there, if you want another image, delete this array and pas the new.   Connections Now, with the project already in the workspace, it is time to set up the connection between the LPC845 Breakout board and the OLED Display. The table below shows which LPC845 Breakout pin are routed each line of the SPI interface and the pins for reset and Data/Command select.   Table 1. Connections.   You can check the Datasheet of the board, of bases on the picture below to see where the pin are, note that GND and 3.3V also needed for the OLED display: Figure 8. LPC845 Breakout to OLED Connection.   Debug. Now, with the demo in the workspace and the connections done, connect a micro USB cable from connector CN2 to a host computer and debug the application.   Figure 9. Run example

This content was originally contributed to lpcware.com by Jack Ganssle In this project I looked at the relative performance of the LPC4350's M4 vs. M0 cores, emulating ARM's big.LITTLE approach. In the last few years the industry has increasingly embraced the notion of using multiple processors, often in the form of multicore. Though symmetric multiprocessing – the use of two or more identical cores – has received a lot of media attention, many embedded systems are making use of heterogeneous cores. A recent example is ARM’s big.LITTLE approach, which is specifically targeted to smart phones. A big Cortex-A15 processor does the heavy lifting, but when computational demands are slight it goes to sleep and a more power-frugal A7 runs identical code. NXP’s LPC43xx also has two ARM cores: a capable Cortex-M4 and a smaller M0. Since power constraints are hardly novel to phones, my question was: “if we mirror the big.LITTLE philosophy, what is the difference in performance between the M4 and the M0?”

The ADC of LPC55xx supports scan mode, in scan mode, once ADC triggering (either hardware or software) can convert multiple analog channels. The document gives an example that the CTImer2 module triggers ADC and ADC converts two analog channels for each triggering. The doc introduces the CTimer configuration, ADC triggering control register configuration, and ADC Command buffer chain and ADC result reading , in this way, the CTimer can trigger ADC, the ADC can convert multiple channels. The example and the doc are attached. The Example is developed based on SDK example lpcxpresso55s69_lpcadc_interrupt example, the tools is MCUXprsso IDE ver11.7, the SDK package is SDK_2.x_LPCXpresso55S69 ver2.11.1  

This article is about how to use MCUXpresso Config Tool to create a USB project from start. The method is the same to all MCUXpresso Config Tool supported MCUs Demo: Creating USB composite HID mouse + keyboard project. Prequisities: LPCXpresso55S69-EVK MCUXPresso IDE 11.1.1 SDK package for LPCXpresso55S69 ,SDK_2.7.1_LPCXpresso55S69. The SDK has to be imported into MCUXPresso IDE (in Installed SDKs). Step by step guide is attached. Enjoy it :-).

This content was originally contributed to lpcware.com by Brewster LaMacchia   This project shows how to take the filter coefficients created by MDS' QEDesign filter design package and use them for real time audio filtering using the floating point DSP capability of the LPC4350. It's designed to run on the Hitex board and uses the UDA1380 for analog stereo I/O. It also uses the touch buttons, COG LCD, and LEDs for controlling operation.   Keil's Logic Analyzer tool was used for performance measurement. For full details see \doc\gen\html\index.html after unzipping the download.   Updated 16-Mar-12 to correct output rolloff in the UDA1380 due to the deemphasis filter being on by mistake.   Original Attachment has been moved to: MyProj.zip

Introduction GUI Guider is a user-friendly graphical user interface development tool from NXP that enables the rapid development of high quality displays with the open-source LVGL graphics library. GUI Guider's drag-and-drop editor makes it easy to utilize the many features of LVGL such as widgets, animations and styles to create a GUI with minimal or no coding at all. In recent years, Smart Home has emerged rapidly and has a strong momentum of development. Smart Homes connect various household appliances and provide services such as lighting control, telephone remote control, burglar alarm and environmental monitoring. Smart Home applications are more and more widely used, but it is difficult for many developers to start. Using NXP GUI Guider can improve the development speed, reduce development difficulty, shorten development cycle. This article mainly introduces the use of GUI Guider to realize some functions of Smart Home, and shares some common methods in the use of GUI Guider, including creating a new project, adding controls, adding events, interface design and layout, and controlling the lighting of hardware lights. Development environment 2.1 Hardware environment Evaluation of LPC54628 -LPCXpresso54628, also applies to LPCxpresso54618, LPCxpresso54608. 2.2 Software Environment This Smart Home demo uses GUI Guider version 1.5.1 to set up the software environment. GUI Guider version 1.5.1 supports LVGL versions 7.10.1 and 8.0.2. This introduction is based on version 8.0.2 LVGL. Download link: https://www.nxp.com/design/software/development-software/gui-guider:GUI-GUIDER Create a new project 3.1 Double-click the GUI Guider icon to start the GUI Guider.   3.2 Click Create a new project (" Create a New Project ") button to start the project creation process.   3.3 select LVGL version v8.3.2 and click Next button.   3.4 Select LPC54628 as the target board template and click Next button.   3.5 Select empty application template EmptyUI and click Next.   3.6 Perform the project Settings, and set the project name, project location, and screen type (select RK043FN66H or RK043FN02H according to your screen type). Click Create to create the project.   3.7 After the project is created, the interface is as follows.   Page Design and Layout This section describes how to adjust the background color, layout, add various controls (Such as images, image buttons, text, and containers , etc), and set properties. 4.1 Create the image folder, and put the image resources needed in the project under the established image folder.   4.2 Adjust the background color of the interface ① Click the Background color icon to open the background color Settings. ② You can set the background Gradient or monochrome by using Gradient. ③ Then select the background color.   4.3 Add images ① Open Widgets control options. ② Click to add the Image control. ③ Then click the image shape button in the Attribute box of the property Settings, and “Select Images” will pop up. In “Select Images”, select the image you want to add, click OK to add the image, and adjust the image size and position.   In the same way, you can add the "small house" image. In the Widgets box, you can view the added image and set the image name. In the Screen box, you can view the current interface and set the interface name.   4.4 Add text ① Open the control options, select and click the Label control. ② In Property Settings Text, set the text content to SMART HOME. ③ Then click the Background background setting area to set the Label control background. ④ Set the color depth of the Label control to 0, without background color. ⑤ Set the Font color, size and style in the font.   4.5 Add a container Containers are essentially basic objects with layout and automatic resizing capabilities. Open the control option, click Container to add the Container control, and drag the control size. Set the background color in the property Settings. ③ Then set the Border and rounded corner of container in "Border".   Name the added Container control cont_TodayInfo. Add other controls to the Container control. You can view other controls (including picture, text, and line controls) added to the cont_TodayInfo container in the Widgets.   4.6 Add an Image button Image button are very similar to simple "button" objects. The only difference is that it displays image in each state defined by the user. ① Open component options, select and click the Imgbtn control. ② Add the Released and Pressed images.   In the same way, add other Imgbtn controls and Label controls.   Switch the interface This section describes how to create sub-interfaces and switch between the main interface and sub-interface. 5.1 Add a second new interface Click “+” to add a new screen, rename the new screen src_Light, add Image, imgbtn controls, and change the background color.   5.2 Add interface switching trigger conditions ① Select the imgbtn_Light button on the first screen. ② Select the Events Settings. ③ Click “+” to add an event, and then set the event. ④  In event Settings, trigger conditions need to be selected, here Clicked trigger conditions are selected. Target Select the second new interface src_Llight that you want to load, and then select the Delete current interface option. When the program is running, when the imgbtn_Light button is clicked, it will switch to the second src_Light interface.   Updating Media   5.3 Add a trigger condition for returning to the interface ① Select the imgbtn_Home control. ② In the event Settings, select Clicked trigger conditions, Target select src_Welcome for the interface to be loaded, and select Delete the current interface option. When the program is running, when the imgbtn_Light button is clicked, it returns to the first main screen of src_Welcome.   5.4 Design the second interface Add controls in the second interface, including Switch control, Slider control, Dropdown control, Image control, Imgbtn control, Label control. Switch control: This switch can be used to turn the light on/off and it looks like a small slider. Slider control: The slider object looks like a bar supplemented with knobs. You can drag the knob to set the value. The slider can be vertical or horizontal. Dropdown control: A drop-down list allows the user to select a value from a list. By default, the drop-down list is turned off and displays a single value or predefined text. The Image control, Imgbtn control, and Label control are described in the previous section.   Control hardware light design Smart home usually has the control of the light, through the control interface to control the hardware light on and off, the steps are as follows: 6.1 GUI Guider generates code project ① Generate the code by clicking the Generate code button. ② Click the Folder icon to open the project folder   6.2 Starting the MDK Project After the generated code is completed, open the project folder and open the MDK project in the specified directory (support MCUXpressoIDE, MDK, IAR).   6.3 First, the drive to control the light switch is added to the project Add a GPIO initializer in lvgl_guider.c.   6.4 then, add a custom Led control function under Custom.c This routine adds Led1_Control, Led2_Control, and Led3_Control lamp control functions.   6.5 Add custom event program to GUI Guider ① Select the first Switch control and add the event. ② In the event, select Trigger to trigger the event condition that the Switch control is on and off, and the Target option is set to Null.  In Action, select C to add custom events and click to open Edit Code.  Add a custom event function to Edit Code (open Led3, close Led2, Led1), and add the header file of the file where the custom event function is located.   6.6 View custom events in the MDK project After setting the custom event, the set Led custom trigger event can be found on events_init.c after the GUI Guider regenerates the code again.   Program download and demo After the project is completed, there are two ways to download the program to the development board: Open the project with IDE (MCUXpresso IDE, KEIL or IAR), compile and download the program to the development board. Selecting MCUXpresso, Keil, or IAR from Target in the GUI Guider automatically compiles the program to download to the board. The following diagram shows how Guider automatically compiles the download program to the development board in GUI.   Attached video shows the effect.   8.In SUMMARY This artical mainly shares the Smart Home interface design based on GUI Guider. GUI Guider, as a tool for GUI design, is powerful and easy to use. This article only uses a few functions of GUI Guider, we can further learn to explore GUI Guider, the related project has been placed in the attachment. The GUI Guider application guide can be found on the NXP official website, and the following are some ways to find information when learning to use GUI Guider. View the User Guide and click Help->User Guide   control Settings and usage instructions, you can click the following small icon to view    

This documet is an introduction about TrustZone on the LPC55S6x devices. LPC55S6x MCU platform and general-purpose blocks The LPC55S69 has one 100-MHz Cortex-M33 core with TrustZone, MPU, FPU, and SIMD and another 100-MHz Cortex-M33 without security features enable. Lets remark that the LPC55Sxx family has another LPC55S66 that only implements a single 100-MHz core. There are two coprocessors on core 0, a DSP accelerator called PowerQuad, and a crypto engine called CASPER. The core platform has a multilayer bus matrix that allows simultaneous execution from both cores and parallel access of the other masters to peripherals and memories. The memory on chip includes up to 640 KB of Flash, up to 320 KB of RAM, and 128 KB of ROM. Timers include 5 - 32-bit timers, a SCTimer/PWM, a multi-rate timer, a windowed watchdog timer, Real Time Clock (RTC), and a micro timer. Each core has its own systick timer. Communication interfaces include a USB high-speed with on-chip HS PHY, a USB full-speed that can run crystal-less, two SDIO interfaces to support WIFI and SD cards at the same time, 1 high-speed SPI with up to 50-MHz clock rate, and 8 Flexcomms with support of up to 8 SPI, I2C, UART, or 4 I2S. The analog system includes a 16-channel 16-bit ADC that samples at 1 MSPS, an analog comparator, 16-channel capacitive touch controller, and a temperature sensor. Other modules include a programmable logic unit, a buck DC-DC converter, operating voltage from 1.71 to 3.6 V over a temperature range from -40 to 105 °C. What is TrustZone? In recent years, the Internet of Things (IoT) has become a hot topic for embedded system developers. IoT system products have become more complex, and better solutions are needed to ensure system security. ARM® TrustZone® technology is a System on Chip (SoC) and CPU system-wide approach to security. The TrustZone® for ARMv8-M security extension is optimized for ultra-low power embedded applications. It enables multiple software security domains that restrict access to secure memory and I/O to trusted software only. TrustZone® for ARMv8-M: Preserves low interrupt latencies for both secure and non-secure domains Does not impose code overhead, cycle overhead or the complexity of a virtualization based solution Introduces efficient instructions for calls to the secure domain with minimal overhead TrustZone® is a technology available in Cortex M23 and Cortex M33. TrustZone® provides the means to implement separation and access control to isolate trusted software and resources to reduce the attack surface of critical components. The created trusted firmware can protect trusted operations and is ideal to store and run the critical security services. The code should also protect trusted hardware to augment and fortify the trusted software. This includes the modules for hardware assists for cryptographic accelerators, random number generators, and secure storage. Best practices demand that that this code be small, well-reviewed code with provisions of security services. The LPC55S66 and LPC55S69 have implemented core 0 as a Cortex-M33 with full TEE and TrustZone® support enabled. The LPC55S69 has a second Cortex-M33 (core 1) that does not implement the secure environment with TZ. Isolation is just the foundation. Security is about layers of protection, adding in further hardware and software to create more layers. Features of TrustZone® technology: Allows user to divide memory map into Secure and Non-Secure regions Allows debug to be blocked for Secure code/data when not authenticated CPU includes Security Attribution Unit (SAU) as well as a duplication of NVIC, MPU, SYSTICK, core control registers etc. such that Secure/Non-Secure codes can have access to their own allocated resources Stack management expands from two stack pointers in original Cortex-M (Main Stack Pointer (MSP) and Process Stack Pointer (PSP)) to four, providing the above pair individually to both Secure and Non-Secure Introduces the concept of Secure Gateway opcode to allow secure code to define a strict set of entry points into it from Non-secure code Secure and non-secure memory TrustZone® technology divides the system into two states, safe (S) and non-secure (NS), and can switch between the two states through corresponding commands. The CPU states can be secure privilege, secure non-privilege, privilege (Handler), or non-privilege (Thread). The Secure memory space is further divided into two types: Secure and Non-secure Callable(NSC). Below are the feature/properties of Trustzone memory regions ( S, NS, NSC 😞 Secure (S) - For Secure code/data − Secure data can only be read by secure code − Secure code can only be executed by CPU in secure mode Non-Secure (NS) – For non-Secure code/data − NS Data can be accessed by both secure state and non-secure state CPU − Cannot be executed by Secure code Non-Secure Callable (NSC) − This is a special region for NS code to branch into and execute a Secure Gateway (SG) opcode. Attribution Units Combination of Security SAU and IDAU assign a specific security attribute  (S, NS, or NSC) to a specific address from the CPU0. Device Attribution Unit (DAU) connects to CPU0 via IDAU interface as show the following Figure. Access from CPU0, dependent on its security status and the resultant security attribute set by the IDAU and SAU, is then compared by the secure AHB Controller to a specific checker which marks various access policies for memory and peripherals. All addresses are either secure or non-secure. The SAU inside of the ARMv8-M works in conjunction with the MPUs. There are 8 SAU regions supported by LPC55S69. Secure and non-secure code runs on a single CPU for efficient embedded implementation. A CPU in a non-secure state can only execute from non-secure program memory. A CPU in a non-secure state can access data from both NS memory only. For the secure, trusted code, there is a new secure stack pointer and stack-limit checking. There are separate Memory Protection Units (MPUs) for S and NS regions and private SysTick timers for each state. The secure side can configure the target domain of interrupts. The NXP IDAU (Implementation specific Device Attribution Unit) implementation of ARM TrustZone for core0 involves using address bit 28 to divide the address space into potential secure and non-secure regions. Address bit 28 is not decoded in memory access hardware, so each physical location appears in two places on whatever bus they are located on. Other hardware determines which kinds of accesses (including non-secure callable) are allowed for any address.  The IDAU is a simple design using address bit 28 to allow aliasing of the memories in two locations. If address bit 28 is = 0 the memory is Non-Secure. If address bit 28 = 1 the memory is Secure. The SAU allows 8 memory regions and allow the user to override the IDAU’s fixed Map, to define the non-secure regions. By default, all memory is set to secure. At least one ASU descriptor should be used to make IDAU effective. If either IDAU or SAU marks a region, then that region is secure. NSC area can be defined in NS region of the IDAU. For example a designer could use bit [28] of the address to define if a memory is Secure or Non-secure, resulting in the following example memory map. Simple IDAU, without creating a critical timing path. (CM33 does allows little for IDAU function) Addresses 0x0000_0000 to 0x1FFF_FFFF are NS, Addresses 0x2000_0000 to 0xFFFF_FFFF If Address Bit_28 = 0  Non-Secure If Address Bit_28 = 1  Secure All peripherals and memories are aliased at two locations. The SAU define region numbers for each of the memory regions. The region numbers are 8-bit, and are used by the Test Target(TT) instruction to allow software to determine access permissions and security attribute of objects in memory. The number of regions that are included in the SAU can be configured to be either 0, 4 or 8. Note: When programming the SAU Non-secure regions, you must ensure that Secure data and code is not exposed to Non-secure applications. Security state changes The system boots in secure state and can change security states using branches as summarized in the following Figure. Transitions from secure to non-secure state can be initiated by software through the use of the BXNS and BLXNS instructions that have the Least Significant Bit (LSB) of the target address unset. Note: The M profile architecture does not support the A32 instruction set. This allows the LSB of an address to denote the security state. Transitions from non-secure to secure state can be initiated by software in two ways: A branch to a secure gateway. A branch to the reserved value FNC_RETURN. A secure gateway is an occurrence of the Secure Gateway instruction (SG) in  the Non-Secure Callable (NSC) region. When branching to a secure gateway from non-secure state, the SG instruction switches to the secure state and clears the LSB of the return address in lr. In any other situation the SG instruction does not change the security state or modify the return address. A branch to the reserved value FNC_RETURN causes the hardware to switch to secure state, read an address from the top of the secure stack, and branch to that address. The reserved value FNC_RETURN is written to lr when executing the BLXNS instruction. Security state transitions can be caused by hardware through the handling of interrupts. Those transitions are transparent to software and are ignored in the remainder of this document. The TT instruction The ARMv8-M architecture introduces the Test Target instruction (TT). The TT instruction takes a memory address and returns the configuration of the Memory Protection Unit (MPU) at that address. An optional T flag controls whether the permissions for the privileged or the unprivileged execution mode are returned. When executed in the secure state the result of this instruction is extended to return the Security Attribution Unit (SAU) and Implementation Defined Attribution Unit (IDAU) configurations at the specific address. The MPU is banked between the two security states. The optional A flag makes the TT instruction read the MPU of the non-secure state when the TT instruction is executed from the secure state. The TT instruction is used to check the access permissions that different security states and privilege levels have on memory at a specified address. You can find more useful information about ARM® TrustZone®, in the following links: https://developer.arm.com/ip-products/security-ip/trustzone https://www.nxp.com/docs/en/application-note/AN12278.pdf http://www.keil.com/appnotes/files/apnt_291.pdf  http://infocenter.arm.com/help/topic/com.arm.doc.ecm0359818/ECM0359818_armv8m_security_extensions_reqs_on_dev_tools_1_0.pdf

Hello community!   Attached is a document that explains how to build and run the LPCOpen Ethernet example projects, it also explains the needed board and PC connections and configurations. The steps described in the document were done using the LPC1769 MCU like the one in the LPCXpresso board for LPC1769 with CMSIS DAP probe, but the same principles are applicable to any LPC MCU. The steps described in this document are valid for the following versions of the software tools: o    LPCXpresso v8.1.4 o    LPCOpen v2.xx Boards o    LPCXpresso board for LPC1769 with CMSIS DAP probe o    EA LPCXpresso BaseBoard o    LPC-Link2 Contents 1. Overview and concepts    1.1    LPCOpen       1.1.1 Core driver library       1.1.2 Middleware       1.1.3 Examples       1.1.4 LPCOpen with an RTOS 2. Running the lwip_tcpecho and webserver demo applications    2.1 Downloading a LPCOpen package    2.3 Setting up the hardware       2.3.1 LPCXpresso board for LPC1769 with CMSIS DAP probe       2.3.2 EA LPCXpresso BaseBoard    2.2 Importing the LPCOpen examples    2.4 Building the demo applications    2.5 Running the demo applications       2.5.1 lwip_tcpecho_sa demo       2.5.2 webserver demo Appendix A - References I hope you can benefit from this post, if you have questions please let me know.   Best Regards! Carlos Mendoza

At the time of the latest update to this article, the latest silicon revision of the LPC55S6x is revision 1B. Since Nov,2019, all the LPCXpresso55S69 EVK boards marked as Revision A2 or A3 are equipped with revision 1B silicon. Initial production boards that have 0A silicon installed are marked Revision A1.                                     NXP introduced its new debug session request functionality on silicon revision 1B. For some IDE versions, the method of initiating a debug session is designed for current 1B silicon revisions and will result in an endless loop when used on older revision 0A parts due to the older revision not implementing some aspects of the handshake protocol. The protocol for this debug connection method, including handling of both 0A and later silicon revisions correctly, is included in the latest LPC55S6x/S2x/2x User Manual, section Debug session protocol.   IDE Considerations MCUXpresso IDE MCUXpresso IDE v11.0.1, incorrectly only supports silicon revision 1B debug session requests and cannot silicon to revision 0A parts in some situations. When connecting LPCXpresso55S69 Revision A1 board, you may have connection error like this: NXP released an MCUXpresso IDE v11.0.1 LPC55xx Debug Hotfix1 for this issue. Please follow the steps to fix the issue below if you have to use IDE v11.0.1 with silicon revision 0A; however it is recommended to update to the latest version of the IDE instead of taking this approach: https://community.nxp.com/community/mcuxpresso/mcuxpresso-ide/blog/2019/10/30/mcuxpresso-ide-v1101-lpc55xx-debug-hotfix IAR According to our test: IAR Embedded Workbench for ARM v8.42 and later can support both silicon revision 1B and 0A production without issue, which can be downloaded from https://www.iar.com/iar-embedded-workbench/tools-for-arm/arm-cortex-m-edition/ Note: The IAR 8.50.5 changed the CMSIS-DAP debug support for trustzone feature. There is known debug issue with the combination of IAR 8.50.5+SDK2.8.0. Thus our recommendation is:        Use IAR 8.50.5 with SDK2.8.0       Use IAR 8.40.2 with SDK 2.7.1   Keil MDK Both Keil MDK v5.28 and v5.29+ latest LPC55S69 pack v12.01 can support silicon revision 1B without problem but cannot support silicon revision 0A. LPC55S69 Revision 0A vs. 1B differences summary Silicon Revision 0A production 1B production Board Revision A1 A2 Deliver Date Before Nov,2019 After Nov,2019 Debug Access handshake Supported but not required. Handshake signaling partially supported Required Secure Boot Revision SB2.0 SB2.1 Maximum CPU Frequency 100MHz 150MHz IDE revision required 1.      MCUXpresso IDE v11.0.0 and older 2.      MCUXpresso IDE v11.0.1 + hotfix1 3.      MCUXpresso IDE 11.1 and later MCUXpresso IDE v11.0.0 and newer SDK version SDK2.5 and newer are supported; SDK2.6.3 and newer are recommended SDK2.6.3 and newer     LPC55S69 Defect Fix: 0A vs. 1B 0A Production 1B Production Defect: For PRINCE encrypted region, partial erase cannot be performed Fixed Defect: For PUF based key provisioning, a reset must be performed Fixed Defect: Unprotected sub regions in PRINCE defined regions cannot be used. Fixed Defect: Last page of image is erased when simultaneously programming the signed image and CFPA region Fixed Defect: PHY does not auto-power down in suspend mode Fixed For more detail, see Errata sheet LPC55S6x which can be downloaded  from NXP web site.   Pre-production Silicon: Note that NO BOARDS WERE EVER SOLD THROUGH DISTRIBUTION WITH PRE-PRODUCTION SILICON. In case you have board marked with Revision 1, 2 ,A, or A1 board with 1B silicon, contact NXP to ask for production replacement.   Get Silicon Revision: The silicon revision info is marked on the chip and board revision is marked on the board silkscreen. For silicon revision marking information, please consult LPC55S6x Data Sheet section 4. Marking . Below is an example of silicon revision marking information where revision is highlighted in red: The user application can also get the silicon revision through chip revision ID and number: SYSCON->DIEID:     The English and Chinese version documents are attached.  

As a free and open-source graphics library, LVGL provides great convenience for related series of chips in creating animations, building advanced graphics and building various blocks. LVGL has been integrated into the MCUXpresso SDK package, which can be imported either through the SDK download or directly in the GUI Guider. GUI-Guider is a ready-to-use GUI from NXP. On the basis of being free for NXP equipment, it has a series of advantages such as convenient operation, automatic programming, Chinese and English interface and input. The following takes the LPC54S018 development board as an example, by creating a simple UI interface, to let everyone familiar with its basic operation process and usage. Create new project Select V8 lvgl version, LPC54S018 development board, EmptyUI, set the name and path, click Finish Fig.1 Set the overall background Drag Widget Tab to the GUI Editor, and resize it to full screen size. Fig.2 Add time display and to-do functions. 1) Change the Tab Content1 name to Clock in the red box on the right. Fig.3 2) Drag aclock into editor, adjust its size and position, and set the time according to the red box in Figure 4. Fig.4 3) Drag the dclock clock into the editor, adjust its size and position, and set the time according to the red box in Figure 5. Fig.5 4) Drag the checkbox into editor, adjust its size and position, and edit its content according to Figure 6. Fig.6 In the second Tab content, add a simple counting function and set the progress bar to interact with it. 1) Add a background. Click Import to import the background image, in the widget, drag the image into the editor, set the size and position, select the imported image in the image path and set its transparency, as shown in Figure 7. Fig.7 2) Add count value, progress bar and button. Figures 8, 9 and 10. In Figure 8, when adding a progress bar, set the starting value in the second step. The range value of the progress bar is set by lv_bar_set_range(guider_ui.screen_progress_bar, 0, 100) which can be added to a key event, executing on every click. Therefore, it is recommended to add this code to the subsequent export file costomer.c, and set it once during initialization. Fig.8 Fig.9 Fig.10 3) Add some explanatory text to the progress bar. The operation steps are shown in Figure 11. Fig.11 4) Create an event in the corresponding button, select Customer Code, write the corresponding code, and complete the interaction. Take the ADD button as an example, as shown in Figure 12. Fig.12 In the Tab third content, 3D animation effect is shown. 1) Set the 3D picture. Select 3Dimg, drag it into the editor, set the image in the image path, and then select the rotation center and rotation angle, as shown in Figure 13. Fig.13 2) Set the display switch. Turn on the switch to display the 3D picture, and when the switch is turned off, the picture disappears. Such as Figure 14. Fig.14 In the fourth Tab content, add “help”. 1) Add logo. Add img, import image to set transparency. Fig.15 2) List the first three modules. Drag the list Widget into the editor, create new lines and modify pictures and texts. After completion, generate the code as shown in Figure 16. The results can be directly displayed by simulation or imported into the development board. Figure 17 shows the simulator and selectable target. The simulation results are shown in Figure 18. There are two ways to download the design to the development board. One is to select the available IDE in Figure 17 and download it directly through GUI Guider. The second is to export the source files first, replace them one by one in the relevant SDK demo code, build with application code in IDE and download/debug with IDE debugger. Fig.16 Fig.17 Fig.18 Video Class : https://www.youtube.com/watch?v=QM52Nu16zKQ  

Note: This document provides a simple description, the details about flashloader can be found at Getting Started with LPC540xx Flashloader User's Guide.pdf which is located in SDK_2.5.0_LPCXpresso54S018\middleware\mcu-boot\doc   Download LPC54S0xx SDK.   Compile the flashloader project to generate flashloader.bin  The project is located in sdk\boards \lpcxpresso54s018\bootloader_examples\flashloader   Use dfu-util.exe or IDE to load flashloader.bin into RAM. dfu-util can be downloaded from http://dfu-util.sourceforge.net/releases/ Configure the ISP pins and then reset the chip to make the chip to enter USB1 DFU boot mode. Boot mode ISP2 PIO0_6 pin ISP1 PIO0_5 pin ISP0 PIO0_4 pin Description USB1 DFU boot LOW LOW HIGH USB DFU class is used to download image over the USB1 high-speed port into SRAM. Connect the LPC54S0xx device USB1 high-speed port and PC with USB. The following is the command line to load the flashloader.bin: $ dfu-util.exe –D flashloader.bin   Use blhost to program/erase LPC540xxM/LPC54S0xxM flash Once the flashloader binary is downloaded and starts its execution on the LPC54S0xx platform and there remains a physical USB connection between the LPC54S0xx platform USB1(High-Speed) and host, the flashloader will be ready to receive the commands. blhost -u 0x1fc9,0x01a2 -- get-property 12 blhost -u 0x1fc9,0x01a2 -- fill-memory 0x2000d000 4 0xc0000004 blhost -u 0x1fc9,0x01a2 -- configure-memory 0xa 0x2000d000 blhost -u 0x1fc9,0x01a2 -- get-property 25 0xa blhost -u 0x1fc9,0x01a2 -t 100000 -- flash-erase-region 0x10000000 0x100000 blhost -u 0x1fc9,0x01a2 -t 100000 -- write-memory 0x10000000 xxx.bin Note: xxx.bin is the target file which needs to be downloaded to the flash.   Author: Hao Liu  Thanks for Hao Liu.

Some customers want to generate CRC checksum during compile project, while the GUN tool chain in MCUXpresso IDE doesn’t include CRC checksum calculation function, so we need  the help of CRC checksum tools. In this article, use SRecord. About detail theoretical knowledge of SRecord, please refer to https://mcuoneclipse.com/2015/04/26/crc-checksum-generation-with-srecord-tools-for-gnu-and-eclipse/ In this thread, mainly describe the steps about how to generate CRC checksum with MCUXpresso IDE post-build, through a hands on.   Environment: LPC54S018 chip MCUXpresso IDE SRecord tool (http://srecord.sourceforge.net/)   Purpose: Generate and place CRC checksum to 0x10000170 of LPC54s018 after compile project. In image header for LPC540xx devices, the offset 0x10 is crc_value, in LPC54s018 , the address is 0x10000170. so we need save CRC checksum value in  this  place.   Steps: Import SDK demo “led_blinky” into MCUXpresso IDE (Just use this demo to demonstrate).   Enable Compute CRC, because there is one bit in Image header for LPC540xx,Just add “ADD_CRC” or “ADD_CRC =1”， build project.     Can check from S19 file: When choose no CRC computation (no defined “ ADD_CRC “ symbol), the data in address 0x0164 bit0 is 1,   When choose compute CRC, the data in address 0x0164 bit0 is 0,        Download SRecord from http://srecord.sourceforge.net/ After download, srec_cat.exe is the main program we used. Place srec_cat.exe utility in a common directory (to reuse it even if you change the project or even the MCUXpresso IDE version). Be sure you add that “common directory” in the PATH environment variable, then be sure the eclipse was restarted to “see” the PATH content.   Create command file crc_add.txt, and place it under" Debug" folder of project. (About detail commands, please refer to SRecord Reference Manual.) # srec_cat command file to add the CRC and produce application file to be flashed # Usage: srec_cat @filename #first: create CRC checksum lpcxpresso54s018m_led_blinky.srec # input file -fill 0xFF 0x10000180 0x10010000 # fill code area with 0xff -crop 0x10000180 0x10010000 # just keep code area for CRC calculation below (CRC will be at 0x1FFFE..0x1FFFF) -CRC16_Big_Endian 0x10000170 -CCITT # calculate big endian CCITT CRC16 at given address. -crop 0x10000170 0x10000172 # keep the CRC itself #second: add application file lpcxpresso54s018m_led_blinky.srec # input file -fill 0xFF 0x10000180 0x10010000 # fill code area with 0xff -crop 0x10000000 0x10000170 0x10000172 0x10010000 #keep all except CRC #finally, produce the output file -Output # produce output lpcxpresso54s018m_led_blinky_crc.srec   Add post-build command to create srecord file with CRC checksum. arm-none-eabi-objcopy -v -O srec "${BuildArtifactFileName}" "${BuildArtifactFileBaseName}.srec" & srec_cat.exe @CRC_add.txt   7） Build project, the .srec with CRC checksum file will under Debug folder:         Pay attention: For the format of image header of LPC540xx devices, we need enable compute CRC and put the CRC value in the specific address. while for other chips, maybe do not need enable, and also can place it in your own address.   Reference: https://mcuoneclipse.com/2015/04/26/crc-checksum-generation-with-srecord-tools-for-gnu-and-eclipse/        

This document is an introduction to the Programmable Logic Unit (PLU) provided for the LPC804 MCU device. PLU is used to create small combinatorial and/or sequential logic networks including simple state machines. This allows to replace external components like the 74xx series, which are used for the glue logic with the microcontroller and external devices, making simple the PCB and saving design costs. Figure 1. LPC80x MCU families The PLU is comprised of an array of 26 inter-connectable, 5-input Look-up Table (LUT) elements, and 4 flip-flops.  Each LUT element contains a 32-bit truth table (look-up table) register and a 32:1 multiplexer. During operation, the five LUT inputs control the select lines of the multiplexer. This structure allows any desired logical combination of the five LUT inputs. Figure 2. PLU Features The PLU is used to create small combinatorial and/or sequential logic networks including simple state machines. The PLU is comprised of an array of 26 inter-connectable, 5-input Look-up Table (LUT) elements, and 4 flip-flops. Eight primary outputs can be selected using a multiplexer from among all of the LUT outputs and the 4 flip-flops. An external clock to drive the 4 flip-flops must be applied to the PLU_CLKIN pin if a sequential network is implemented. Programmable logic can be used to drive on-chip inputs/triggers through external pin-to-pin connections. A tool suite is provided to facilitate programming of the PLU to implement the logic network described in a Verilog RTL design.   Advantages Some advantages of the PLU are: Replace the combinational logic of the 7400 series. State machine design using Flip-flop. Address decoder. Pattern match. Low-power application. PLU works in deep-sleep and power-down mode. Programmable so PLU can be reprogrammed and reused. Seamless connection using SWM and PLU. Pin description There are up to six primary inputs into the PLU module, one clock input, and eight primary outputs. All the inputs are connected directly to the package pins via chip-level I/O multiplexing.  All these pins can be enabled by configuring the relevant SWM register (PINASSIGN_FIXED0). A particular logic network may not require all of the available inputs or outputs. The user can specify which inputs and outputs to use, and which package pins those inputs and outputs will connect to as part of the overall top-level IO configuration. Registers Programming the PLU to implement a particular logic network involves writing to the various Truth Table registers to specify the logic functions to be performed by each of the LUT elements, programming the Input multiplexer registers to select the five inputs presented to each LUT, and programming the Output multiplexer register to select the eight primary outputs from the PLU module. Programming of all of these registers is performed only during initialization. Table 1. PLU registers PLU Shield board with LPCXpresso804 The OM40001 package includes a shield board for use with the LPCXpresso804 board when prototyping programmable logic unit (PLU) designs. The PLU shield provides the following features to assist with this type of development: 5 slide switches to enable 5 possible PLU inputs to be connected to VDD (marked as VCC on the Shield) or GND through a resistor (to set those inputs to a logic 1 or zero). 8 LEDs with jumpers to connect/disconnect possible PLU outputs for visual status indication. Push button option for momentary / edge signal inputs. Low-frequency oscillator with 1024Hz and 8Hz outputs. The PLU shield also includes a test circuit that can be used to implement a simple continuity tester. Several signals from the LPC804 used on the PLU Shield are shared with other functions on the main LPCXpresso804 board. Please review jumper settings on the LPCXpresso804 board carefully before installing the PLU Shield. https://www.nxp.com/docs/en/user-guide/UM11083.pdf  Figure 3. LPCXpresso804 + PLU Shield = PLU demo board   PLU input options On/off switches S1 through S5 connect possible PLU inputs to VDD or GND via a resistor, enabling those inputs to be driven to a known, fixed state. PIO0_8 is connected to a push button (S6) and a 100kohm pull up to VDD; PIO0_8 will be grounded when the button is pressed. Table below shows these connections. Table 2. PLU input on/off switches. A digital oscillator circuit is also included on the Shield, with 1.024kHz and 8Hz outputs available. LPC804 signal PIO0_1 can be connected to these oscillator signals in order to provide a low-speed clock to the flip-flops in the PLU block. The center pin (2) of JP12 connects to PIO0_1, so a jumper can be placed onto JP12 to connect this signal to the required clock (see markings on the Shield silk screen.) An external clock can be provided to the PLU by connecting it to the center pin of JP12. PLU output options LEDs are used to monitor the PLU outputs. Due to the limited number of pins on the chip/board, some of the inputs and outputs are shared. Table 3. PLU shield LEDs. PLU examples You have two options to find a PLU example: Using the SDK for the LPCXpresso804. You can download the SDK for the LPCXpresso804 from Welcome | MCUXpresso SDK Builder The PLU project is a simple demonstration program of the SDK PLU driver. In this example, a number of switches are used act as PLU inputs and LEDs are used to monitor the PLU outputs to demonstrate the configuration and use of the Programmable Logic Unit (PLU). Using the LPC804 Example Code Bundle. Code Bundle, containing source code for drivers, example code and project files. You can download it from LPCXpresso804 board for LPC804 Microcontroller (MCU)|NXP  It is recommended to use the PLU configuration tool. Please check the following links for more details. PLU Tool Direct, LUT-based design: https://www.nxp.com/video/part-2-plu-tool-direct-lut-based-design:Part2-PLU-config-tool-verilog PLU Tool Schematic design: https://www.nxp.com/video/part-3-plu-tool-schematic-design:Part3-PLU-config-tool-schematic PLU Tool Importing Verilog files: https://www.nxp.com/video/part-4-plu-tool-importing-verilog-files:Part4-PLU-config-tool-directlut

In some early LPC products, such as LPC11xx, LPC17xx, LPC18xx, LPC40xx, LPC43xx, LPC8xx, etc, CRP is used to utilize code protection. CRP has three different security levels: Figure 1 shows the security levels of CRP1, CRP2, and CRP3. Figure 1 The LPC55 series (LPC55(S)0x, 1x,2x, and 6x) uses Secure boot and Protected Flash Region (PFR) configuration instead of CRP for security protection. The part number with S (eg. LPC55S) supports Secure boot, for instance, LPC55S28 and LPC55S06. However, non-S series products, such as LPC5506, LPC5528,  can only utilize code protection by configuring FPR related fields. CRP2 is the most commonly used protection level. With CRP2, SWD access is blocked, so users can not read, write, or erase Flash via SWD or ISP. In addition, users cannot erase part of Flash to modify existing code. Once in CRP2 mode, Flash can only be recovered by Mass Erase Flash, which effectively prevents attacker from reading and modifying the Flash code. Unfortunately, the LPC5500 device such as LPC55(S)0x, 1x,2x,6x doesn't have exactly the same functional mechanism as the CRP2, which is questioned by many users. However, if we need to achieve the same functionality as CRP2, we can configure CMPA to disable ISP and SWD debugging port. 1.   Disable ISP Customer Manufacturing/Factory Configuration Area (CMPA) is part of the PFR, Configure BOOT_CFG to select whether the ISP mode is enabled. Table 1 shows the field table starting with 9E40 word address in CMPA. ISP control domains have been marked in red (as shown in Table 1). Table 2 shows the mode selection of ISP domains, 111 is ISP disabled. If the ISP mode is disabled, set BOOT_CFG to 0b1110000. Word Address（HEX） Byte Address Field Description 6 5 4 3 2 1 0 9E40 9E400 BOOT_CFG Default ISP mode 0 0 0 0 9E404 SPI_FLASH_CFG 0 0 0 0 0 0 0 9E408 USB_ID USB Vendor ID 9E40C SDIO_CFG 0 0 0 0 0 0 0 9E41 9E410 CC_SOCU_PIN ISP_CMD_EN MCM33_DBGEN 0 0 0 0 0 9E414 CC_SOCU_DFLT ISP_CMD_EN MCM33_DBGEN TAPEN SPIDEN SPNIDEN DBGEN NIDEN Table 1 Default ISP mode Bit 【6：4】 Auto ISP 000 USB_HID_MSC 001 UART ISP 010 SPI Slave ISP 011 I2C slave ISP 100 Disable ISP 111 Table 2 2.   Disable SWD The DCFG_CC_SOCU is a configuration that specifies debug access restrictions per debug domain. These access restrictions are also referred as constraint attributes in this section. The debug subsystem is sub-divided into multiple debug domains to allow finer access control. Figure 2 shows debug domains and their corresponding control bit position in DCFG_CC_SOCU. Logically, DCFG_CC_SOCU has two components: SOCU_PIN and SOCU_DFLT. The SOCU_PIN and SOCU_DFLT registers are used together to define SWD debug access for the module. Which is logically composed of two components: SOCU_PIN: A bitmask that specifies which debug domains are predetermined by device configuration. SOCU_DFLT: Provides the final access level for those bits that the SOCU_PIN field indicated are predetermined by device configuration. In another words, set the corresponding bit of SOCU_PIN and SOCU_DFLT register to 1 at the same time to enable the module. This module is disabled by setting the corresponding bits of the SOCU_PIN and SOCU_DFLT registers to 0 simultaneously. See Figure 2. Figure 2 Note that the default value of CC_SOCU_PIN and CC_SOCU_DFLT in LPC55 PFR are all zeros. Therefore, in this case, although SOCU_PIN and SOCU_DFLT are both 0, the bit reverse rule is not met (Figure 3 below). Therefore, all debugging permissions are enabled by default when CC_SOCU_PIN and CC_SOCU_DFLT are all 0. Figure 3 Note: the distinction between CC_SOCU_PIN(CC_SOCU_DFLT) and SOCU_PIN(SOCU_DFLT). The former with CC_ includes the reverse bit of the latter. For example, if SOCU_PIN and SOCU_DFLT are set to all zeros and the reverse bit is set to 1, all SWD modules are disabled. Figure 4 3. Implementation The following uses LPC5506 as an example to configure the CMPA field: 3.1  Disable ISP and SWD Figure 5 Keep the default CMPA values except for the two highlighted in red in Figure 5. 1) Set BOOT_CFG to 0x70 to disable ISP. 2) Set all SOCU_PIN and SOCU_DFLT to 0, and set all reverse bits to 1. That is, disable all debug accessing subdomains. 3.2 Enable ISP and SWD Figure 6 Keep the default CMPA values except for the two highlighted in red in Figure 6. 1) Set BOOT_CFG to 0x00 to enable Auto ISP. 2) Restore the default values of DCFG_CC_SOCU, that is, CC_SOCU_PIN and CC_SOCU_DFLT to all zeros. in this case, all debug permissions are restored (turned on) because the rule of bit reversal is not met (see Part 2 of this article). 3.3 Code Implementation Enable or disable the SWD and ISP functions by serial command (1 or 0). Figure 7 The demo code is attached. This routine has been tested on the LPCXpresso55S06 development board. NOTE：     As system security requirements and the attack surface evolves, it is important for customers to understand the types of attacks (especially advanced physical attacks) which NXP does not claim to protect against, or strongly mitigate, so that appropriate mitigation can be taken by the customer at the system level if necessary.  

To help you get started with the LPC800 Mini-Kit, we've put together a few basic resources for you here. LPC800 Mini-Kit Code Base The LPC800 comes populated with an LPC810 MCU in a DIP8 package. The LPC810 package a lot of peripheral punch into a small, extremely affordable package, but as with any deeply embedded device, it's always a challenge to fit the most code and functionality possible into the smallest device available. The LPC810 with 4KB flash and 1KB SRAM is no exception. To help you get started writing light-weight, but easy to understand code in C, we've put together a basic code base for the LPC810 Mini-Kit based around NXP's free LPCXpresso IDE, which uses the free GNU toolchain beneath the surface. The latest version of the code can be viewed and downloaded online on github (LPC810 Code Base), or you can download the latest version directly. Board Schematic The schematics for the LPC800 Mini-Kit are available for download here. See what the LPCWare community did with it! In 2013, NXP ran the LPC800 Simplicity Challenge, and the LPCWare community showed amazing inventiveness in what they created. Check out what they did on our LPC800 campaign pages. Further LPC800 Resources In addition to the LPC800 Mini-Kit Code Base above, you may find some of the following links useful working with the LPC810: LPC810 Product Page on NXP.com LPC800 Switch Matrix Configuration Tool Introducing the LPC800 Videos on YouTube LPC800 Switch Matrix: Making life easier one pin at a time (LPCNow.com) LPC800 LPCXpresso Board Schematics LPCXpresso Forum (for LPCXpresso related support) Tutorial: Getting Started with the LPC810 (Adafruit.com) Programming the LPC800 Mini-Kit with Flash Magic The LPC800 mini board can be programmed using any SWD debugger and your favorite IDE -- NXP's own LPCXpresso, as well as IAR, Keil uVision, and Crossworks for ARM all support the LPC800 out of the box! -- but you can also use an inexpensive UART/USB adapter and ISP mode to program the flash memory on the LPC810. What You'll Need A USB to UART cable or adapter, such as FTDI's popular 'TTL-232R-3V3' cables or a breakout based on the FT232RL chipset The latest version of the free Flash Magic tool​ Configuring the LPC800 Mini Board The first step you will need to do is connect you UART to USB adapter cable to the 'FTDI' header on the top of the LPC800 Mini Board. The pin layout is setup to match FTDI's popular cables by default, specifically the 'TTL-232R-3V3'. Other adapters can of course be used, but you will need to connect the GND, VCC, TXD and RXD pins in the right location yourself. FTDI's TTL-232R-3V3 cable is shown connected here as a reference: LPC800-mini-board The next step is placing the LPC810 in 'ISP' mode. This is accomplished by pulling PIO0_1 'low' during reset, which causes the bootloader to enter ISP mode. The LPC800 mini board conveniently has an 'ISP' switch – the white button in the bottom left-hand side of the board – which we can hold down to pull the ISP pin low. While continuing to press the ISP button, press and then release the 'RESET' button (the red button on the opposite side of the board). This will cause the board to reset, the internal bootloader will see that the ISP pin is low, and it will enter ISP mode where we can program the flash in Flash Magic using the on-chip UART0 peripheral. Configuring Flash Magic for the LPC810 The next step requires you to download and install the latest version of Flash Magic if you haven't already done so. It's available for free at http://www.flashmagictool.com/. Once installed, open the tool, and the run through the following steps: Setup the 'Communications' options: Select LPC810M021FN8 as your target device Set your COM port to whatever port your USB to UART adapter enumerated as (you can find this in the device manager in Windows) Set the Baud Rate to 115200, or whatever matches your USB to UART adapter Make sure that the 'Interface' is set to 'None (ISP)' Set the Oscillator to '12', which matches the speed of the IRC used by the bootloader You can double-check all of your communications settings and connection by selecting the 'ISP > Read Device Signature …' menu item. If you are in ISP mode and properly connected, with the right 'Communications' settings, you should see something similar to the following screen:FlashMagic Device IDIf you get an error message, double check your connections and your settings in Flash Magic, making sure you are actually in ISP mode on the LPC810, and that you've selected the right COM port. Check the 'Erase blocks used by Hex File' checkbox in the 'Erase' section. Select your hex file in the 'Hex File' section: Use the 'Browse' button to point to the Intel Hex file generated by your toolchain or IDE (for example, LPCXpresso). You can also use one of the sample .hex files available here if you don't have a .hex file ready yet. You should end up with Flash Magic configuration as follows ('Verify after programming' is optional): Flash magic settings: Now click the 'Start' button to program the flash … … and finally, once the device has been programmed, reset your board (via the red 'Reset' button). If at some point you want to change your firmware, simply repeat the process of re-entering ISP mode by holding the ISP pin low, resetting the LPC810, releasing the ISP pin, and the programming the device via Flash Magic again. Known issues There is an issue with some of the LPC810 DIP8 parts that are populated on the mini board that prevents the analog comparator from functioning. To see if the part on your board is affected, locate the date code on the top of the DIP8 package (the last line of text on top of the chip). If this line end with either "2X" or "2A", your part is affected. LPC800 mini board schematics Rev AR2.pdf - Attached

This article mainly introduces how to re-enable SWD after disabled. 1.Problem description The Enhanced Code Read Protection (ECRP) of the LPC546xx series is used to configure different security levels for user programs. It is configured when the startup image file offset is 0x20 and is used in combination with OTP. Users of LPC546xx can disable SWD and ISP by configuring ECRP values. Some users need to re-enable SWD after disabling SWD, you can use the J-link commander "unlock LPC5460x" command or re-enable SWD based on LPC-LINK2 CMSIS-DAP these two methods, this article will introduce the two methods in detail. 2.Theoretical analysis and solutions Customer’s example: LPC54605:Configure ECRP to 0x00015800. After disabling SWD, it needs to be restored. When the ECRP value is 0x00015800, we analyze from high to low through  user manual. In ECRP, 31:18 bits are reserved, and 17:16 bits determine the status of SWD. In this example, 17:16=01 ,this means that SWD is disabled.   15: 14 =01, it is not allowed to enter ISP through IAP call.   13: 12 = 01, it is not allowed to enter ISP through pin.   11: 10 = 10, IAP sector erase / write protection is disabled, so sector protect (5:0) is ignored.   At this point,  SWD (17:16) is DISABLED, ISP Entry from ISP (15:14) is DISABLED, and ISP Entry from Bootloader (13:12) is DISABLED, the IAP Mass Erase can still be used to erase the entire Flash to recover a device. as long as the OTP MASS ERASE is ENABLED. If the OTP has been configured and bit 4 is set to 1, that is, disabled mass erase command, the SWD can never be recovered again. When Mass Erase is enabled, the Debug Mailbox is also enabled and allows a debugger to communicate with the bootloader to execute a Mass Erase.   Therefore, the Debug Mailbox can be used to perform Mass Erase operation and restore ECRP settings. To achieve the purpose of re-enabling SWD. 3. Re-enable SWD 3.1 Use "unlock LPC5460x" command re-enable SWD If use J-link debug probe, use "unlock LPC5460x" command to re-enable SWD. Open the J-Link commander and enter unlock to view supported devices. Enter the corresponding chip command. In this paper, the command is unlock LPC5460x. As shown in the picture below:   However, for some chips, this method still fails to re-enable SWD. The following is a method of SWD recovery based on LPC-LINK2 CMSIS DAP. If the unlock LPC546xx command does not work, use the following method. 3.2 LPC-LINK2 CMSIS-DAP re-enable SWD If use CMSIS-DAP debug probe, use below steps to re-enable SWD. IDE: MCUXpresso IDE v11.7.1_9221 or other version. IDE installation path: C:\nxp\ MCUXpresso IDE v11.7.1_9221. The development board emulator firmware uses LPC-LINK2 CMSIS-DAP. Tool script: LPC546xxMassErase.scp. Tool script path: C:\nxp\ MCUXpresso IDE v11.7.1_9221 \ide\binaries\Scripts. The operations are the same for other versions of MCUXpressoIDE and other installation paths. 1) Put LPC546xxMassErase.scp script in the path: C:\nxp\MCUXpressoIDE_11.7.1_922\ide\binaries\Scripts 2) Open a command prompt window. 3) Change the path to C:\nxp\ MCUXpresso IDE v11.7.1_9221 \ide\binaries.   4) Run the redlinkserv -commandline command. 5) After running the redlinkserv -commandline command, you should see the redlink> prompt.   6) Run the load command "C:\nxp\MCUXpressoIDE_11.7.1_9221\ide\binaries\Scripts\LPC546xxMassErase.scp". 7) After executing the load command, you should see that "LPC546xxMassErase.scp" is being loaded. 😎 Execute the run command. 9) After executing the run command, you should see the following message.   In this case, the SWD interface can be used normally. 4.Query ECRP level In the LPC546xx user manual, we can see  ISP-AP command, one function is query the ECRP  level, that is, to view the ECRP configuration of this chip.   From the log in part 3, we can see the returned ECRP level:   However, there is no explanation in the user manual, so here we show the meanings of each bit. There is a table translation from the ECRP level user defined and the ECRP definition used by the ROM code: /* Feature bit defines */ #define CRP_JTAG_EN_BIT         (1 << 6) #define CRP_MASS_ERASE_DIS_BIT  (1 << 7) #define CRP_IAP_PROT_EN_BIT     (1 << 😎 #define CRP_ISP_PINS_EN_BIT     (1 << 9) #define CRP_ISP_IAP_EN_BIT      (1 << 10) #define CRP_DBG_MBOX_EN_BIT     (1 << 11) #define CRP_COUNT_MASK          0x3F #define CRP_DEFAULT_FEATURES    0xFFFFFFFF #define CRP_MASS_ERASE_ONLY     (CRP_SECT_ERASE_DIS_BIT) For example: In CRP_JTAG_EN_BIT, 1 is JTAG/SWD enabled and 0 is disabled. It’s corresponding to ECRP value bit 17 and 16. In CRP_MASS_ERASE_DIS_BIT, 0 is Mass Erase allowed and 1 is disallowed. It’s corresponding to the combination of ECRP value bit 0~5, bit 10~11, and bit 14~15. In CRP_IAP_PROT_EN_BIT, 1 is IAP protection enabled and 0 is disabled. It’s corresponding to ECRP value bit 14~15. In CRP_ISP_PINS_EN_BIT, 1 is ISP pin enabled and 0 is disabled. It’s corresponding to ECRP value bit 12~13. In CRP_ISP_IAP_EN_BIT, 1 is ISP in IAP mode enabled and 0 is disabled. It’s corresponding to ECRP value bit 14~15. In CRP_DBG_MBOX_EN_BIT, 1 is ISP-AP or debugger mailbox enabled and 0 is disabled. It’s corresponding the combination of some reserved ECRP bits and OTP setting. Of course, all these ECRP value used by the ROM not only look into the user defined ECRP value but also check the OTP setting. When “Query ECRP Level” is called, it returns the value used by the ROM code, but not the ECRP value programmed in the image by the user. 5.Summary: In the LPC546xx series, even if SWD is disabled, the debugger can communicate with LPC5460x through the Debug mailbox. As long as OTP does not disable Mass Erase, the debugger can ask LPC5460x to perform mass erase through the Debug Mailbox to re-enable SWD functionality. In addition, the article also adds the specific meaning of the value returned by the ISP-AP command.    

This document was made to explain how to regain control of any LPC EVK on brick mode without using an external debugger. Explore the simple way. In some cases, this method forms well and is the easy way, open your IDE and select your project.   At this point you may have a debugger configuration of your last debug session, so, you have similar icons to the image. Open the tab below and select erase. Depending on your debugger configuration you need to select the same icons below. Note: In some cases will be necessary to put your MCU in ISP. And that’s all, could try if the MCU is out the brick mode.   Introduction First, you need to install these tools on your PC. LPCScrypt [LPCScrypt v2.1.2 | NXP Semiconductors]. J-Link Commander. [J-Link Commander (segger.com)]. To understand this document, we need to know that every EVK [Evaluation Kit] can be divided into 2 parts. The debugger on the board Link2 and the target LPC55sXX. Figure 1. Link2 Green square, LPC55sXX Red square This document will describe two methods that must be done in the order mentioned because we will see how to update the firmware of the debugger to use the same board for a self-recovery, this step is necessary for the tool J-Link Commander to recognize the debugger as a Segger probe, then when the update is done the second step should be to enter ISP mode to do a mass erase of the target to get out of the brick mode. Link2 The Link 2 (LPC4370) debugger on the board probe can be configured to support various development tools and IDEs using a variety of different downloadable firmware images. Available firmware images include: J-Link by Segger. LinkServer. By default, the EVK board has the firmware LinkServer on the LPC4322 (dependent on your board), for this proposal we will see how to change to J-Link On-Board. DFU The EVK needs to be prepared to receive this firmware on the debugger, to do that we need to put the board on DFU [Device Firmware Update]. On the schematic need to find the DFU jumper to put on the board, the image below is an example of different EVKs check Figure 2.   Figure 2. DFU from different boards. Then connect it to the PC. Note: The firmware update is completely reversible. LPCScrypt Once installed on the PC we need to locate these files of the installation. Root example: C:\nxp\LPCScrypt\scripts When you have the board on DFU, connecting the USB Llink2 to the PC and then RUN the Scrypt (program_JLINK) in CMD check Figure 3. Press any key to continue… Figure 3. Flash firmware of J-Link in DFU mode. Successfully done, at this moment the EVK has the firmware of J-Link Segger. Review the Figure 4. Figure 4. The firmware was flashed successfully. Remove the USB cable to remove the DFU jumper with the board unpowered. ISP Brief of ISP (In System Programming) this method is used to recover a part programmed with a corrupted image which is not detectable by ROM. So, to enter this mode the user needs to put a jumper in the ISP header pins, search for this in the schematic, then connect to the PC and check Figure 5.     Figure 5. ISP image examples from different boards. J-LINK Commander Open the software and if the communication is right the message will appear J-Link via USB… OK check Figure 6. Figure 6. The EVK is now communicating to the tool J-Link Commander. Commands To start the communication needs to send the command “connect”. Then the tool shows your last target (if you use it) and use the next command “?” to change the target review Figure 7. Figure 7. Review the target. In the new popup window in the green area, you need to put the name of the target, take care you do not put the debugger check Figure 8. Figure 8. In the green area, you need to put the matricula of the MCU target. Example [LPC55s16 or LPC55s69] depending of your target check Figure 9. Figure 9. If the tool supports the MCU will show below the red square. In the next selections the tool is asking for the interface of communication, the communication of the EVK is SWD, and for that write “S” as SWD. On speed, only click enter without entry. Then this will appear before the connection check Figure 10. Figure 10. The communication is Done. Then use the command “erase” like the Figure 11. Figure 11. The tool indicate the erase is done. Finally disconnect the USB and remove the ISP jumper, then open the IDE and test the blinky led example, or if you wanted you could use the BLHOST. Flashing the MCU using  BLHOST. At this step you could able to use the IDE or use BLHOST. You could install SPSDK if you wanted [Installation Guide — SPSDK documentation]. In ISP mode… blhost -p COMxx  get-property 1 Figure 12. The first command is to check the communication. blhost -p COMxx flash-erase-all Figure 13. Do a mass erase. blhost -p COMxx write-memory 0 C:\root_example\Debug\led_blinky.bin Figure 14. The flashing was done. Remove the ISP jumper and reset your device. Common error LPCScrypt If the message appears “Nothing to boot”, need to be sure the board is connected to the PC with the DFU mode in LINK 2 check Figure 16. Figure 16. The red square is an example of an error communication. J-Link Commander If a similar message appears, “Cannot connect to target”, need to put the target in ISP mode, and return to the first steps with J-Link commander check Figure 18. Figure 18. Show how the communication is not done.