Note:
The example was designed on:
S32M24 PMSM/BLDC Motor Control Evaluation Board | NXP Semiconductors
BLDC/PMSM Low Voltage Motor Control Accessory Kit | NXP Semiconductors
C-project based example is a part of S32M24XEVB-SW application SW (the 6-step example has been the part of the application SW from release 1.1).
Application software contains:
S32M24xEVB_BLDC_6Step_Sensorless - Low-level drivers of RTD and S32 Design Studio Configuration Tools (S32CT) are used to demonstrate a 6-step sensorless application.
Contents
1. Introduction
2. System concept
3. Sensorless BLDC control
3.1. Overview of the brushless DC motor
3.2. Output voltage actuation, PWM technique, current and BEMF measurement
3.3. Position estimation based on BEMF zero-crossing detection
3.4 States of the sensorless BLDC control based on BEMF zero-crossing detection
4. Software implementation on the S32M244
4.1. S32M244 – Key modules for BLDC 6-step control
4.2. S32M244 Device initialization
4.2.1. Clock configuration and power management
4.2.2. FlexTimer Module (FTM)
4.2.3. Trigger MUX Control (TRGMUX)
4.2.4. Programmable delay block (PDB)
4.2.5. Analog-to-digital converter (ADC)
4.2.6. Low Power Serial Peripheral Interface (LPSPI)
4.2.7. Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
4.2.8. Port control and pin multiplexing
4.2.9. Interrupt configuration
4.2.10. Low Power Interrupt Timer (LPIT) configuration
4.2.11. Application Extension (AE) configuration
4.3. Software architecture
4.3.1. Introduction
4.3.2. Application data flow overview
4.3.3. State Machine
4.3.4 Application timing and interrupts
4.3.5 Zero crossing detection algorithm
4.3.6 Speed evaluation, motor current limitation and control
4.3.7. AMMCLIB Integration
5. FreeMASTER and MCAT user interface
6. Conclusion
7. References
1. Introduction
This article describes the design of a 3-phase Brushless DC (BLDC) motor control drive using S32M244 NXP integrated solution.
Following are the supported features:
3-phase BLDC speed control based on Six-step commutation control
Shaft position obtained by BEMF (Back Electromotive Force) voltage zero-crossing detection technique
DC-bus current, DC-bus voltage and BEMF voltage sensing
Motor speed determined by BEMF zero-crossing period
Application control user interface using FreeMASTER debugging tool
Motor Control Application Tuning (MCAT) tool
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2. System concept
The system is designed to drive a 3-phase BLDC motor. The application meets the following performance specifications:
Targeted at the S32M24xEVB-C064/L064 Evaluation Board (refer to dedicated user manual for S32M24xEVB available at www.nxp.com) See section References for more information.
Control technique incorporating:
Six-step commutation control of 3-phase brushless DC motor without position sensor
Rotor position is obtained by BEMF voltage zero-crossing detection technique
Closed-loop speed control with action period 1ms
Bi-directional rotation
Motor current limitation
Alignment and start-up
50μs current sampling period
Automotive Math and Motor Control Library (AMMCLIB) – Speed control loop built on blocks of precompiled SW library (see section References)
FreeMASTER software control interface (motor start/stop, speed setup)
FreeMASTER software monitor
FreeMASTER Motor Control Application Tuning (MCAT) tool (motor parameters, speed loop, sensorless parameters)
FreeMASTER software MCAT graphical control page (required speed, actual motor speed, start/stop status, DC-Bus voltage level, DC-Bus current, system status)
FreeMASTER software speed scope (observes actual and desired speeds, DC-Bus voltage and DC-Bus current)
FreeMASTER software high-speed recorder (six-step commutation control quantities)
DC-Bus over-voltage and under-voltage, over-current, overload and start-up fail protection.
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3. Sensorless BLDC control
3.1. Overview of the brushless DC motor
The description of fundamental brushless DC motor principles, overview of electronic commutation control and speed/torque control of BLDC motor can be found in NXP application note AN12435: 3-phase Sensorless BLDC Motor Control Kit with S32K144, chapters 3.1., 3.1.1., 3.1.2.
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3.2. Output voltage actuation, PWM technique, current and BEMF measurement
The 3-phase voltage source inverter is shown on page 6 of S32M24xEVB schematics, see References. It uses single DC-bus shunt resistor (represented as R134 and R135 in parallel). DC-bus current which flows through the shunt resistor produces a voltage drop which is interfaced to the AD converter of microcontroller through the Digital Programmable Gain Amplifier (DPGA) integrated inside S32M244 . The BEMF voltage dividers for BEMF measurement (used for sensorless 6-step control) are integrated in S32M244. The description of the PWM technique used for BLDC motor control, is described in NXP application note AN12435: 3-phase Sensorless BLDC Motor Control Kit with S32K144, chapter 3.2.
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3.3. Position estimation based on BEMF zero-crossing detection
The position detection based on BEMF measurement and BEMF measurement are explained in NXP application note AN12435: 3-phase Sensorless BLDC Motor Control Kit with S32K144, chapter 3.3. The only difference in conditioning of BEMF voltages and DC Bus current - in case of S32M24x no external dividers for BEMF voltage are needed since these are integrated in S32M24x and voltage drop on shunt resistor is conditioned by S32M24x-integrated DPGA (Digital Programmable Gain Amplifier).
3.4. States of the sensorless BLDC control based on BEMF zero-crossing detection
In order to start and run the BLDC motor, the control algorithm has to go through the following states:
Initialization
Calibration
Alignment (initial position setting)
Start-up (forced commutation or open-loop mode)
Run (sensorless running with BEMF acquisition and zero-crossing detection
3.4.1. Initialization
Initialization of variables relevant for motor control.
3.4.2. Calibration
In this state the DC current measurement calibration takes place.
3.4.3. Alignment
As mentioned previously, the main task for sensorless control of a BLDC motor is position estimation. Before starting the motor, however, the rotor position is not known. The aim of the alignment state is to align the rotor to a known position. This known position enables starting the rotation of the shaft in the desired direction and generating the maximal torque during start-up. During the alignment state, all three phases are powered in order to get the best performance behavior in either direction of shaft rotation. Phase C is connected to the positive DC bus voltage and phases A and B are grounded. The alignment time depends on the mechanical constant of the motor, including load, and also on the applied motor current.
3.4.4. Start-up
In the start-up state, motor commutation is controlled in an open-loop mode without any rotor position feedback. The commutation period is controlled by an open-loop starting curve. The open-loop start is required only until the shaft speed is high enough (approximately 5% of nominal motor speed) to produce an identifiable BEMF voltage.
3.4.5. Run
The block diagram of the run state is represented by Figure 1 and includes the BEMF acquisition with zero-crossing detection in order to control the commutations. The motor speed is estimated based on zero-crossing time periods. The difference between the demanded and estimated speeds is fed into the speed PI controller. The output of the speed PI controller is proportional to the voltage to be applied to the BLDC motor. The motor current is measured and filtered during the BEMF zero-crossing event and used as feedback into the current controller. The output of the current PI controller limits the output of the speed PI controller. The limitation of the speed PI controller output protects the motor current from exceeding the maximal allowed motor current.
Figure 1. Speed control with current limitation
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4. Software implementation on S32M244
4.1. S32M244 – Key modules for BLDC 6-step control
The S32M244 is an integrated solution which comprises MCU and Application Extension (AE). The MCU part includes modules such as the FlexTimer Module (FTM), Trigger MUX Control (TRGMUX), Programmable Delay Block (PDB) and Analog-to-Digital Converter (ADC) suitable for control applications, in particular, motor control applications. These modules are directly interconnected and can be configured to meet various motor control application requirements. Figure 2 shows module interconnection for a typical BLDC 6-step application working in Sensorless mode using single shunt current sensing. The modules are described in further chapters and the detailed description can be found in the S32M24x Series Reference Manual (see section References).
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4.1.1. Modules interconnection
As mentioned earlier, S32M24x consists of two parts: MCU and AE which are connected together via die-to-die (D2D) connections.
The SPI interface (part of D2D) serves for parameter settings and status monitoring of AE and the rest of D2D interface is used for motor control loop (e.g.: DC bus current reading).
The AE comprises modules vital for motor control such as Gate Driver Unit (GDU) and Digital Programmable Gain Amplifier (DPGA) which allow for using S32M244 in motor control applications with minimum of external components.
The GDU drives the power MOSFETs. The GDU is interconnected with the outputs of FTM via D2D connections.
The shunt resistor voltage drop signal (proportional to DC Bus current) is conditioned by the integrated DPGA which output is connected to the ADC via D2D connection.
DC Bus voltage and BEMF voltages are conditioned via integrated voltage dividers which outputs are connected to the ADC via D2D connection.
The MCU die modules involved in output actuation, data acquisition and the synchronization of actuation and acquisition, form the so-called Control Loop. This control loop consists of the FTM, TRGMUX, PDB, and ADC modules. The control loop is very flexible in operation and can support static, dynamic or asynchronous timing.
Each control loop cycle can be initiated either by FTM initialization trigger init_trig or by FTM external trigger ext_trig. While init_trig signal is generated at beginning of PWM cycle, ext_trig can be generated any time within the PWM period based on the value defined in the corresponding FTM Channel Value register CnV.
FTM trigger signal is routed to hardware trigger input of the PDB module through flexible TRGMUX unit. In S32M24x, there are two ADC modules and two PDB modules that work in pairs. This means that PDB0 is linked with ADC0 and PDB1 is linked with ADC1.
PDB pre-triggers ch0pretrigx are used as a precondition for ADC module. They are directly connected to ADHWTS ports to select ADC channels as well as order of the channels by configurable pre-triggers delays. When ADC receives rising edge of the trigger, ADC will start conversion according to the order defined by pre-triggers ch0pretrigx.
PDB pre-trigger delays must be properly set to allow reliable operation between PDB and corresponding ADC module. When the first pre-trigger is asserted, associated lock of the pre-trigger becomes active until corresponding conversion is not completed. This associated lock is released by corresponding ADC conversion complete flag ADC_SC1[COCOx]. This means that next pre-trigger can be generated only if the ongoing conversion is completed.
FTM0 module is used for commutation control. It is configured to schedule and force commutation events which are determined from the actual BEMF zero-crossing period.
Detailed description can be found in the S32M24x Series Reference Manual (see section References).
Figure 2. S32M244 modules interconnection.
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4.1.2. Modules involvement in digital BLDC control loop
This section will discuss timing and modules synchronization to accomplish BLDC 6-step control on the S32M244 and the internal hardware features.
The timing diagram of the automatic synchronization between PWM and ADC in the BLDC application is shown in Figure 3.
Figure3. Time Diagram of PWM and ADC Synchronization.
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4.2. S32M244 Device initialization
To simplify and accelerate application development, embedded part of the BLDC 6-step sensorless motor control application has been created using S32M244 Real Time Drivers (RTD). S32M244 can be configured either by means of S32 Configuration Tools (CT) - using GUI
or programmed directly using RTD drivers. Peripherals are initialized at beginning of the main() function. For each S32M244 module, there is a specific configuration function that uses S32M244 RTD APIs and configuration structures generated by RTD graphical tools to configure the MCU (as per Table 1).
Detailed RTD documentation can be found in folder created with S32 Design Studio installation (see References).
Table 1. Modules and their configuration functions.
Function
Module
McuClockConfig()
MCU clock configuration
McuCacheConfig()
MCU cache configuration
McuPowerConfig()
MCU power management configuration
McuIntConfig()
MCU interrupt management configuration
McuTrigmuxConfig()
TRGMUX module configuration
McuPinsConfig()
PINs and PORT modules configuration
McuLpuartConfig()
LPUART module configuration
McuAdcConfig()
ADC modules configuration
McuPdbConfig()
PDB modules configuration
McuFtmConfig()
FTM modules configuration
McuSPIConfig()
SPI module configuration
AECConfig()
AE module configuration
AEC_DPGAConfig()
DPGA module configuration
AEC_GDUConfig()
GDU module configuration
AEC_HVMConfig()
HV module configuration
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4.2.1. Clock configuration and power management
S32M244 features a complex clocking sourcing, distribution and power management. To run a core of the S32M244 as well as some MCU peripherals at maximum frequency 80 MHz in normal RUN mode, S32M244 is supplied externally by 16 MHz crystal. This clock source supplies Phase-lock-loop (PLL), which circuit multiplies frequency by 20 and divides by 2 resulting 160 MHz frequency on output. PLL output is then divided by 2 to supply core and system (80 MHz), further divided by two and four to supply bus clock (40 MHz) and flash clock (20 MHz), respectively. This clock configuration belongs to one of the typical and recommended. It is summarized in Table 2.
Table 2. S32M244 clock configuration in RUN mode.
Clock
Frequency
CORE_CLOCK
80 MHz
SYS_CLK
80 MHz
BUS_CLK
40 MHz
FLASH_CLK
20 MHz (max frequency in RUN mode)
This clock configuration can be setup by S32 CT Clocks graphical tool, for further details see the SW example, where the detailed clock settings for the particular peripherals can be found.
Once the clock configuration is set, RTD generates static configuration structure Clock_Ip_aClockConfig[0], the respective RTD API is then called in MCUClockConfig which can be found in the SW example in .../src/Peripherals/peripherals_config.c.
As discussed at the beginning of this chapter, power management of the S32M244 is configured for normal RUN mode. This power mode can be set in S32CT Peripherals graphical tool, Figure 4.
Figure 4. S32M244 power management configuration in S32CT Peripherals tool.
Static configuration generated by RTD is called by the respective RTD API and this is encapsulated in MCUPowerConfig function, which can be found in the SW example in .../src/Peripherals/peripherals_config.c
The same mechanism for peripherals configuration by RTD works for all S32M244 peripherals, which are discussed below.
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4.2.2. FlexTimer Module (FTM)
FlexTimer module (FTM) is built upon a timer with a 16-bit counter. It contains an extended set of features that meet the demands of motor control, including the signed up-counter, dead time insertion hardware, fault control inputs, enhanced triggering functionality, and initialization and polarity control.
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4.2.2.1. Center-aligned PWM mode
FTM3 instance is used in BLDC 6-Step motor control application to generate center-aligned PWM by three complementary channels pairs to control power MOSFETs.
The configuration is shown in Figure 5, FTM3 PWM frequency of 20 kHz is adjusted by Counter Period = 4000, taking 80MHz clock source frequency into account. Note that while Center-aligned mode is selected (up-down counter), the value written into FTM3 modulo register is half of Counter Period - this is done internally by the RTD. To protect power MOSFETs against short circuit, deadtime 0.5μs is inserted for each complementary channels pair in number of clock ticks 40 with default deadtime prescaler 1. This FTM3 configuration can be carried out by using S32CT, FTM_Pwm module, Figure 5. For detailed settings, please see all the settings tabs in Ftm_Pwm module in S32CT Peripherals tool.
Figure 5. S32M244 FTM3 configuration in S32CT.
The double-buffered register FTM3_SWOCTRL is used to control the unipolar PWM pattern as discussed in 3.2. The FTM3_SWOCTRL register controls the PWM output by forcing selected channels into a defined state. The PWM channel which is not SW-controlled is not forced into a SW-defined state but is PWM-controlled. The double-buffered values are applied at each commutation event triggered by FTM0 init_trig . To allow this triggering mechanism, Hardware trigger 0 is enabled in Ftm Synchronization Config tab, Figure 5. The following table shows the SWOCTRL values applied at a commutation event in a particular sector of the six-step commutation sequence.
Table 3. Software control definition in six-step commutation sequence
Sector
FTM3_SWOCTRL
PWM Output settings
0
0x0838
Phase A standard PWM, Phase B low side on, Phase C low/high OFF
1
0x203C
Phase A standard PWM, Phase C low side on, Phase B low/high OFF
2
0x2033
Phase B standard PWM, Phase C low side on, Phase A low/high OFF
3
0x020F
Phase B standard PWM, Phase A low side on, Phase C low/high OFF
4
0x080F
Phase C standard PWM, Phase A low side on, Phase B low/high OFF
5
0x0A0F
Phase C standard PWM, Phase B low side on, Phase A low/high OFF
Alignment 1
0x0A0F
Phase C standard PWM, Phase A low side on, Phase B low side on
PWM off
0x003F
1 Alignment vector is set to allow a commutation sequence starting from sector 0
To allow the application of the double-buffered values outside the commutation event, Hardware trigger 1 is enabled in Ftm Synchronization Config tab, Figure 5. This hardware trigger is generated by writing 1 to the SIM_FTMOPT1[FTM3SYNCBIT] bit.
The duty cycle of the center-aligned PWM is controlled by the FTM3_CnV (n = 0, 2, 4) register values. In up-down counting mode, even channels define both, leading as well as trailing edges. Even channels are set according to:
Equation 1.
To initiate control loop at beginning of the PWM period, Initialization trigger is enabled in FTM Instance Configuration tab as well, Figure 5.
Once the FTM3 setting is completed, RTD generates configuration structure Ftm_Pwm_Ip_BOARD_INITPERIPHERALS_UserCfg3 which, using the respective RTD API Ftm_Pwm_Ip_Init configures FTM3, this is encapsulated in function MCUFTMConfig, which can be found in the SW example in .../src/Peripherals/peripherals_config.c.
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4.2.2.2. Commutation timer for Sensorless mode
FTM0 is used in Sensorless mode to schedule and identify the commutation event. External trigger output signal ext_trig is internally routed to the FTM3 module trigger 0 input in order to perform commutation of the PWM pairs. The commutation event is scheduled by setting the PWM period (CHTM0 CH0 value). When the counter reaches CH0 value, ext_trig is generated and an interrupt is invoked. The ext_trig is also routed to FTM0 trigger 0, what resets FTM0 counter. This ensures FTM0 counter is in the range from 0 to CH0 value (commutation scheduling) and it triggers FTM3 via ext_trig to perform commutation when scheduled.
To be able to schedule long commutation periods at low speeds, the FTM0 counter is configured to run at 625 kHz frequency. This module settings can be configured by S32CT as per Figure 6. In order to make use of RTD APIs, FTM0 is configured as FTM PWM but is used for timing exclusively, the outputs of FTM0 are disabled. For detailed FTM0 configuration, please see all the configuration tabs as per Figure 6 in SW example.
Once the FTM0 setting is completed, RTD generates configuration structure Ftm_Pwm_Ip_BOARD_INITPERIPHERALS_UserCfg0 which, using the respective RTD API Ftm_Pwm_Ip_Init configures FTM0, this is encapsulated in function MCUFTMConfig, which can be found in the SW example in .../src/Peripherals/peripherals_config.c.
Figure 6. FTM0 configuration.
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4.2.3. Trigger MUX Control (TRGMUX)
The TRGMUX provides an extremely flexible mechanism for connecting various trigger sources to multiple pins/peripherals. With the TRGMUX, each peripheral that accepts external triggers usually has one specific 32-bit trigger control register. Each control register supports up to four triggers, and each trigger can be selected from the available input triggers.
To trigger PDB0 and PDB1 modules by FTM3 initialization trigger signal init_trig, TRGMUX needs to be set appropriately.
RTD allows to generate configuration structure Trgmux_Ip_xTrgmuxInitPB that sets all TRGMUX registers to assign trigger inputs with trigger outputs as demanded, Figure 7.
The configuration structure Trgmux_Ip_xTrgmuxInitPB is then used as the argument of Trgmux_Ip_Init() which is encapsulated in .../src/Peripherals/peripherals_config.c
Figure 7. S32M244 TRGMUX configuration in RTD.
In particular, FTM3 initialization trigger signal as a source is assigned to three targets: PDB0, PDB1 and for debug/visualization purposes to TRGMUX output 2. As mentioned before, FTM0 external trigger output is connected to FTM3 hardware trig 0 input and FTM0 hardware trig 0 input for commutation scheduling and control. ADC0 conversion complete flag COCO is assigned to TRGMUX output 5 for debug/visualization.
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4.2.4. Programmable delay block (PDB)
The Programable Delay Block (PDB) is intended to completely avoid CPU involvement in the timed acquisition of state variables during the control cycle. The PDB module contains a 16-bit programmable delay counter that delays FTM3 initialization trigger and schedules ADC channels sampling through PDB pre-triggers delays. When FTM3 initialization trigger is detected on the PDB0 and PDB1 trigger input, PDB0 and PDB1 generate hardware signal to trigger ADC0 and ADC1 channels in order defined by pre-trigger delays, Figure 8.
Figure 8. PDB pre-triggers and trigger output.
PDB pre-trigger delays can be set independently using CHnDLYm registers. Since the PDB0, PDB1 and FTM3 modules are synchronized and share the same source frequency 80MHz, values of the CHnDLYm registers are set using the same time base as for PWM. The following table shows all PDB0 and PDB1 pre-triggers used in BLDC six-step motor control application.
Table 4. PDB0 and PDB1 pre-triggers
State variable
PDB pre-trigger
CHnDLYm value [ticks]
Relation to PWM
Phase BEMF voltage
pdb1_ch0_pretrig0
pdb_delay
At 90% of the active PWM pulse
DC bus current
pdb0_ch0_pretrig0
0
At beginning of the PWM
DC bus voltage
pdb0_ch0_pretrig1
pdb_delay
At 90% of the active PWM pulse
DC bus current measurement is triggered every PWM cycle at beginning of the PWM period by pdb0_ch0_pretrig0. This delay is static value defined only once at the initialization phase. To measure BEMF voltage and DC bus voltage simultaneously towards the end of the active PWM pulse, pdb1_ch0_pretrig0 and pdb1_ch0_pretrig0 pre-trigger delays are dynamically modified according to actual duty cycle:
Equation 2.
A software routine limits pdb_delay to 180 ticks to prevent collision between pdb0_ch0_pretrig1 and pdb0_ch0_pretrig0, at low duty cycles. This limit respects ADC conversion time that typically takes ~1.25µs considering short ADC sample time and 40MHz ADC input frequency. PDB Sequence Error Interrupt can be activated as well as hardware detector.
It should be noticed that CHnDLYx are double buffered registers meaning pdb_delay value is first latched into CHnDLYx buffers and then loaded from their buffers at beginning of the PWM period when 1 is written to SC[LDOK] bit and FTM3 init_trig signal is detected on PDB0 and PDB1 input.
General settings of the PDB module such as clock pre-scaler, input trigger source, loading mechanism for double buffered registers as well as operation mode for pre-triggers can be configured by means of S32CT as shown in Figure 9, for details, see the PDB configuration in the SW example.
Figure 9. S32M244 PDB module and pre-triggers configuration.
RTD generates configuration structures PdbHwUnit_0_BOARD_INITPERIPHERALS and PdbHwUnit_1_BOARD_INITPERIPHERALS for appropriate PDB registers. This configuration is loaded calling .../src/Peripherals/peripherals_config.c/McuPdbConfig().
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4.2.5. Analog-to-digital converter (ADC)
The S32M244 device has two 12-bit Analog-to-Digital Converters (ADCs). These are 32-channel multiplexed input successive approximation ADCs with 16 result registers.
Both ADC instances are triggered independently by two PDBs. ADC channels are sampled in the order defined by PDB pre-triggers. When the first pre-trigger is asserted, associated lock of the pre-trigger becomes active waiting for the conversion complete flag COCO generated by the corresponding ADC channel. This sequence is repeated for each PDB pre-trigger and ADC channel couple.
The configuration in S32CT is shown in Figure 10, see the SW example for details.
Figure 10. S32M244 ADC0 module configuration.
ADC0 channel 0 measures DC bus current, ADC0 channel 1 measures DC Bus voltage. ADC1 channel 0 measures BEMF voltage. Note that the respective BEMF phase voltage is dynamically assigned to ADC1 channel 0 depending on the commutation sector. This happens in FTM0 ISR notification function FTM0_CH0_Notif(), by calling MEAS_SetBEMFPhase().
RTD generates module configuration structures AdcHwUnit_0_BOARD_INITPERIPHERALS, and AdcHwUnit_1_BOARD_INITPERIPHERALS, which take effect calling the respective RTD API in function .../src/Peripherals/peripherals_config/McuAdcConfig().
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4.2.6. Low Power Serial Peripheral Interface (LPSPI)
LPSPI is used as communication interface between S3M244 MCU and AE. Configuration of LPSPI1 by means of S32CT can be seen in Figure 11.
Figure 11. S32M244 LPSPI module configuration.
LPSPI is then initialized using the RTD-generated configuration structure in .../src/Peripherals/peripherals_config/McuSPIConfig().
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4.2.7. Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
LPUART1 is used as a communication interface between S32M244 processor and FreeMASTER run-time debugging and visualization tool. Function .../src/Peripherals/peripherals_config/McuLpuartConfig() initializes LPUART0 module with baud rate 115200, 1 stop bit and 8 bits per channel. This configuration is carried out by RTD’s LPUART driver.
Configuration structure Lpuart_Uart_Ip_xHwConfigPB_0_BOARD_INITPERIPHERALS is configured by means of S32CT as shown in Figure 12.
Figure 12. S32M244 LPUART module configuration.
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4.2.8. Port control and pin multiplexing
BLDC 6-step sensorless motor control application requires following on chip pins assignment:
Table 5. Pins assignment for S32M244 BLDC 6-step sensorless control.
Peripheral
Signal
Pin
Description
ADC0
DCBI
PTB13 / ADC0_SE8
DC Bus current
DCBV
PTA6 / ADC0_SE2
DC Bus voltage
ADC1
HS0V
PTD2/ADC1_SE2
BEMF Phase A
HS1V
PTB4/ADC1_SE6
BEMF Phase B
HS2V
PTB12/ADC1_SE7
BEMF Phase C
FTM3
PWMA_HS
PTA2 / FTM3_CH0
PWM A high-side driver
PWMA_LS
PTA3 / FTM3_CH1
PWM A low-side driver
PWMB_HS
PTB10 / FTM3_CH2
PWM B high-side driver
PWMB_LS
PTB11 / FTM3_CH3
PWM B low-side driver
PWMC_HS
PTC10 / FTM3_CH4
PWM C high-side driver
PWMC_LS
PTC11 / FTM3_CH5
PWM C low-side driver
LPSPI1
SPI_SCLK
PTB14 / LPSPI1_SCK
SPI clock
SPI_SIN
PTB15 / LPSPI1_SIN
SPI data in
SPI_SOUT
PTB16 / LPSPI1_SOUT
SPI data out
SPI_CS
PTB17 / LPSPI1_PCS3
SPI chip select
GPIO
AE_Fault
PTD3
Application Extension fault (active low)
LPUART0
LPUART_In
PTC2 / lpuart_rx
Receive data from FreeMASTER
LPUART_Out
PTC3 / lpuart_tx
Send data to FreeMASTER
TRGMUX
TRGMUX_InitTrg
PTD1 / trgmux_out2
FTM3 Init trigger visualization
TRGMUX_CoCo
PTE11 / trgmux_out5
ADC0 CH1 conversion complete visualization
GPIO
Exec_Meas
PTE15
Toggled pin for execution time measurement
SW0
PTB4
Application control via board button
SW1
PTB5
LED
PTE15
LED indication:
steady lit - ready,
slow flashing - run
fast flashing - fault
This pins assignment can be carried out by means of RTD, Pins tool. Pin assignment of the FTM3 module is shown in Figure 13 as an example.
Figure 13. S32M244 Pins assignment for FTM3 in S32CT.
The RTD-generated configuration structure g_pin_mux_InitConfigArr_BOARD_InitPins and the respective RTD function is then called in ...src/Peripherals/peripherals_config.c/MCUPinsConfig().
Note: At the time of this article publication, ADC0 interleave on pin PTB13 was not available in the S32CT Pins tool, therefore the interleave is set in ...src/Peripherals/peripherals_config.c/MCUPinsConfig() by calling Port_Ci_Port_Ip_SetMuxModeSel(IP_PORTB, 13, PORT_MUX_ADC_INTERLEAVE)
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4.2.9. Interrupt configuration
The configuration of the respective interrupts takes place in RTD Peripherals tool. The interrupts are configured as per the following table:.
Table 6. Interrupts in S32M244 BLDC 6-step sensorless example.
Name
Priority
Description
ADC0_IRQn
2
Zero cross detection, state variables acquisition
FTM0_Ch0_Ch1_IRQn
1
Commutation scheduling
PDB0_IRQn
0
Sequence error reset - presence of sequence errors is normal due to asynchronous commutation and resulting switch-over between ADC channels connected to the respective BEMF voltages.
PDB1_IRQn
0
PORTD_IRQn
1
AE fault detection
LPIT0_Ch0_IRQn
0
Control loop calculation
The configuration of the interrupts in S32CT peripherals tool is shown in Figure 14, see SW example for details.
Figure 14. S32M244 interrupt configuration in RTD.
The interrupt from AE fault is carried out by detection of falling edge on PTD3, this needs to be set in RTD peripherals tool as well, a part of the setting is shown in Figure 15. See the detailed setting in RTD peripherals tool for the module Port_Ci_Icu.
The S32CT -generated configuration structure IntCtrlConfig_0 and the structure for PTD3 interrupt Port_Ci_Icu_Ip_3_Config_PB_BOARD_INITPERIPHERALS and the respective RTD function is then called in src/peripherals/peripherals_config.c/MCUIntConfig().
Figure 15. S32M244 enabling PTD3 falling edge detection.
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4.2.10. Low Power Interrupt Timer (LPIT) configuration
The LPIT channel 0 is employed to control the speed and motor current in a software task. LPIT channel 0 is configured to generate a periodic interrupt every 1 ms. The configuration by means of S32CT is as follows:
Figure 16. S32M244 LPIT configuration.
The S32CT -generated configuration structure LPIT_0_InitConfig_PB_BOARD_INITPERIPHERALS and the respective RTD function is then called in src/peripherals/peripherals_config.c/MCULpitConfig().
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4.2.11. Application Extension (AE) configuration
Configuration of AE is describen in NXP application note AN14454: 3-phase Sensorless PMSM Motor Control with S32M244. Identical AE configuration is used also for this SW example.
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4.3. Software architecture
Figure 17 presents the conceptual system block diagram of the BLDC Six-step control technique working in sensorless mode. This section is focused on the software design of the Sensorless algorithm based on the zero-crossing detection technique.
The application is optimized for S32M244 motor control peripherals to achieve the least possible core involvement in state variable acquisition and output action application. The motor control peripherals (FTM0, FTM3, PDB0, PDB1, ADC0, ADC1) are internally linked together to work independently from the core, and to achieve deterministic sampling of analog quantities and precise commutation of the stator field. The software part of the application consists of different blocks which are described below. The entire application behavior is controlled from a PC through the FreeMASTER run-time debugging tool.
The inputs of the control loop are the measured voltages and current on the power stage, in particular the phase/BEMF voltages, the DC bus current, and DC bus voltage.
From a control perspective, the block diagram can be divided into two logical parts:
Commutation control, where the phase voltages and DC bus voltage are used to calculate the actual position of the shaft. According to the identified position, the next commutation event can be prepared.
Speed/torque control, where the required shaft velocity is compared to the actual measured speed and regulated by the PI controller. The output of the speed PI controller is the duty cycle. The duty cycle is limited by the current PI controller and assigned to the PWM.
Figure 17. System block diagram.
4.3.1. Introduction
This section describes the software design of the Sensorless BLDC Six Step Control framework application. The application overview and description of software implementation are provided. The aim of this chapter is to help in understanding of the designed software.
4.3.2. Application data flow overview
Figure 18 explains the different application states. The figure consists of two interconnected parts:
The speed over time characteristic
The blocks in the lower part of the picture, which show the states of the application and the transitions between respective states
The application software has three main states: the alignment state, the open-loop start state, and the run state. In the run state, the BLDC motor is fully controlled in a closed-loop sensorless mode. After the initialization of the peripheral modules has completed, the software enters the alignment state. In alignment state, the rotor position is stabilized into a known position in order to create the same start-up torque in both directions of rotation. This is achieved by applying a PWM signal to phase C. Phases A and B are assigned with a duty cycle equal to zero; that is, they are connected to the negative pole of the DC bus. The value of the duty cycle on phase C depends on the motor inertia and load applied on the shaft. Such a technique aligns the shaft into position between phase A and B, which is perpendicular to both start-up flux vectors (vectors 0 and 3) generated by the stator winding, and therefore ensures the same start-up torque in both directions of rotation. The duration of the alignment state depends on the motor’s electrical and mechanical constants, the applied current (meaning duty cycle), and the mechanical load.
When the alignment time-out expires, the application software moves to the open-loop start state. At a very low shaft velocity, the BEMF voltage is too low to reliably detect the zero-crossing. Therefore, the motor has to be controlled in an open-loop mode for a certain time period. The very first vector generated by the stator windings needs to be set to a position 90° relative to the position of the flux vector generated by magnets mounted on the rotor. The alignment and first start-up vector are shown in Figure 18 . The duration of the open-loop start state is defined by the number of open-loop commutations. The number of open-loop commutations depends on the mechanical time constant of the motor, including load, and also on the applied voltage (duty cycle). The shaft velocity after an open-loop start-up is approximately 5% of nominal velocity. At a velocity approximately 5% of nominal velocity, the BEMF voltage is high enough to reliably detect the zero-crossing.
After a defined number of commutation cycles, the state changes from the open-loop start state to the run state. From here on, the commutation process based on the BEMF zero-crossing measurement takes place, and the control enters the closed-loop mode.
Figure 18. Flow chart diagram of main function with background loop.
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4.3.3. State Machine
The application state machine is implemented using a one-dimensional array of pointers to state functions, called AppStateMachine[]. The index of the array specifies the pointer to the related application state function. The application state machine consists of the following seven states selected using the index variable appState value.
Possible state transitions are shown in Figure 19.
The application states are listed in the following table:
Table 7. Application states in Sensorless mode
AppState
Application state
Description
0
INIT
The INIT state provides the initial configuration of the PWM duty cycle and initialization of DC bus current offset calibration. The state machine then transitions to the STOP state.
1
CALIB
The CALIB state provides the DC bus current calibration. The state machine then transitions to ALIGNMENT state.
2
ALIGNMENT
In the ALIGNMENT state, the alignment vector is applied to the stator to set the rotor to the defined position. The duration of the alignment state and the duty cycle applied during the state are defined by the ALIGN_DURATION and ALIGN_VOLTAGE macro values accessible in the BLDC appconfig.h header file. The state machine then transitions to the START state.
3
START
In the START state, the motor commutation is controlled in an open-loop without any rotor position feedback. The initial commutation period is controlled by the STARTUP_CMT_PER macro value. Motor acceleration (commutation period multiplier <1) is set by the START_CMT_ACCELER macro value. The number of commutations in the START state is defined by STARTUP_CMT_CNT macro value. All macro values are accessible in the BLDC_appconfig.h header file. The aim of the START state is to achieve an RPM where the zero-crossing event can be reliably detected (BEMF high enough). Once the defined number of commutations is performed, the state machine transitions to the RUN state.
4
RUN
In the RUN state, the BLDC motor is controlled in the closed-loop by the sensorless algorithm (BEMF zero-crossing detection). Speed control and current limitation are performed as described in 4.3.6, “Speed evaluation, motor current limitation and control”. The transition to the INIT state is done by setting the appSwitchState variable to 0.
5
STOP
In the STOP state, the motor is stopped and prepared to start running. Transition to the ALIGNMENT state is performed once the appSwitchState variable is set to 1 and the freewheeling counter expires.
6
FAULT
The fault detection function is executed in the main endless loop, detecting DC bus undervoltage, DC bus overvoltage, DC bus overcurrent, and AE faults. Once any of the faults are detected, the state machine automatically transitions to the FAULT state. The PWM outputs are set to the safe state. To exit the FAULT state, all fault sources must be removed and the faultSwitchClear variable has to be set to 1 to clear the fault latch. The state machine then automatically transitions to the INIT state.
Figure 19. Application state machine
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4.3.4. Application timing and interrupts
Figure 20 shows the application timing and the associated interrupts used for the commutation, zero-crossing and speed control. The grey boxes show the executed interrupt routines versus the phase voltage measurement.
The top row shows the interrupt that is activated when the ADC conversion sequence of BEMF voltage, DC bus current, and DC bus voltage has been completed. In this interrupt, the FTM0 timer counter value is saved as a BEMF measurement reference point. The zero-crossing detection algorithm is executed in each ADC0 conversion complete interrupt after a commutation event. Once the zero-crossing is found, the detection algorithm is disabled until the new commutation event occurs.
The second row shows the FTM0 timer counter interrupt generated at the time of the commutation event. The time between each FTM0 timer counter interrupt is dependent on the actual speed of the motor. Channel of the ADC1 is reconfigured to reflect the change in the phase used for the BEMF voltage sensing.
The last row shows the LPIT channel 0 time-out interrupt generated every 1 ms. This interrupt is used for speed loop control and motor current limitation, executing PI controller functions.
Figure 20. Application timing and interrupts
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4.3.5. Zero crossing detection algorithm
For state variable acquisition and zero-crossing detection processing, the ADC0 conversion sequence complete interrupt is used. The interrupt service routine is executed once the conversion sequence consisting of BEMF voltage, DC bus current and DC bus current conversion is finished. The ADC0 conversion sequence complete interrupt service routine can be found in the SW example in .../src/main.c/ADC0_ConversionCompleteNotif().
Before the ADC0 conversion complete ISR is executed, the ADC0 and ADC1 store the results in the ADC0 and ADC1 results registers; BEMF voltage into ADC1_R0, DC bus current into ADC0_R0, and DC bus voltage into ADC0_R1. These measurements are then saved into the result structure. The value of the current sense amplifier bias voltage offset is subtracted from the measured DC bus current value to obtain the bidirectional DC bus current. A filtering of the DC bus voltage and DC bus current is provided using the moving average filter functions. The BEMF voltage is then calculated as the difference between the phase voltage and the half of the DC bus voltage. The BEMF voltage value is a signed number.
The software checks whether the current decay period has already passed to initiate the zero-crossing detection. (See the details on BEMF-based position detection in chapter 3.3.3.1. of NXP application note AN12435: 3-phase Sensorless BLDC Motor Control Kit with S32K144). The current decay period is called T OFF (variable timeZCToff) in the application implementation:
Example 1. Conditions for zero-crossing detection initiation
void ADC0_ConversionCompleteNotif(const uint8 ControlChanIdx)
{
.
.
.
timeOldBackEmf = timeBackEmf;
timeBackEmf = Ftm_Gpt_Ip_GetCntValue(INST_FTM0);
if(driveStatus.B.AfterCMT == 1)
{
if(timeBackEmf > timeZCToff)
{
driveStatus.B.AfterCMT = 0;
}
}
if((driveStatus.B.AfterCMT == 0) &&
(driveStatus.B.NewZC == )&&
(driveStatus.B.Sensorless == 1))
{
.
.
.
}
Where the commutation transient time T OFF has not yet expired (driveStatus.B.AfterCMT = 1), the zero-crossing calculation will not be performed. The calculation will also not be performed if the zero-crossing point has already been identified in the current commutation period (driveStatus.B.NewZC= 1), or if the application is running in open-loop mode (driveStatus.B.Sensorless = 0).
If the above mentioned conditions are not met, the zero-crossing detection routine will be executed. Based on the current commutation sector, the BEMF slope direction is checked. If the BEMF slope is negative, the sign of the calculated value is changed. This operation allows usage of a single BEMF zero-crossing detection function for a positive slope BEMF in all commutation sectors.
When the zero-crossing position calculation is finished, the BEMF voltage value is stored as the old value as it will be referenced again in the next PWM cycle.
In the case of a negative BEMF voltage (VBEMF < VDCB / 2), the zero-crossing point has not been passed and the zero-crossing is not detectable. The software exits the zero-crossing detecting routine and leaves the zero-crossing status bit unchanged (driveStatus.B.NewZC = 0). In the case of a zero or a positive BEMF voltage (VBEMF ≥ VDCB / 2), the zero-crossing point was reached or passed and Equation 7 is calculated (see AN12435: 3-phase Sensorless BLDC Motor Control Kit with S32K144 for Equation 7 and its description), meaning that the BEMF voltage is divided by the delta of the two measured points and multiplied by the measured PWM period (BEMF measurement period). After this calculation, the old zero-crossing time and the new one are saved into the appropriate variables. The zero-crossing period is then calculated based on the calculated time of zero-crossing and the time of the zero-crossing in the previous commutation cycle. The zero-crossing period is also filtered to improve reliability
At the end of the routine, the new commutation time is calculated. Here, some motor characteristics have to be taken into account. Instead of just adding half of a zero-crossing period to the actual zero-crossing time, a so-called advance angle factor is taken into account, which actually activates the commutation a bit earlier than calculated. This is usually a constant and depends on the motor characteristics.
Finally, the zero-crossing status bit is set (driveStatus.B.NewZC = 1), so the zero-crossing detection does not take place anymore in the current commutation cycle.
For details, see the code in the SW example in ADC0 ISR notification
.../src/main.c/ADC0_ConversionCompleteNotif().
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4.3.6. Speed evaluation, motor current limitation and control
The speed controller is executed in a timer interrupt every 1 ms. The actual speed is calculated from all of the last six zero-crossing periods, and this is stored as the actual speed. The required speed is fed into the ramp function controlling the motor speed slope. The difference between the speed ramp function output and actual speed defines the speed error.
In the closed-loop mode, the actual speed error is fed into the PI controller function. Inputs to the PI controller function include the speed error and the PI controller’s parameters such as the proportional and integral gain constants. The output of the PI controller is the duty cycle, which is scaled to the PWM resolution.
At the end of the speed control function, the duty cycle is loaded into the FTM3 PWM module.
The current limit controller is located in the same 1 ms timer interrupt (.../src/main.c/LpitNotif() ) as the speed controller because the inputs and outputs of both controllers are linked together.
When the actual speed has been calculated, the current limit PI controller can be called by feeding it with the difference between the actual current and the maximum allowed current of the motor. The output of the PI controller is scaled to the number proportional to the PWM period. After the current PI controller has calculated its duty cycle, both duty cycle output values are compared to each other.
If the speed PI controller duty cycle output is higher than the current limit PI controller output, then the speed PI Controller duty cycle output value is limited to the output value of the current limit PI controller. Otherwise, the speed PI duty cycle output will be taken as the duty cycle update value. The value of the duty cycle will be used to update the FTM3 PWM module. At the end, the integral portion values of both the PI controllers need to be synchronized to avoid one of the controllers increasing its internal value as far as the upper limit. If the duty cycle was limited to the current PI duty cycle output, then the integral portion of the current PI controller will be copied into the integral portion of the speed controller, and vice versa.
At the end of .../src/main.c/LpitNotif() PDB0 and PDB1 pre-trigger delays are calculated based on the actual duty cycle to measure DC Bus voltage and BEMF voltage towards the end of the active PWM pulse as discussed in chapter 4.2.4.
4.3.7. AMMCLIB Integration
The integration of AMMCLIB is done in the manner identical to the one described in NXP application note AN12435: 3-phase Sensorless BLDC Motor Control Kit with S32K144.
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5. FreeMASTER and MCAT user interface
The FreeMASTER debugging tool is used to control the application and monitor variables during run time. FreeMASTER and MCAT interface enables online application tuning and control.
MCAT (Motor Control Application Tuning) is a graphical tool dedicated to motor control developers and the operators of modern electrical drives. The main feature of proposed approach is automatic calculation and real-time tuning of selected control structure parameters. Connecting and tuning new electric drive setup becomes easier because the MCAT tool offers a possibility to split the control structure and consequently to control the motor at various levels of cascade control structure.
FreeMASTER and MCAT user interface are described in NXP application note AN12435: 3-phase Sensorless BLDC Motor Control Kit with S32K144.
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6. Conclusion
The design described shows the simplicity and efficiency in using the S32M244 microcontroller for Sensorless BLDC motor control and introduces it as an appropriate candidate for various low-cost applications in the automotive area. MCAT tool provides interactive online tool which makes the BLDC drive application tuning friendly and intuitive.
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7. References
• S32 Design Studio IDE for S32 Platform • Real-Time Drivers (RTD) • FreeMASTER Run-Time Debugging Tool • Automotive Math and Motor Control Library • S32M24x Reference Manual • S32M2xx Data Sheet • S32M24x PMSM/BLDC Motor Control Evaluation Boards • BLDC PMSM low voltage motor control accessory kit • Rashid, M. H. Power Electronics Handbook, 2nd Edition. Academic Press • Motor Control Application Tuning (MCAT) Tool
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