S32M244 - Hall sensor based 6-step BLDC motor control

Yes

Note:

The example was designed on:

C-project based example is a part of S32M24XEVB-SW application SW (the 6-step example has been the part of the application SW from release 1.1).

Application software contains:

S32M24xEVB_BLDC_6Step_Hall - Low-level drivers of RTD and S32 Design Studio Configuration Tools (S32CT) are used to demonstrate a 6-step Hall application.

1. Introduction

This article describes the design of a 3-phase Brushless DC (BLDC) motor control drive using S32M244 NXP integrated solution.

Following are the supported features:

3-phase BLDC speed control based on Six-step commutation control
Shaft position obtained by hall sensors
DC-bus current and DC-bus voltage
Motor speed determined by hall sensors
Application control user interface using FreeMASTER debugging tool
Motor Control Application Tuning (MCAT) tool

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2. System concept

The system is designed to drive a 3-phase BLDC motor. The application meets the following performance specifications:

Targeted at the S32M24xEVB-C064/L064 Evaluation Board (refer to dedicated user manual for S32M24xEVB available at www.nxp.com) See section References for more information.
Control technique incorporating:
- Six-step commutation control of 3-phase brushless DC motor with hall sensors
- Rotor position is obtained by hall sensors
- Closed-loop speed control with action period 1ms
- Bi-directional rotation
- Motor current limitation
- Alignment and start-up
- 50μs current sampling period
Automotive Math and Motor Control Library (AMMCLIB) – Speed control loop built on blocks of precompiled SW library (see section References)
FreeMASTER software control interface (motor start/stop, speed setup)
FreeMASTER software monitor
FreeMASTER embedded Motor Control Application Tuning (MCAT) tool (motor parameters, speed loop)
FreeMASTER software MCAT graphical control page (required speed, actual motor speed, start/stop status, DC-Bus voltage level, DC-Bus current, system status)
FreeMASTER software speed scope (observes actual and desired speeds, DC-Bus voltage and DC-Bus current)
FreeMASTER software high-speed recorder (six-step commutation control quantities)
DC-Bus over-voltage and under-voltage, over-current, overload and start-up fail protection.

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3. Hall sensor-based BLDC control

3.1. Overview of the brushless DC motor

The description of fundamental brushless DC motor principles, overview of electronic commutation control and speed/torque control of BLDC motor can be found in NXP application note AN12435: 3-phase Sensorless BLDC Motor Control Kit with S32K144, chapters 3.1., 3.1.1., 3.1.2.

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3.2. Output voltage actuation and complementary unipolar PWM
modulation technique

The 3-phase voltage source inverter is shown on page 7 of S32M24xEVB schematics, see References. It uses single DC-bus shunt resistor (represented as R134 and R135 in parallel). DC-bus current which flows through the shunt resistor produces a voltage drop which is interfaced to the AD converter of microcontroller through the integrated Digital Programmable Gain Amplifier (DPGA) integrated inside S32M244 . The description of the PWM technique used for BLDC motor control, is available in NXP application note AN12435: 3-phase Sensorless BLDC Motor Control Kit with S32K144, chapter 3.2. The Hall sensors are connected to terminal header J200.

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3.3. Position estimation based on Hall sensor

The position estimation based on Hall sensor is a simple and cost-effective way to control the commutation of BLDC motor. In BLDC motors, there are three Hall sensors mounted around the rotor or stator periphery shifted 120° apart from each other. When the rotor magnet crosses one of the sensor, sensor generates high or low logic signal depending on the magnet polarity. As rotor magnets cross all three sensors, these sensors give out position angle from 0° to 360° every 60°.

To get optimal torque and efficiency conditions in Six-step commutation control, switching sequence of the phases energizing has to produce stator magnetic flux which is 120° - 60° in relation to rotor magnetic flux, Figure 1. The picture depicts the situation when rotor enters first commutation sector “Sector 0”. This moment is indicated by Hall sensor logic “110”. In this sector, phase C is connected to positive polarity of the DC bus voltage, phase B is connected to negative polarity of the DC bus voltage and phase A is unpowered. This phases energizing creates stator magnetic flux which is 120° ahead to rotor magnetic flux. Torque is produced and angle between stator flux and rotor flux decreases from 120° to 60° as rotor moves towards the next commutation sector “Sector 2”. This process is then repeated for each commutation sector.

Figure 1. Speed control with current limitation

The shown Hall sensor states for the particular sectors are applicable to Sunrise motor 42BLY3A78-24110 and may differ for other motor type. The resulting switching statesfor the mentioned motor are as per the following table, where NC denotes the not connected motor phase, LS means low side transistor and HS means high side transistor:

Table 1. Switching table.

Direction	Hall A	Hall B	Hall C	Phase A	Phase B	Phase C
ccw	1	1	0	NC	LS ON	HS PWM
ccw	1	0	0	LS ON	NC	HS PWM
ccw	1	0	1	LS ON	HS PWM	NC
ccw	0	0	1	NC	HS PWM	LS ON
ccw	0	1	1	HS PWM	NC	LS ON
ccw	0	1	0	HS PWM	LS ON	NC
cw	1	1	0	NC	HS PWM	LS on
cw	0	1	0	LS ON	HS PWM	NC
cw	0	1	1	LS ON	NC	HS PWM
cw	0	0	1	NC	LS ON	HS PWM
cw	1	0	1	HS PWM	LS ON	NC
cw	1	0	0	HS PWM	NC	LS ON

Note: The rotation direction is valid for the aforementioned Sunrise motor and may be reversed in case of other motor.

Please note that in case of S32M244 the Flex Timer Module (FTM) is used for PWM control and thus for realization of the switching table. The FTM registers used for execution of the particular switching pattern (table) are double buffered. Meaning they only take effect after a synchronization event. In this SW example, the synchronization event occurs when the state of Hall sensors has changed. Therefore, the algorithm chooses the switching state based on Hall sensors state for "next commutation sector", loads the corresponding settings into FTM registers and they are applied when the Hall state changes to "next commutation sector".

For example: the desired rotation is ccw, the Hall state changes to [110]. Now the algorithm prepares the FTM registers for the switching pattern applicable or the next commutation sector (Hall state [100]) meaning the respective double-buffered registers are set to generate pattern: Phase A - LS ON, Phase B - NC, Phase C - HS PWM, but this pattern is not applied yet, it is only applied after the Hall state changes to "next commutation sector" i.e., when Hall state is [100]. This happens for all Hall states in both directions of rotation.

3.4. States of the BLDC control based on Hall sensors

In order to start and run the BLDC motor, the control algorithm has to go through the following states:

Initialization
Calibration
Alignment (initial position setting)
Run

3.4.1. Initialization

Initialization of variables relevant for motor control.

3.4.2. Calibration

In this state the DC current measurement calibration takes place.

3.4.3. Alignment

Before starting, the motor is aligned to the middle of commutation sector. During the alignment state, all three phases are powered in order to get the best performance behavior in either direction of shaft rotation. Phase C is connected to the positive DC bus voltage and phases A and B are grounded. The alignment time depends on the mechanical constant of the motor, including load, and also on the applied motor current.

3.4.4. Run

The block diagram of the run state is represented by Figure 2 . The motor speed is estimated based on Hall events. The difference between the demanded and estimated speeds is fed into the speed PI controller. The output of the speed PI controller is proportional to the voltage to be applied to the BLDC motor. The motor current is measured and filtered and used as feedback into the current controller. The output of the current PI controller limits the output of the speed PI controller. The limitation of the speed PI controller output protects the motor current from exceeding the maximal allowed motor current.

Figure 2. Speed control with current limitation

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4. Software implementation on S32M244

4.1. S32M244 – Key modules for BLDC 6-step control

The S32M244 is an integrated solution which comprises MCU and Application Extension (AE). The MCU part includes modules such as the FlexTimer Module (FTM), Trigger MUX Control (TRGMUX), Programmable Delay Block (PDB) and Analog-to-Digital Converter (ADC) suitable for control applications, in particular, motor control applications. These modules are directly interconnected and can be configured to meet various motor control application requirements. Figure 3 shows module interconnection for a typical BLDC 6-step application working in Hall sensor-based mode using single shunt current sensing. The modules are described in further chapters and the detailed description can be found in the S32M24x Series Reference Manual (see section References).

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4.1.1. Module interconnection

As mentioned earlier, S32M24x consists of two parts: MCU and AE which are connected together via die-to-die (D2D) connections.

The SPI interface (part of D2D) serves for parameter settings and status monitoring of AE and the rest of D2D interface is used for motor control loop (e.g.: DC bus current reading).

The AE comprises modules vital for motor control such as Gate Driver Unit (GDU) and Digital Programmable Gain Amplifier (DPGA) which allow for using S32M244 in motor control applications with minimum of external components.

The GDU drives the power MOSFETs. The GDU is interconnected with the outputs of FTM via D2D connections.

The shunt resistor voltage drop signal (proportional to DC Bus current) is conditioned by the integrated DPGA which output is connected to the ADC via D2D connection.

DC Bus voltage is conditioned via integrated voltage dividers which outputs are connected to the ADC via D2D connection.

The MCU die modules involved in output actuation, data acquisition and the synchronization of actuation and acquisition, form the so-called Control Loop. This control loop consists of the FTM, TRGMUX, PDB, and ADC modules. The control loop is very flexible in operation and can support static, dynamic or asynchronous timing.

Each control loop cycle can be initiated either by FTM initialization trigger init_trig or by FTM external trigger ext_trig. While init_trig signal is generated at beginning of PWM cycle, ext_trig can be generated any time within the PWM period based on the value defined in the corresponding FTM Channel Value register CnV.

FTM trigger signal is routed to hardware trigger input of the PDB module through flexible TRGMUX unit. In S32M24x, there are two ADC modules and two PDB modules that work in pairs. This means that PDB0 is linked with ADC0 and PDB1 is linked with ADC1. The Hall sensor-based 6-step example only uses ADC0 and PDB0.

PDB pre-triggers ch0pretrigx are used as a precondition for ADC module. They are directly connected to ADHWTS ports to select ADC channels as well as order of the channels by configurable pre-triggers delays. When ADC receives rising edge of the trigger, ADC will start conversion according to the order defined by pre-triggers ch0pretrigx.

PDB pre-trigger delays must be properly set to allow reliable operation between PDB and corresponding ADC module. When the first pre-trigger is asserted, associated lock of the pre-trigger becomes active until corresponding conversion is not completed. This associated lock is released by corresponding ADC conversion complete flag ADC_SC1[COCOx]. This means that next pre-trigger can be generated only if the ongoing conversion is completed.

FTM2 module is used for commutation control. It is configured to schedule and force commutation events which are determined from the states of the Hall sensors.

Detailed description can be found in the S32M24x Series Reference Manual (see section References).

Figure 3. S32M244 modules interconnection.

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4.1.2. Module involvement in digital BLDC control loop

This section will discuss timing and modules synchronization to accomplish BLDC 6-step control on the S32M244 and the internal hardware features.

The timing diagram of the automatic synchronization between PWM and ADC in the BLDC application is shown in Figure 4.

Figure 4. Time Diagram of PWM and ADC Synchronization.

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4.2. S32M244 Device initialization

To simplify and accelerate application development, embedded part of the BLDC 6-step motor control application has been created using S32M244 Real Time Drivers (RTD). S32M244 can be configured either by means of S32 Configuration Tools (CT) - using GUI

or programmed directly using RTD drivers. Peripherals are initialized at beginning of the main() function. For each S32M244 module, there is a specific configuration function that uses S32M244 RTD APIs and configuration structures generated by RTD graphical tools to configure the MCU (as per Table 2).

Detailed RTD documentation can be found in folder created with S32 Design Studio installation (see References).

Table 2. Modules and their configuration functions.

Function	Module
McuClockConfig()	MCU clock configuration
McuCacheConfig()	MCU cache configuration
McuPowerConfig()	MCU power management configuration
McuIntConfig()	MCU interrupt management configuration
McuTrigmuxConfig()	TRGMUX module configuration
McuPinsConfig()	PINs and PORT modules configuration
McuLpuartConfig()	LPUART module configuration
McuAdcConfig()	ADC modules configuration
McuPdbConfig()	PDB modules configuration
McuFtmConfig()	FTM modules configuration
McuSPIConfig()	SPI module configuration
AECConfig()	AE module configuration
AEC_DPGAConfig()	DPGA module configuration
AEC_GDUConfig()	GDU module configuration
AEC_HVMConfig()	HV module configuration

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4.2.1. Clock configuration and power management

S32M244 features a complex clocking sourcing, distribution and power management. To run a core of the S32M244 as well as some MCU peripherals at maximum frequency 80 MHz in normal RUN mode, S32M244 is supplied externally by 16 MHz crystal. This clock source supplies Phase-lock-loop (PLL), which circuit multiplies frequency by 20 and divides by 2 resulting 160 MHz frequency on output. PLL output is then divided by 2 to supply core and system (80 MHz), further divided by two and four to supply bus clock (40 MHz) and flash clock (20 MHz), respectively. This clock configuration belongs to one of the typical and recommended. It is summarized in Table32.

Table 3. S32M244 clock configuration in RUN mode.

Clock	Frequency
CORE_CLOCK	80 MHz
SYS_CLK	80 MHz
BUS_CLK	40 MHz
FLASH_CLK	20 MHz (max frequency in RUN mode)

This clock configuration can be setup by S32 CT Clocks graphical tool, for further details see the SW example, where the detailed clock settings for the particular peripherals can be found.

Once the clock configuration is set, RTD generates static configuration structure Clock_Ip_aClockConfig[0], the respective RTD API is then called in MCUClockConfig which can be found in the SW example in .../src/Peripherals/peripherals_config.c.

As discussed at the beginning of this chapter, power management of the S32M244 is configured for normal RUN mode. This power mode can be set in S32CT Peripherals graphical tool, Figure 5.

Figure 5. S32M244 power management configuration in S32CT Peripherals tool.

Static configuration generated by RTD is called by the respective RTD API and this is encapsulated in MCUPowerConfig function, which can be found in the SW example in .../src/Peripherals/peripherals_config.c

The same mechanism for peripherals configuration by RTD works for all S32M244 peripherals, which are discussed below.

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4.2.2. FlexTimer Module (FTM)

FlexTimer module (FTM) is built upon a timer with a 16-bit counter. It contains an extended set of features that meet the demands of motor control, including the signed up-counter, dead time insertion hardware, fault control inputs, enhanced triggering functionality, and initialization and polarity control.

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4.2.2.1. Center-aligned PWM mode

FTM3 instance is used in BLDC 6-Step motor control application to generate center-aligned PWM by three complementary channels pairs to control power MOSFETs.

The configuration is shown in Figure 6, FTM3 PWM frequency of 20 kHz is adjusted by Counter Period = 4000, taking 80MHz clock source frequency into account. Note that while Center-aligned mode is selected (up-down counter), the value written into FTM3 modulo register is half of Counter Period - this is done internally by the RTD. To protect power MOSFETs against short circuit, deadtime 0.5μs is inserted for each complementary channels pair in number of clock ticks 40 with default deadtime prescaler 1. This FTM3 configuration can be carried out by using S32CT, FTM_Pwm module, Figure 6.
For detailed settings, please see all the settings tabs in Ftm_Pwm module in S32CT Peripherals tool.

Figure 6. S32M244 FTM3 configuration in S32CT.

The double-buffered register FTM3_SWOCTRL is used to control the unipolar PWM pattern as discussed in 3.2. The FTM3_SWOCTRL register controls the PWM output by forcing selected channels into a defined state. The PWM channel which is not SW-controlled is not forced into a SW-defined state but is PWM-controlled. The double-buffered values are applied at each commutation event triggered by FTM2 init_trig . To allow this triggering mechanism, Hardware trigger 0 is enabled in Ftm Synchronization Config tab, Figure 6. The following table shows the SWOCTRL values applied at a commutation event in a particular sector of the six-step commutation sequence.

Table 4. Software control definition in six-step commutation sequence

Sector	FTM3_SWOCTRL	PWM Output settings
0	0x0838	Phase A PWM, Phase B low side on, Phase C low/high OFF
1	0x203C	Phase A PWM, Phase C low side on, Phase B low/high OFF
2	0x2033	Phase B PWM, Phase C low side on, Phase A low/high OFF
3	0x020F	Phase B PWM, Phase A low side on, Phase C low/high OFF
4	0x080F	Phase C PWM, Phase A low side on, Phase B low/high OFF
5	0x0A0F	Phase C PWM, Phase B low side on, Phase A low/high OFF
Alignment¹	0x0A0F	Phase C PWM, Phase A low side on, Phase B low side on
PWM off	0x003F
¹ Alignment vector is set to allow a commutation sequence starting from sector 0

To allow the application of the double-buffered values outside the commutation event, Hardware trigger 1 is enabled in Ftm Synchronization Config tab, Figure 6. This hardware trigger is generated by writing 1 to the SIM_FTMOPT1[FTM3SYNCBIT] bit.

The duty cycle of the center-aligned PWM is controlled by the FTM3_CnV (n = 0, 2, 4) register values. In up-down counting mode, even channels define both, leading as well as trailing edges. Even channels are set according to:

Equation 1.

To initiate control loop at beginning of the PWM period, Initialization trigger is enabled in FTM Instance Configuration tab as well, Figure 6.

Once the FTM3 setting is completed, RTD generates configuration structure Ftm_Pwm_Ip_BOARD_INITPERIPHERALS_UserCfg3 which, using the respective RTD API Ftm_Pwm_Ip_Init configures FTM3, this is encapsulated in function MCUFTMConfig, which can be found in the SW example in .../src/Peripherals/peripherals_config.c.

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4.2.2.2. Commutation for 6-step

In 6-step Hall-based control, the commutation depends on the change of Hall sensor state. The Hall sensors are routed to GPIOs which trigger interrupts on both raising and falling signal edges. In the interrupt service routine for GPIO the Hall signals are processed, new switching combination of the MOSFETs is stipulated based on Hall sensor signals and desired direction of rotation. The time which has elapsed between two Hall signal events is measured by FTM2. After each Hall (commutation event) FTM2 CNT (counter) value is recorded and FTM2 CNT is restarted.
Init trigger signal init_trig is internally routed to the FTM3 module trigger 0 input in order to perform commutation of the PWM pairs.

FTM2 module settings can be configured by S32CT as per Figure 7. In order to make use of RTD APIs, FTM2 is configured as FTM PWM but is used for measurement of time between Hall (commutation) events exclusively, the outputs of FTM2 are disabled. For detailed FTM2 configuration, please see all the configuration tabs as per Figure 7 in SW example.

Once the FTM2 setting is completed, RTD generates configuration structure Ftm_Pwm_Ip_BOARD_INITPERIPHERALS_UserCfg0 which, using the respective RTD API Ftm_Pwm_Ip_Init configures FTM2, this is encapsulated in function MCUFTMConfig, which can be found in the SW example in .../src/Peripherals/peripherals_config.c.

Figure 7. FTM2 configuration.

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4.2.3. Trigger MUX Control (TRGMUX)

The TRGMUX provides an extremely flexible mechanism for connecting various trigger sources to multiple pins/peripherals. With the TRGMUX, each peripheral that accepts external triggers usually has one specific 32-bit trigger control register. Each control register supports up to four triggers, and each trigger can be selected from the available input triggers.

To trigger PDB0 module by FTM3 initialization trigger signal init_trig, TRGMUX needs to be set appropriately.

RTD allows to generate configuration structure Trgmux_Ip_xTrgmuxInitPB that sets all TRGMUX registers to assign trigger inputs with trigger outputs as demanded, Figure 8.

The configuration structure Trgmux_Ip_xTrgmuxInitPB is then used as the argument of Trgmux_Ip_Init() which is encapsulated in .../src/Peripherals/peripherals_config.c

Figure 8. S32M244 TRGMUX configuration in RTD.

In particular, FTM3 initialization trigger signal as a source is assigned to two targets: PDB0 and for debug/visualization purposes to TRGMUX output 2. As mentioned before, FTM2 init trigger output is connected to FTM3 hardware trig 0 input. ADC0 conversion complete flag COCO is assigned to TRGMUX output 5 for debug/visualization.

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4.2.4. Programmable delay block (PDB)

The Programable Delay Block (PDB) is intended to completely avoid CPU involvement in the timed acquisition of state variables during the control cycle. The PDB module contains a 16-bit programmable delay counter that delays FTM3 initialization trigger and schedules ADC channels sampling through PDB pre-triggers delays. When FTM3 initialization trigger is detected on the PDB0 input, PDB0 generates hardware signal to trigger ADC0 channels in order defined by pre-trigger delays, Figure 9.

Figure 9. PDB pre-triggers and trigger output.

PDB pre-trigger delays can be set independently using CHnDLYm registers. Since the PDB0, PDB1 and FTM3 modules are synchronized and share the same source frequency 80MHz, values of the CHnDLYm registers are set using the same time base as for PWM. The following table shows all PDB0 pre-triggers used in BLDC six-step motor control application.

Table 5. PDB0 pre-triggers

State variable	PDB pre-trigger	CHnDLYm value [ticks]	Relation to PWM
DC bus current	pdb0_ch0_pretrig0	0	At beginning of the PWM
DC bus voltage	pdb0_ch0_pretrig1	pdb_delay	In the middle of the PWM

DC bus current measurement is triggered every PWM cycle at beginning of the PWM period by pdb0_ch0_pretrig0. This delay is static value defined only once at the initialization phase. The DC Bus voltage is measured in the middle of the PWM period.

General settings of the PDB module such as clock pre-scaler, input trigger source, loading mechanism for double buffered registers as well as operation mode for pre-triggers can be configured by means of S32CT as shown in Figure 10, for details, see the PDB configuration in the SW example.

Figure 10. S32M244 PDB module and pre-triggers configuration.

RTD generates configuration structure PdbHwUnit_0_BOARD_INITPERIPHERALS for appropriate PDB registers. This configuration is loaded calling .../src/Peripherals/peripherals_config.c/McuPdbConfig().

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4.2.5. Analog-to-digital converter (ADC)

The S32M244 device has two 12-bit Analog-to-Digital Converters (ADCs). These are 32-channel multiplexed input successive approximation ADCs with 16 result registers.

The ADC0 instance is used in the SW example and is triggered by PDB0. ADC channels are sampled in the order defined by PDB pre-triggers. When the first pre-trigger is asserted, associated lock of the pre-trigger becomes active waiting for the conversion complete flag COCO generated by the corresponding ADC channel. This sequence is repeated for each PDB pre-trigger and ADC channel couple.

The configuration in S32CT is shown in Figure 11, see the SW example for details.

Figure 11. S32M244 ADC0 module configuration.

ADC0 channel 0 measures DC bus current, ADC0 channel 1 measures DC Bus voltage.

RTD generates module configuration structure AdcHwUnit_0_BOARD_INITPERIPHERALS, which takes effect calling the respective RTD API in function .../src/Peripherals/peripherals_config/McuAdcConfig().

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4.2.6. Low Power Serial Peripheral Interface (LPSPI)

LPSPI is used as communication interface between S3M244 MCU and AE. Configuration of LPSPI1 by means of S32CT can be seen in Figure 12.

Figure 12. S32M244 LPSPI module configuration.

LPSPI is then initialized using the RTD-generated configuration structure in .../src/Peripherals/peripherals_config/McuSPIConfig().

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4.2.7. Low Power Universal Asynchronous Receiver/Transmitter (LPUART)

LPUART1 is used as a communication interface between S32M244 processor and FreeMASTER run-time debugging and visualization tool. Function .../src/Peripherals/peripherals_config/McuLpuartConfig() initializes LPUART0 module with baud rate 115200, 1 stop bit and 8 bits per channel. This configuration is carried out by RTD’s LPUART driver.

Configuration structure Lpuart_Uart_Ip_xHwConfigPB_0_BOARD_INITPERIPHERALS is configured by means of S32CT as shown in Figure 13.

Figure 13. S32M244 LPUART module configuration.

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4.2.8. Port control and pin multiplexing

BLDC 6-step motor control application requires following on chip pins assignment:

Table 6. Pins assignment for S32M244 BLDC 6-step Hall sensor-based control.

Peripheral	Signal	Pin	Description
ADC0	DCBI	PTB13 / ADC0_SE8	DC Bus current
ADC0	DCBV	PTA6 / ADC0_SE2	DC Bus voltage
GPIO	HALL_A	PTE4	Hall sensor Phase A
	HALL_B	PTE5	Hall sensor Phase B
	HALL_C	PTD0	Hall sensor Phase C
FTM3	PWMA_HS	PTA2 / FTM3_CH0	PWM A high-side driver
	PWMA_LS	PTA3 / FTM3_CH1	PWM A low-side driver
	PWMB_HS	PTB10 / FTM3_CH2	PWM B high-side driver
	PWMB_LS	PTB11 / FTM3_CH3	PWM B low-side driver
	PWMC_HS	PTC10 / FTM3_CH4	PWM C high-side driver
	PWMC_LS	PTC11 / FTM3_CH5	PWM C low-side driver
LPSPI1	SPI_SCLK	PTB14 / LPSPI1_SCK	SPI clock
	SPI_SIN	PTB15 / LPSPI1_SIN	SPI data in
	SPI_SOUT	PTB16 / LPSPI1_SOUT	SPI data out
	SPI_CS	PTB17 / LPSPI1_PCS3	SPI chip select
GPIO	AE_Fault	PTD3	Application Extension fault (active low)
LPUART0	LPUART_In	PTC2 / lpuart_rx	Receive data from FreeMASTER
LPUART0	LPUART_Out	PTC3 / lpuart_tx	Send data to FreeMASTER
TRGMUX	TRGMUX_InitTrg	PTD1 / trgmux_out2	FTM3 Init trigger visualization
TRGMUX	TRGMUX_CoCo	PTE11 / trgmux_out5	ADC0 CH1 conversion complete visualization
GPIO	Exec_Meas	PTE15	Toggled pin for execution time measurement
	SW0	PTB4	Application control via board button
	SW1	PTB5	Application control via board button
	LED	PTE15	LED indication: steady lit - ready, slow flashing - run fast flashing - fault

This pins assignment can be carried out by means of RTD, Pins tool. Pin assignment of the FTM3 module is shown in Figure 14 as an example.

Figure 14. S32M244 Pins assignment for FTM3 in S32CT.

The RTD-generated configuration structure g_pin_mux_InitConfigArr_BOARD_InitPins and the respective RTD function is then called in ...src/Peripherals/peripherals_config.c/MCUPinsConfig().

Note: At the time of this article publication, ADC0 interleave on pin PTB13 was not available in the S32CT Pins tool, therefore the interleave is set in ...src/Peripherals/peripherals_config.c/MCUPinsConfig() by calling Port_Ci_Port_Ip_SetMuxModeSel(IP_PORTB, 13, PORT_MUX_ADC_INTERLEAVE)

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4.2.9. Interrupt configuration

The configuration of the respective interrupts takes place in RTD Peripherals tool. The interrupts are configured as per the following table:.

Table 7. Interrupts in S32M244 BLDC 6-step Hall sensor-based example.

Name	Priority	Description
ADC0_IRQn	2	State variables acquisition
PORT_CI_ICU_IP_D_EXT_IRQ_ISR PORT_CI_ICU_IP_E_EXT_IRQ_ISR	1	Interrupt from Hall sensor status change
PDB0_IRQn	0	PDB0 Sequence Error
PORTD_IRQn	1	AE fault detection
LPIT0_Ch0_IRQn	0	Control loop calculation

The configuration of the interrupts in S32CT peripherals tool is shown in Figure 15, see SW example for details.

Figure 15. S32M244 interrupt configuration in RTD.

The interrupt from AE fault is carried out by detection of falling edge on PTD3, this needs to be set in RTD peripherals tool as well, a part of the setting is shown in Figure 16. See the detailed setting in RTD peripherals tool for the module Port_Ci_Icu. The same applies for Hall sensor signals, pins PTE4, PTE5 and PTD0.

The S32CT -generated configuration structure IntCtrlConfig_0 and the structures for PTD3, PTE4, PTE5 and PTD0 interrupt:
Port_Ci_Icu_Ip_3_Config_PB_BOARD_INITPERIPHERALS,
Port_Ci_Icu_Ip_4_Config_PB_BOARD_INITPERIPHERALS
and the respective RTD function is then called in src/peripherals/peripherals_config.c/MCUIntConfig().

Figure 16. S32M244 enabling PTD3 falling edge detection.

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4.2.10. Low Power Interrupt Timer (LPIT) configuration

The LPIT channel 0 is employed to control the speed and motor current in a software task. LPIT channel 0 is configured to generate a periodic interrupt every 1 ms. The configuration by means of S32CT is as follows:

Figure 17. S32M244 LPIT configuration.

The S32CT-generated configuration structure LPIT_0_InitConfig_PB_BOARD_INITPERIPHERALS and the respective RTD function is then called in src/peripherals/peripherals_config.c/MCULpitConfig().

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4.2.11. Application Extension (AE) configuration

Configuration of AE is described in NXP application note AN14454: 3-phase Sensorless PMSM Motor Control with S32M244. Identical AE configuration is used also for this SW example.

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4.3. Software architecture

Figure 18 presents the conceptual system block diagram of the BLDC Six-step control technique working in Hall sensor-based mode.

The application is optimized for S32M244 motor control peripherals to achieve the least possible core involvement in state variable acquisition and output action application. The motor control peripherals (FTM2, FTM3, PDB0, ADC0) are internally linked together to work independently from the core, and to achieve deterministic sampling of analog quantities and precise commutation of the stator field. The software part of the application consists of different blocks which are described below. The entire application behavior is controlled from a PC through the FreeMASTER run-time debugging tool.

The inputs of the control loop are the measured voltages and current on the power stage, in particular the phase/BEMF voltages, the DC bus current, and DC bus voltage.

From a control perspective, the block diagram can be divided into two logical parts:

Commutation control, where the signals from Hall sensors are used to determine the actual position of the shaft. According to the identified position, the next commutation event can be prepared.
Speed/torque control, where the required shaft velocity is compared to the actual measured speed and regulated by the PI controller. The output of the speed PI controller is the duty cycle. The duty cycle is limited by the current PI controller and assigned to the PWM.

Figure 18. System block diagram.

4.3.1. Introduction

This section describes the software design of the Hall sensor-based BLDC Six Step Control framework application. The application overview and description of software implementation are provided. The aim of this chapter is to help in understanding of the designed software.

4.3.2. Application data flow overview

The application software has two main states: the alignment state and the run state. In the run state, the BLDC motor is fully controlled in a closed-loop mode. After the initialization of the peripheral modules has completed, the software enters the alignment state. In alignment state, the rotor position is stabilized into a known position in order to create the same start-up torque in both directions of rotation. This is achieved by applying a PWM signal to phase C. Phases A and B are assigned with a duty cycle equal to zero; that is, they are connected to the negative pole of the DC bus. The value of the duty cycle on phase C depends on the motor inertia and load applied on the shaft. Such a technique aligns the shaft into position between phase A and B, which is perpendicular to both start-up flux vectors generated by the stator winding, and therefore ensures the same start-up torque in both directions of rotation. The duration of the alignment state depends on the motor’s electrical and mechanical constants, the applied current (meaning duty cycle), and the mechanical load.

When the alignment time-out expires, the application software moves to start state, which in case of Hall-based example is only a one-pass state (on the contrary to sensorless application where open loop startup takes place.

Then the state changes to the run state, where the commutation process based on the Hall sensor signals takes place, and the control enters the closed-loop mode.

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4.3.3. State Machine

The application state machine is implemented using a one-dimensional array of pointers to state functions, called AppStateMachine[]. The index of the array specifies the pointer to the related application state function. The application state machine consists of the following seven states selected using the index variable appState value.

Possible state transitions are shown in Figure 19.

The application states are listed in the following table:

Table 8. Application states

AppState	Application state	Description
0	INIT	The INIT state provides the initial configuration of the PWM duty cycle and initialization of DC bus current offset calibration. The state machine then transitions to the STOP state.
1	CALIB	The CALIB state provides the DC bus current calibration. The state machine then transitions to ALIGNMENT state.
2	ALIGNMENT	In the ALIGNMENT state, the alignment vector is applied to the stator to set the rotor to the defined position. The duration of the alignment state and the duty cycle applied during the state are defined by the ALIGN_DURATION and ALIGN_VOLTAGE macro values accessible in the BLDC appconfig.h header file. The state machine then transitions to the START state.
3	START	Only a one-pass state in Hall-based application
4	RUN	In the RUN state, the BLDC motor is controlled in the closed-loop . Speed control and current limitation are performed as described in 4.3.5, “Speed evaluation, motor current limitation and control”. The transition to the INIT state is done by setting the appSwitchState variable to 0.
5	STOP	In the STOP state, the motor is stopped and prepared to start running. Transition to the ALIGNMENT state is performed once the appSwitchState variable is set to 1 and the freewheeling counter expires.
6	FAULT	The fault detection function is executed in the main endless loop, detecting DC bus undervoltage, DC bus overvoltage, DC bus overcurrent, and AE faults. Once any of the faults are detected, the state machine automatically transitions to the FAULT state. The PWM outputs are set to the safe state. To exit the FAULT state, all fault sources must be removed and the faultSwitchClear variable has to be set to 1 to clear the fault latch. The state machine then automatically transitions to the INIT state.

Figure 19. Application state machine

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4.3.4. Application timing and interrupts

Figure 20 shows the application timing and the associated interrupts used for the commutation, Hall sensor processing and speed control. The grey boxes show the executed interrupt routines versus the phase voltage measurement.

The top row shows the interrupt that is activated when the ADC conversion sequence of DC bus current, and DC bus voltage has been completed.
The second row shows the GPIO interrupt caused by Hall sensors state change generated at the time of the commutation event. The time between each GPIO interrupt is measured by FTM2 counter.

The last row shows the LPIT channel 0 time-out interrupt generated every 1 ms. This interrupt is used for speed loop control and motor current limitation, executing PI controller functions.

Figure 20. Application timing and interrupts

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4.3.5. Speed evaluation, motor current limitation and control

The speed controller is executed in a timer interrupt every 1 ms. The actual speed is calculated from all of the last six commutation periods, and this is stored as the actual speed. The required speed is fed into the ramp function controlling the motor speed slope. The difference between the speed ramp function output and actual speed defines the speed error.

In the closed-loop mode, the actual speed error is fed into the PI controller function. Inputs to the PI controller function include the speed error and the PI controller’s parameters such as the proportional and integral gain constants. The output of the PI controller is the duty cycle, which is scaled to the PWM resolution.

At the end of the speed control function, the duty cycle is loaded into the FTM3 PWM module.

The current limit controller is located in the same 1 ms timer interrupt (.../src/main.c/LpitNotif() ) as the speed controller because the inputs and outputs of both controllers are linked together.

When the actual speed has been calculated, the current limit PI controller can be called by feeding it with the difference between the actual current and the maximum allowed current of the motor. The output of the PI controller is scaled to the number proportional to the PWM period. After the current PI controller has calculated its duty cycle, both duty cycle output values are compared to each other.

If the speed PI controller duty cycle output is higher than the current limit PI controller output, then the speed PI Controller duty cycle output value is limited to the output value of the current limit PI controller. Otherwise, the speed PI duty cycle output will be taken as the duty cycle update value. The value of the duty cycle will be used to update the FTM3 PWM module. At the end, the integral portion values of both the PI controllers need to be synchronized to avoid one of the controllers increasing its internal value as far as the upper limit. If the duty cycle was limited to the current PI duty cycle output, then the integral portion of the current PI controller will be copied into the integral portion of the speed controller, and vice versa.

4.3.6. AMMCLIB Integration

The integration of AMMCLIB is done in the manner identical to the one described in NXP application note AN12435: 3-phase Sensorless BLDC Motor Control Kit with S32K144.

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5. FreeMASTER and MCAT user interface

The FreeMASTER debugging tool is used to control the application and monitor variables during run time.
FreeMASTER and MCAT interface enables online application tuning and control.

MCAT (Motor Control Application Tuning) is a graphical tool dedicated to motor control developers and the operators of modern electrical drives. The main feature of proposed approach is automatic calculation and real-time tuning of selected control structure parameters. Connecting and tuning new electric drive setup becomes easier because the MCAT tool offers a possibility to split the control structure and consequently to control the motor at various levels of cascade control structure.

FreeMASTER and MCAT user interface are described in NXP application note AN12435: 3-phase Sensorless BLDC Motor Control Kit with S32K144.

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6. Conclusion

The design described shows the simplicity and efficiency in using the S32K144 microcontroller for Hallsensor-based BLDC motor control and introduces it as an appropriate candidate for various low-cost applications in the automotive area. MCAT tool provides interactive online tool which makes the BLDC drive application tuning friendly and intuitive.

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7. References

• S32 Design Studio IDE for S32 Platform
• Real-Time Drivers (RTD)
• FreeMASTER Run-Time Debugging Tool
• Automotive Math and Motor Control Library
• S32M24x Reference Manual
• S32M2xx Data Sheet
• S32M24x PMSM/BLDC Motor Control Evaluation Boards
• BLDC PMSM low voltage motor control accessory kit
• Rashid, M. H. Power Electronics Handbook, 2nd Edition. Academic Press
• Motor Control Application Tuning (MCAT) Tool

S32M244 - Hall sensor based 6-step BLDC motor control

S32M244 - Hall sensor based 6-step BLDC motor control