Example Description
This application demonstrates the usage FlexTimer Module in Complementary mode and dead-time insertion. The application includes S32 Design Studio projects for both devices, that uses configurations for for the IP layer only (Clocks, Port_Ip_1 and Ftm_Pwm).
For more details please refer to FlexTimer Module (FTM) Usage on S32M24x and S32K14x Series.
Installation steps
Software installation
S32 Design Studio for S32 Platform v.3.5
RTD for S32K1 and S32M24x version 2.0.0 including patch P01
Hardware installation
Supported boards:
- S32M24xEVB-C064
- S32K144EVK
Connections to the scope in S32M24xEVB-C064/S32K144EVK:
- ftm0_ch0 -> PTD15 (J21-2/J2-2)
- ftm0_ch1 -> PTD16 (J21-1/J2-4)
- ftm0_ch2 -> PTD0 (J60-2/J2-6)
- ftm0_ch3 -> PTD1 (J60-3/J6-2)
Debugger in S32M24xEVB-C064/S32K144EVK
- Use the On-board Debug Interface in J32/J7 Open SDA connector.
S32 Configurations Tool
Clocks Tool
S32M244 and S32K144 features a complex clocking sourcing, distribution. To run a core of the S32M244/S32K144 as well as some MCU peripherals at maximum frequency 80 MHz in normal RUN mode, S32M244 is supplied externally by 16 MHz crystal (meanwhile S32K144 is supplied externally by 8 MHz crystal). This clock source supplies Phase-lock-loop (PLL), which circuit multiplies frequency by 20 in S32M244 (and by 40 in S32K144) and divides by 2 resulting 160 MHz frequency on output for both devices. PLL output is then divided by 2 to supply core and system (80 MHz), further divided by 2 and 4 to supply bus clock (40 MHz) and flash clock (20 MHz), respectively (See next Figure).
Figure 1. S32M244 Clocks Configuration
Pins Tool
In Pins Tool are selected the signals to use the FTM0 module as follows:
Figure 2. S32M244 Pins Configuration
Peripherals Tool
Below is the FTM0 configuration (the default configuration of the tabs that are not shown is used):
Figure 3: FTM Hardware instance
Figure 4: FTM Clock Configuration
Figure 5: FTM Global Channel Configuration
Figure 6: FTM PwmFtmCh (for Ch0 and Ch1)
Figure 7: FTM PwmFtmCh (for Ch2 and Ch3)
Software implementation
The application software functionality perform the following instructions (see Example 1):
- Initialize Clock driver.
- Initialize Port driver
- Initialize PWM driver
- Update period for FTM0
- Update duty cycle to PWM signals
Example 1. S32M244 FTM0 configured by S32 SDK
int main(void)
{
/* Init clock */
Clock_Ip_Init(&Clock_Ip_aClockConfig[0]);
/* Initialize all pins using the Port driver */
Port_Ci_Port_Ip_Init(NUM_OF_CONFIGURED_PINS_BOARD_InitPins, g_pin_mux_InitConfigArr_BOARD_InitPins);
/* Initialize PWM driver */
Ftm_Pwm_Ip_Init(FTM_INSTANCE_0, &Ftm_Pwm_Ip_UserCfg0);
/* Set new period for PWM Signals*/
Ftm_Pwm_Ip_UpdatePwmPeriod(FTM_INSTANCE_0, 0x5000, TRUE);
/* Setup new duty cycle to PWM signals */
Ftm_Pwm_Ip_UpdatePwmChannel(FTM_INSTANCE_0, FTM_CH_0, 0x4000, 0x000, TRUE);
Ftm_Pwm_Ip_UpdatePwmChannel(FTM_INSTANCE_0, FTM_CH_2, 0x2000, 0x000, TRUE);
…
}
On the oscilloscope
Figure 8 shows that the ftm0_ch0 (D0), ftm0_ch1 (D1), ftm0_ch2 (D2) and ftm0_ch3 (D3) signals on the oscilloscope. Such signals have the same period aligned in the center and with dead-time insertion. ftm0_ch1 is the complementary of ftm0_ch0 with inverted output. And ftm0_ch3 is the complementary of ftm0_ch2 with duplicated output.
Figure 8: Complementary mode and dead-time insertion
