Abstract
This document outlines the use of the eMIOS module on S32M27x and S32K3 series, detailing various operation modes and their implementations based on the RTD low level API to support diverse application needs.
Contents
1. Introduction
2. eMIOS components of RTD 6.0.0 (LLD)
3. Microcontroller Library (MCL) driver
4. General Purpose Timer (GPT) driver
4.1. GPT Example Project
5. Output Compare Unit (OCU) driver
5.1. SAOC Example Project
6. Pulse Width Modulation (PWM) driver
6.1. OPWMB example project:
6.2. DAOC example project
6.3. OPWMT example project
6.4. OPWMCB example project
6.5. OPWFMB example project
6.6. PWM design considerations
7. Input Capture Unit (ICU) driver
7.1. IPWM example project
7.2. IPM example project
7.3. SAIC example project – Edge Counter
7.4. SAIC example project – Signal Edge Detect
7.5. ICU design considerations
8. Conclusion
9. References
10. Appendix
10.1. Application Software Content
1. Introduction
This document provides an overview of the Enhanced Modular IO Subsystem (eMIOS) module for the S32M27x and S32K3 series. It describes the supported operation modes and their implementations using the RTD 6.0.0 low-level API, designed to meet a wide range of application requirements.
The supported features include:
- General-purpose timing in continuous and one-shot modes, with interrupt support.
- Output generation on counter bus match using SAOC mode.
- PWM signal generation in OPWMB, DAOC, OPWMT, OPWMCB, and OPWFMB modes, with support for:
- Interrupts
- Triggering
- Single PWM pulse
- Output state control
- Frequency modulation
- Synchronization
- Edge-alignment
- Center-alignment
- Dead-time insertion
- Complementary output
- Phase shift
- Lower PWM frequencies
- Input capture functionalities in IPWM, IPM and SAIC modes, supporting:
- Duty cycle and period measurement
- Edge counting
- Edge detection
- Interrupts
- Overflow notifications
2. eMIOS components of RTD 6.0.0 (LLD)
S32 Configuration Tools (Peripherals) provide five RTD eMIOS drivers to implement diverse configurations for timer functionality, generation of timed outputs, time measurement of input signals and increment its counter as input edges are detected:
- Emios_Mcl_Ip -> eMIOS Microcontroller Library
- Emios_Gpt -> eMIOS General Purpose Timer
- Emios_Ocu -> eMIOS Output Compare Unit
- Emios_Pwm -> eMIOS Pulse Width Modulation
- Emios_Icu -> eMIOS Input Capture Unit
To use them, please take into account the following considerations:
Emios_Mcl_Ip must be added in your project to use the other four drivers.
General process for eMIOS initialization:
- Initialize instance (MCL) → Initialize channel (GPT, OCU, PWM, ICU) → Other (start, notification, etc.)
To access the User Manual for each driver, click on the button in the upper right corner, for example:
Figure 1. Access the User Manuals
3. Microcontroller Library (MCL) driver
The MCL driver allows you to configure the module's global prescaler and, if needed, multiple master buses. A master bus is a channel operating in Modulus Counter (MC) or Modulus Counter Buffered (MCB) mode (either up or up/down counting) and includes its own internal channel prescaler. This driver is always used in conjunction with the other four drivers.
For more information, please refer to the following sections (GPT, OCU, PWM, ICU).
4. General Purpose Timer (GPT) driver
GPT driver allows to implement timer functionality using channels types X and G, which have internal counters.
It can operate in either continuous or one-shot mode after the time-out has expired.
Main API functions are: start, stop, change next time-out and generate an interrupt notification when time-out is reached.
Time-out is defined by the compare value in clock cycles (or “ticks”), which is calculated as follows:
CompareValueTICKS = (fINPUT × CVDESIRED) / (GPRE × CPRE)
Where:
fINPUT = eMIOS clock frequency (Hz)
GPRE = Global prescaler
CPRE = Channel prescaler
CVDESIRED = Desired compare value (s)
For example:
fINPUT = 120 MHz
GPRE = 200
CPRE = 1
CVDESIRED = 50 ms
CompareValueTICKS = (120,000,000 × 0.05) / (200 × 1) = 30,000 ticks
Note: Consider the width of the 16-bit eMIOS timer, which allows a maximum count of 65,534 ticks (for S32K388/S32K389: 24-bits).
Connections:
S32M27XEVB-C064 / S32K31XEVB-Q100 -> Pin -> Signal -> Label
J60-1 / J40-12 -> PTE16 -> siul2_gpio_144 -> GPIO1
J60-4 / J38-3 -> PTD0 -> siul2_gpio_96 -> GPIO2
Note:
For S32M27XEVB-C064, consider remove following resistors: R208 and R181.
Clocking:
EMIOSx_CLK = CORE CLK -> 120MHz
4.1. GPT Example Project
This example shows how to use GPI functionality with two channels initialized in the following way:
- eMIOS_1_ch0 in continuous mode with compare value of 60,000 ticks (100ms) – toggles GPIO1.
- eMIOS_0_ch0 in one-shot mode with compare value of 60,000 ticks (100ms) – toggles GPIO2.
Both channel interrupts are enable and each one toggles one GPIO (GPIO1 and GPIO2).
Then it is counted when Emios1_Ch0_Notification() function is called. When g_gptCount = 4, it change the compare value to 30,000 ticks. And when g_gptCount = 8, stop the counter. See Figure 2.
Note: Both eMIOS channel are not synchronized.
Application Software:
S32M276_RTD600_eMIOS_GPT_Ip_example
S32K311_RTD600_eMIOS_GPT_Ip_example
Figure 2. Signals of GPT Example Project
5. Output Compare Unit (OCU) driver
OCU driver can implement Single Action Output Capture (SAOC) mode. It is used to run a counter until a predefined value is reached. When a compare-match (also called threshold) occurs, a hardware interrupt and/or a state change of an output pin will be triggered. It can use any channel types (X, Y, G and H).
Threshold can be calculated in the similar way than compare value of GPT.
Connections:
S32M27XEVB-C064 / S32K31XEVB-Q100 -> Pin -> Signal -> Label
J60-1 / J40-12 -> PTE16 -> siul2_gpio_144 -> GPIO1
J21-1 / J38-6 -> PTD16 -> emios_0_ch_1_g -> OCU1
Note:
For S32M27XEVB-C064, consider remove following resistors: R208 and R169.
Clocking:
EMIOSx_CLK = CORE CLK -> 120MHz
5.1. SAOC Example Project
This example shows how to use SAOC mode with one channel initialized in the following way:
- MCL: eMIOS_0
- Clock Divider Value (global prescaler): 200
- MCL: eMIOS_0_ch_23 (Global bus A)
- Master bus prescaler (UC internal prescaler): 1
- Default period: 60,000 ticks
- Master Bus Mode Type: MCB_UP_COUNTER
- PWM: eMIOS_0_ch_1
- Emios Bus Select: EMIOS_OCU_BUS_A
- Default Threshold: 60,000 ticks
- Max Counter Value: 60,000 ticks
- Notification: Enable
- Output Pin Default State: OCU_HIGH
- Output Pin Action: OCU_TOGGLE
Then it is counted when Emios0_Ch1_Notification() function is called. When g_ocuCount >= 4, it change the threshold to 30,000 ticks. And when g_ocuCount = 8, stop the channel. Additionally, GPIO1 is toggled in the same notification function. See Figure 3.
Application Software:
S32M276_RTD600_eMIOS_SAOC_Ip_example
S32K311_RTD600_eMIOS_SAOC_Ip_example
Figure 3. Signals of SAOC Example Project
5. Pulse Width Modulation (PWM) driver
The PWM driver can implement the following modes:
- Output Pulse Width Modulation Buffered (OPWMB)
- Double Action Output Compare (DAOC)
- Output Pulse Width Modulation Trigger (OPWMT)
- Center-Aligned Output PWM Buffered with Dead Time (OPWMCB)
- Output Pulse Width and Frequency Modulation Buffered (OPWFMB)
The following sections detail the implementation of each mode and highlight their key characteristics.
Period in clock cycles (or “ticks”) is calculated as follows:
PeriodTICKS = fINPUT / (GPRE × CPRE × fDESIRED)
Where:
fINPUT = eMIOS clock frequency (Hz)
GPRE = Global prescaler
CPRE = Channel prescaler
fDESIRED = Desired signal frequency (Hz)
Duty cycle in clock cycles (or “ticks”) is calculated as follows:
DutyCycleTICKS = (DutyCycle% × PeriodTICKS ) / 100 %
One tick in seconds is calculated as follows:
1 tick = fINPUT / (GPRE × CPRE)
For example:
fINPUT = 120 MHz
GPRE = 200
CPRE = 1
fDESIRED = 2 kHz
DutyCycle% = 50 %
PeriodTICKS= 120,000,000 / (1 × 1 × 2,000) = 60,000 ticks
DutyCycleTICKS = (50 × 60,000) / 100 = 30,000 ticks
1 tick = 120,000,000 / (1 × 1) = 8.33 ns
Note: Consider the width of the 16-bit eMIOS timer, which allows a maximum of 65,534 ticks (for S32K388/S32K389: 24-bits).
Connections:
S32M27XEVB-C064 / S32K31XEVB-Q100 -> Pin -> Signal -> Label
J60-1 / J40-12 -> PTE16 -> siul2_gpio_144 -> GPIO1
J21-1 / J38-6 -> PTD16 -> emios_0_ch_1_g -> PWM1
J21-3 / J39-1 -> PTB5 -> emios_0_ch_5_g -> PWM2
J60-4 / J38-3 -> PTD0 -> siul2_gpio_96/ emios_0_ch_2_g -> GPIO2/PWM3*
*PWM3 is used in OPWMCB example project, for the rest GPIO2 is used.
Note:
For S32M27XEVB-C064, consider remove following resistors: R208, R169, R208 and R181.
Clocking:
EMIOSx_CLK -> 120MHz
6.1 OPWMB example project
OPWMB generates a simple output PWM signal, using any channel types (X, Y, G and H).
This example implements one channel as GPI (for time reference in scope) and two channels in OPWMB mode initialized as follows:
- MCL: eMIOS_1
- Clock Divider Value (global prescaler): 200
- MCL: eMIOS_0
- Clock Divider Value (global prescaler): 1
- MCL: eMIOS_0_ch_23 (Global bus A)
- Master bus prescaler (UC internal prescaler): 1
- Default period: 60,000 ticks
- Master Bus Mode Type: MCB_UP_COUNTER
- PWM exclusive access: Enable
- GPT: eMIOS_1_ch_0
- GptEmiosPrescaler (UC internal prescaler): 1
- Emios Notification: Enable
- Emios Channel Mode: EMIOS_GPT_IP_CH_MODE_CONTINUOUS
- Compare Value: 750 ticks
- PWM: eMIOS_0_ch_1
- Counter Bus EMIOS_PWM_IP_BUS_A
- Flag generation: Trailing_Edge
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 60,000 ticks
- Duty cycle: 30,000 ticks
- Phase shift: 0 ticks
- Flag Event response: EMIOS_PWM_IP_INTERRUPT_REQUEST
- PWM: eMIOS_0_ch_5
- Counter Bus EMIOS_PWM_IP_BUS_A
- Flag generation: Trailing_Edge
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 60,000 ticks
- Duty cycle: 30,000 ticks
- Phase shift: 7,500 ticks
- Flag Event response: EMIOS_PWM_IP_NOTIFICATION_DISABLED
Clock Divider Value from MCL eMIOS_1, along with Compare Value from GPT eMIOS_1_ch_0 generates a time-out period. Once time-out is reached its Emios Notification toggles GPIO1. This allows us to observe in scope 3 events (see Figure 4) that will be described later.
The eMIOS_0_ch_23 channel is configured as global counter bus A. In this setup, it can act as the time base for other eMIOS_0 channels—specifically PWM1 and PWM2 in this case—enabling synchronization between them. This synchronization ensures that both channels share the same time base, thereby defining a common period for their operation.
Despite both channels being synchronized, phase shift feature is possible in this mode. Note PWM2 is phase shifted with respect to global counter bus A, and therefore with respect to PWM1.
An interrupt is requested on every flag event, during which GPIO2 is toggled. In this configuration, the flag is generated on the trailing edge—interpreted here as the falling edge, considering HIGH polarity. Alternatively, it can be configured to trigger on both the trailing and leading edges, allowing interrupts on both transitions.
The three events shown in Figure 4 are described as follows:
- Initialization of eMIOS_0 counter.
- Set new period for global counter bus A (which means frequency modulation). Set new duty cycle to PWM1 and PWM2. As well as set new phase shift value to PWM2.
- Set the state of output pin to LOW, deinitialization of both PWM channels and stop the GPT counter.
Application Software:
S32M276_RTD600_eMIOS_OPWMB_Ip_example
S32K311_RTD600_eMIOS_OPWMB_Ip_example
Figure 4. Signals of OPWMB Example Project
6.2. DAOC example project
DAOC generates a single PWM pulse, it can be implemented using channel types G and H.
This example implements one channel as GPI (for time reference in scope) and two channels in PWM mode—one in DAOC mode (PWM1) and the other in OPWMB mode (PWM2)—initialized as follows:
- MCL: eMIOS_1
- Clock Divider Value (global prescaler): 200
- MCL: eMIOS_0
- Clock Divider Value (global prescaler): 1
- MCL: eMIOS_0_ch_23 (Global bus A)
- Master bus prescaler (UC internal prescaler): 1
- Default period: 60,000 ticks
- Master Bus Mode Type: MCB_UP_COUNTER
- PWM exclusive access: Enable
- GPT: eMIOS_1_ch_0
- GptEmiosPrescaler (UC internal prescaler): 1
- Emios Notification: Enable
- Emios Channel Mode: EMIOS_GPT_IP_CH_MODE_CONTINUOUS
- Compare Value: 750 ticks
- PWM: eMIOS_0_ch_1
- Counter Bus EMIOS_PWM_IP_BUS_A
- Flag generation: Trailing_Edge
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 60,000 ticks
- Duty cycle: 30,000 ticks
- Flag Event response: EMIOS_PWM_IP_INTERRUPT_REQUEST
- PWM: eMIOS_0_ch_5
- Counter Bus EMIOS_PWM_IP_BUS_A
- Flag generation: Trailing_Edge
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 60,000 ticks
- Duty cycle: 30,000 ticks
- Flag Event response: EMIOS_PWM_IP_NOTIFICATION_DISABLED
Clock Divider Value from MCL eMIOS_1, along with Compare Value from GPT eMIOS_1_ch_0 generates a time-out period. Once time-out is reached its Emios Notification toggles GPIO1. This allows us to observe in scope 3 events (see Figure 5) that will be described later.
The eMIOS_0_ch_23 channel is configured as global counter bus A. In this setup, it can act as the time base for other eMIOS_0 channels—specifically PWM1 and PWM2 in this case—enabling synchronization between them. This synchronization ensures that both channels share the same time base, thereby defining a common period for their operation.
An interrupt is requested on every flag event, during which GPIO2 is toggled. In this configuration, the flag is generated on the trailing edge.
The three events shown in Figure 5 are described as follows:
- Initialization of eMIOS_0 counter.
- Generation of a second PWM pulse with DAOC channel. Set new period for global counter bus. And set new duty cycle to PWM1 and PWM2.
- Set the state of output pin to LOW, deinitialization of both PWM channels and stop the GPT counter.
Note: Disabling DAOC notification in interrupt function and set the state of output pin LOW are necessary because the PWM driver does not support single PWM pulse generation. See details in application software.
Application Software:
S32M276_RTD600_eMIOS_DAOC_Ip_example
S32K311_RTD600_eMIOS_DAOC_Ip_example
Figure 5. Signals of DAOC Example Project
6.3. OPWMT example project
OPWMT generates a PWM signal with a fixed offset and a trigger signal. It can be implemented using any channel types (X, Y, G and H).
This example implements one channel as GPI (for time reference in scope) and two channels in OPWMT mode initialized as follows:
- MCL: eMIOS_1
- Clock Divider Value (global prescaler): 200
- MCL: eMIOS_0
- Clock Divider Value (global prescaler): 1
- MCL: eMIOS_0_ch_23 (Global bus A)
- Master bus prescaler (UC internal prescaler): 1
- Default period: 60,000 ticks
- Master Bus Mode Type: MCB_UP_COUNTER
- PWM exclusive access: Enable
- GPT: eMIOS_1_ch_0
- GptEmiosPrescaler (UC internal prescaler): 1
- Emios Notification: Enable
- Emios Channel Mode: EMIOS_GPT_IP_CH_MODE_CONTINUOUS
- Compare Value: 750 ticks
- PWM: eMIOS_0_ch_1
- Counter Bus EMIOS_PWM_IP_BUS_A
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 60,000 ticks
- Duty cycle: 30,000 ticks
- Phase shift: 0 ticks
- Trigger: 15,000 ticks
- Flag Event response: EMIOS_PWM_IP_INTERRUPT_REQUEST
- PWM: eMIOS_0_ch_5
- Counter Bus EMIOS_PWM_IP_BUS_A
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 60,000 ticks
- Duty cycle: 30,000 ticks
- Phase shift: 7,500 ticks
- Trigger: 0 ticks
- Flag Event response: EMIOS_PWM_IP_NOTIFICATION_DISABLED
Clock Divider Value from MCL eMIOS_1, along with Compare Value from GPT eMIOS_1_ch_0 generates a time-out period. Once time-out is reached its Emios Notification toggles GPIO1. This allows us to observe in scope 3 events (see Figure 6) that will be described later.
The eMIOS_0_ch_23 channel is configured as global counter bus A. In this setup, it can act as the time base for other eMIOS_0 channels—specifically PWM1 and PWM2 in this case—enabling synchronization between them. This synchronization ensures that both channels share the same time base, thereby defining a common period for their operation.
Despite both channels being synchronized, phase shift feature is possible in this mode. Note PWM2 is phase shifted with respect to global counter bus A, and therefore with respect to PWM1.
An interrupt is requested on every flag event, during which GPIO2 is toggled. In this configuration, the flag is generated. This flag event, can be configured using Trigger parameter.
The three events shown in Figure 6 are described as follows:
- Initialization of eMIOS_0 counter.
- Set new period for global counter bus A (which means frequency modulation). Set new duty cycle to PWM channels. Set new Trigger placement value to PWM1. As well as set new phase shift value to PWM2.
- Set the state of output pin to LOW, deinitialization of both PWM channels and stop the GPT counter.
Application Software:
S32M276_RTD600_eMIOS_OPWMT_Ip_example
S32K311_RTD600_eMIOS_OPWMT_Ip_example
Figure 6. Signals of OPWMT Example Project
6.4. OPWMCB example project
OPWMCB generates a centered aligned PWM output signal with dead time insertion. It can be implemented using channel type G.
This example implements one channel as GPI (for time reference in scope) and three channels in OPWMCB mode initialized as follows:
- MCL: eMIOS_1
- Clock Divider Value (global prescaler): 200
- MCL: eMIOS_0
- Clock Divider Value (global prescaler): 1
- MCL: eMIOS_0_ch_23 (Global bus A)
- Master bus prescaler (UC internal prescaler): 1
- Default period: 60,000 ticks
- Master Bus Mode Type: MCB_UP_DOWN_MODE
- PWM exclusive access: Enable
- GPT: eMIOS_1_ch_0
- GptEmiosPrescaler (UC internal prescaler): 1
- Emios Notification: Enable
- Emios Channel Mode: EMIOS_GPT_IP_CH_MODE_CONTINUOUS
- Compare Value: 750 ticks
- PWM: eMIOS_0_ch_1
- Counter Bus EMIOS_PWM_IP_BUS_A
- Mode select: EMIOS_PWM_IP_MODE_OPWMCB_TRAIL_EDGE
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 59,998 ticks
- Duty cycle: 14,999 ticks
- Deadtime: 0 ticks
- Flag Event response: EMIOS_PWM_IP_NOTIFICATION_DISABLED
- PWM: eMIOS_0_ch_5
- Counter Bus EMIOS_PWM_IP_BUS_A
- Mode select: EMIOS_PWM_IP_MODE_OPWMCB_TRAIL_EDGE
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 59,998 ticks
- Duty cycle: 29,999 ticks
- Deadtime: 0 ticks
- Flag Event response: EMIOS_PWM_IP_NOTIFICATION_DISABLED
- PWM: eMIOS_0_ch_2
- Counter Bus EMIOS_PWM_IP_BUS_A
- Mode select: EMIOS_PWM_IP_MODE_OPWMCB_TRAIL_EDGE
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 59,998 ticks
- Duty cycle: 29,999 ticks
- Deadtime: 3,750 ticks
- Flag Event response: EMIOS_PWM_IP_NOTIFICATION_DISABLED
Clock Divider Value from MCL eMIOS_1, along with Compare Value from GPT eMIOS_1_ch_0 generates a time-out period. Once time-out is reached its Emios Notification toggles GPIO1. This allows us to observe in scope 3 events (see Figure 7) that will be described later.
The eMIOS_0_ch_23 channel is configured as global counter bus A. In this setup, it can act as the time base for other eMIOS_0 channels—specifically PWM1, PWM2 and PWM3 in this case—enabling synchronization between them. This synchronization ensures that these three channels share the same time base, thereby defining a common period for their operation.
Note: Synchronization in OPWMCB mode means PWM signals are center-aligned, instead of edge-aligned.
Despite all three PWM channels are center-aligned, and PWM2 and PWM3 have the same duty cycle, deadtime insertion feature is supported in this mode. Note trailing edge of PWM3 includes deadtime insertion with respect to PWM2, increasing high time.
Alternatively, by selecting the EMIOS_PWM_IP_MODE_OPWMCB_LEAD_EDGE mode, deadtime insertion is applied to the leading edge of PWM3 instead, decreasing high time.
The three events shown in Figure 7 are described as follows:
- Initialization of eMIOS_0 counter.
- Set new period for global counter bus A (which means frequency modulation). Set new duty cycle to all three PWM channels. As well as set new dead time value to PWM3.
- Set the state of output pin to LOW, deinitialization of both PWM channels and stop the GPT counter.
Application Software:
S32M276_RTD600_eMIOS_OPWMCB_Ip_example
S32K311_RTD600_eMIOS_OPWMCB_Ip_example
Figure 7. Signals of OPWMCB Example Project
6.5. OPWFMB example project
OPWFMB generates a output PWM signal with variable period and variable duty cycle using its internal counter. It can be implemented using channel types G.
This example implements one channel as GPI (for time reference in scope) and two channels in OPWFMB mode initialized as follows:
- MCL: eMIOS_1
- Clock Divider Value (global prescaler): 200
- GPT: eMIOS_1_ch_0
- GptEmiosPrescaler (UC internal prescaler): 1
- Emios Notification: Enable
- Emios Channel Mode: EMIOS_GPT_IP_CH_MODE_CONTINUOUS
- Compare Value: 750 ticks
- PWM: eMIOS_0_ch_1
- Counter Bus EMIOS_PWM_IP_BUS_INTERNAL
- Flag generation: Trailing_Edge
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 60,000 ticks
- Duty cycle: 30,000 ticks
- Flag Event response: EMIOS_PWM_IP_INTERRUPT_REQUEST
- PWM: eMIOS_0_ch_5
- Counter Bus EMIOS_PWM_IP_BUS_INTERNAL
- Flag generation: Trailing_Edge
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 60,000 ticks
- Duty cycle: 40,000 ticks
- Flag Event response: EMIOS_PWM_IP_NOTIFICATION_DISABLED
Clock Divider Value from MCL eMIOS_1, along with Compare Value from GPT eMIOS_1_ch_0 generates a time-out period. Once time-out is reached its Emios Notification toggles GPIO1. This allows us to observe in scope 3 events (see Figure
Due to its reliance on an internal counter, OPWFMB mode does not support synchronization with other eMIOS channels. However, it enables both Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) functionalities within a single eMIOS channel.
An interrupt is requested on every flag event, during which GPIO2 is toggled. In this configuration, the flag is generated on the trailing edge—interpreted here as the rising edge, considering HIGH polarity. Alternatively, it can be configured to trigger on both the trailing and leading edges, allowing interrupts on both transitions.
The three events shown in Figure 8 are described as follows:
- Initialization of eMIOS_0_ch_1 and eMIOS_0_ch_5 counters.
- Set new period and new duty cycle to each PWM channels (which means frequency modulation).
- Set the state of output pin to LOW, deinitialization of both PWM channels and stop the GPT counter.
Application Software:
S32M276_RTD600_eMIOS_OPWFMB_Ip_example
S32K311_RTD600_eMIOS_OPWFMB_Ip_example
Figure 8. Signals of OPWFMB Example Project
6.6. PWM design considerations
During pin assignment for application, beyond the “eMIOS Channel Types” tables for PWM mode support, “eMIOS channel configuration” tables for channel types per instance and the “Counter Buses, Channels, and Timebase Sources” tables for clocking in the reference manuals, consider the following support features for each PWM mode.
- Interrupt support is available through flag generation for the OPWMB, DAOC, OPWMCB, and OPWFMB modes. It is also supported in OPWMT mode through flag generation, but with more flexible timing through the configuration of the Trigger parameter.
- Triggering support is also available via flag generation (see interrupt support for more details).
- A single PWM pulse can be generated in all PWM modes by disabling notifications and setting the state of output pin to LOW in the interrupt function, similar to the approach used in the DAOC example project.
- All PWM modes support output state control for individual channels.
- Frequency modulation is supported in OPWMB, DAOC, OPWMT, and OPWMCB modes by configuring another eMIOS channel as a counter bus to serve as the time base. In OPWFMB mode, frequency modulation is supported using its internal counter.
- Synchronization is only achievable for channels that share the same time base.
- Edge-alignment is also limited to channels using the same time base, with the exception of OPWMCB mode.
- Center-alignment and dead-time insertion are core features of OPWMCB mode but can also be achieved in OPWMB and OPWMT modes by properly configuring the duty cycle and phase shift parameters.
- The complementary output feature is supported in all PWM modes when the Polarity parameter is configured. However, it only makes practical sense when used in combination with synchronization and/or dead-time insertion features.
- Phase shift functionality is supported exclusively in OPWMB and OPWMT modes. It can only be applied when the generated pulse remains entirely within the defined PWM period.
- The maximum achievable PWM frequency is determined by the CORE CLK. On the other hand, lower PWM frequencies can be achieved in OPWMB, DAOC, OPWMT, and OPWMCB modes by configuring another eMIOS channel as a counter bus to serve as the time base and adjusting its clock divider value (range: 1–256). *Additionally, in all PWM modes (including OPWFMB), lower PWM frequencies can be achieved by configuring the clock prescaler parameter (range: 1–16) in each channel.
Table 1 summarizes the support features available for each PWM mode.
| OPWMB | DAOC | OPWMT | OPWMCB | OPWFMB | |
| Interrupts | x | x | x | x | x |
| Triggering | x | x | x | x | x |
| Single PWM pulse | x | x | x | x | x |
| Output state control | x | x | x | x | x |
| Frequency modulation | x | x | x | x | x |
| Synchronization | x | x | x | x | |
| Edge-alignment | x | x | x | ||
| Center-alignment | x | x | x | ||
| Dead-time insertion | x | x | x | ||
| Complementary output | x | x | x | ||
| Phase shift | x | x | |||
| Lower PWM frequencies | x | x | x | x | x* |
Table 1. Supported features across PWM modes
7. Input Capture Unit (ICU) driver
The ICU driver can implement the following eMIOS modes:
- Input Pulse Width Measurement (IPWM)
- Input Period Measurement (IPM)
- Single Action Input Capture (SAIC)
The following sections detail the implementation of each ICU measurement mode and highlight their key characteristics.
Connections:
S32M27XEVB-C064 / S32K31XEVB-Q100 -> Pin -> Signal -> Label
J60-1 / J40-12 -> PTE16 -> siul2_gpio_144 -> GPIO1
J21-1 / J38-6 -> PTD16 -> emios_0_ch_1_g -> PWM1
J21-3 / J39-1 -> PTB5 -> emios_0_ch_5_g -> ICU1
J60-4 / J38-3 -> PTD0 -> siul2_gpio_96 -> GPIO2
Connect:
PWM1 -> ICU1
Note:
For S32M27XEVB-C064, consider remove following resistors: R208, R169, R208 and R181.
Clocking:
EMIOSx_CLK -> 120MHz
7.1. IPWM example project
IPWM determines the width of an input signal, using channel types G and H.
This example implements one channel as GPI (for time reference in scope) and one channels in OPWMB mode (PWM1) and one channel in IPWM mode (ICU1) initialized as follows:
- MCL: eMIOS_1
- Clock Divider Value (global prescaler): 200
- MCL: eMIOS_0
- Clock Divider Value (global prescaler): 1
- MCL: eMIOS_0_ch_23
- Clock Divider Value: 1
- Default period: 60,000 ticks
- Master Bus Mode Type: MCB_UP_COUNTER
- PWM exclusive access: Enable
- GPT: eMIOS_1_ch_0
- Emios Notification: Enable
- Emios Channel Mode: EMIOS_GPT_IP_CH_MODE_CONTINUOUS
- Compare Value: 750 ticks
- PWM: eMIOS_0_ch_1
- Counter Bus EMIOS_PWM_IP_BUS_A
- Flag generation: Trailing_Edge
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 60,000 ticks
- Duty cycle: 30,000 ticks
- ICU: eMIOS_0_ch_5
- Icu Measurement Mode: ICU_MODE_SIGNAL_MEASUREMENT
- Icu Signal Measurement Property: ICU_DUTY_CYCLE
- Icu Sub Mode for Measurement: IPWM
Clock Divider Value from MCL eMIOS_1, along with Compare Value from GPT eMIOS_1_ch_0 generates a time-out period. Once time-out is reached its Emios Notification toggles GPIO1. This allows us to observe in scope 3 events (see Figure 9) that will be described later.
The eMIOS_0_ch_23 channel is configured as global counter bus A. In this setup, it can act as the time base for other eMIOS_0 channels—specifically PWM1 in this case.
ICU1 measures PWM1 twice in code and toggles GPIO2 once the results are available.
The three events shown in Figure 9 are described as follows:
- Initialization of eMIOS_0 counter, PWM channel and ICU instance. Additionally it start first signal measurement.
- Set new period and duty cycle to PWM1. As well as start second signal measurement.
- Set the state of output pin to LOW, deinitialization of PWM channel and stop the GPT counter.
Application Software:
S32M276_RTD600_eMIOS_IPWM_Ip_example
S32K311_RTD600_eMIOS_IPWM_Ip_example
When you suspend debug session, in Expressions tab (Figure 10) you can observe results: g_icuResults[0] corresponds to the first signal measurement meanwhile g_icuResults[1] corresponds to the second signal measurement.
Figure 10. Expressions tab of IPWM Example Project
7.2. IPM example project
IPM determines the period of an input signal, using channel types G and H.
This example implements one channel as GPI (for time reference in scope) and one channels in OPWMB mode (PWM1) and one channel in IPM mode (ICU1) initialized as follows:
- MCL: eMIOS_1
- Clock Divider Value (global prescaler): 200
- MCL: eMIOS_0
- Clock Divider Value (global prescaler): 1
- MCL: eMIOS_0_ch_23
- Clock Divider Value: 1
- Default period: 60,000 ticks
- Master Bus Mode Type: MCB_UP_COUNTER
- PWM exclusive access: Enable
- GPT: eMIOS_1_ch_0
- Emios Notification: Enable
- Emios Channel Mode: EMIOS_GPT_IP_CH_MODE_CONTINUOUS
- Compare Value: 750 ticks
- PWM: eMIOS_0_ch_1
- Counter Bus EMIOS_PWM_IP_BUS_A
- Flag generation: Trailing_Edge
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 60,000 ticks
- Duty cycle: 30,000 ticks
- ICU: eMIOS_0_ch_5
- Icu Measurement Mode: ICU_MODE_SIGNAL_MEASUREMENT
- Icu Signal Measurement Property: ICU_PERIOD_TIME
- Icu Sub Mode for Measurement: IPM
Clock Divider Value from MCL eMIOS_1, along with Compare Value from GPT eMIOS_1_ch_0 generates a time-out period. Once time-out is reached its Emios Notification toggles GPIO1. This allows us to observe in scope 3 events (see Figure 11) that will be described later.
The eMIOS_0_ch_23 channel is configured as global counter bus A. In this setup, it can act as the time base for other eMIOS_0 channels—specifically PWM1 in this case.
ICU1 measures PWM1 twice in code and toggles GPIO2 once the results are available.
The three events shown in Figure 11 are described as follows:
- Initialization of eMIOS_0 counter, PWM channel and ICU instance. Additionally it start first signal measurement.
- Set new period and duty cycle to PWM1. As well as start second signal measurement.
- Set the state of output pin to LOW, deinitialization of PWM channel and stop the GPT counter.
Application Software:
S32M276_RTD600_eMIOS_IPM_Ip_example
S32K311_RTD600_eMIOS_IPM_Ip_example
Figure 11. Signals of IPM Example Project
When you suspend debug session, in Expressions tab (Figure 12) you can observe results: g_icuResults[0] corresponds to the first signal measurement meanwhile g_icuResults[1] corresponds to the second signal measurement.
Figure 12. Expressions tab of IPM Example Project
7.3. SAIC example project – Edge Counter
SAIC mode can emulate Pulse Edge Counting (PEC) mode using any channel types (X, Y, G and H).
This example implements one channel as GPI (for time reference in scope) and one channels in OPWMB mode (PWM1) and one channel in SAIC mode (ICU1) initialized as follows:
- MCL: eMIOS_1
- Clock Divider Value (global prescaler): 200
- MCL: eMIOS_0
- Clock Divider Value (global prescaler): 1
- MCL: eMIOS_0_ch_23
- Clock Divider Value: 1
- Default period: 60,000 ticks
- Master Bus Mode Type: MCB_UP_COUNTER
- PWM exclusive access: Enable
- GPT: eMIOS_1_ch_0
- Emios Notification: Enable
- Emios Channel Mode: EMIOS_GPT_IP_CH_MODE_CONTINUOUS
- Compare Value: 750 ticks
- PWM: eMIOS_0_ch_1
- Counter Bus EMIOS_PWM_IP_BUS_A
- Flag generation: Trailing_Edge
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 60,000 ticks
- Duty cycle: 30,000 ticks
- ICU: eMIOS_0_ch_5
- Icu Measurement Mode: ICU_MODE_EDGE_COUNTER
- Icu Overflow Notification: Emios0_Ch5_Notification
- Icu Sub Mode for Measurement: SAIC
Clock Divider Value from MCL eMIOS_1, along with Compare Value from GPT eMIOS_1_ch_0 generates a time-out period. Once time-out is reached its Emios Notification toggles GPIO1. This allows us to observe in scope 3 events (see Figure 13) that will be described later.
The eMIOS_0_ch_23 channel is configured as global counter bus A. In this setup, it can act as the time base for other eMIOS_0 channels—specifically PWM1 in this case.
ICU1 count PWM1’s edges and toggles GPIO2 when an overflow occurs, which is defined by max counter value.
The three events shown in Figure 13 are described as follows:
- Initialization of eMIOS_0 counter, PWM channel and ICU instance. Additionally it sets initial counter value = 2 and max counter value = 4, as well as enables edge count.
- Set new period and duty cycle to PWM1.
- Set the state of output pin to LOW, deinitialization of PWM channel, stop the GPT counter and gets edge counter measurement.
Application Software:
S32M276_RTD600_eMIOS_SAIC_Edge_Counter_Ip_example
S32K311_RTD600_eMIOS_SAIC_Edge_Counter_Ip_example
When you suspend debug session, in Expressions tab (Figure 14) you can observe g_icuResults = 3, which correspond to edge count, after having overflowed 6 times.
Note: ICU is initialized after PWM, so first edge is not counted.
7.4. SAIC example project – Signal Edge Detect
SAIC mode can also generate an interrupt when detects an edge using any channel types (X, Y, G and H).
This example implements one channel as GPI (for time reference in scope) and one channels in OPWMB mode (PWM1) and one channel in SAIC mode (ICU1) initialized as follows:
- MCL: eMIOS_1
- Clock Divider Value (global prescaler): 200
- MCL: eMIOS_0
- Clock Divider Value (global prescaler): 1
- MCL: eMIOS_0_ch_23
- Clock Divider Value: 1
- Default period: 60,000 ticks
- Master Bus Mode Type: MCB_UP_COUNTER
- PWM exclusive access: Enable
- GPT: eMIOS_1_ch_0
- Emios Notification: Enable
- Emios Channel Mode: EMIOS_GPT_IP_CH_MODE_CONTINUOUS
- Compare Value: 750 ticks
- PWM: eMIOS_0_ch_1
- Counter Bus EMIOS_PWM_IP_BUS_A
- Flag generation: Trailing_Edge
- Polarity: EMIOS_PWM_IP_ACTIVE_HIGH
- Period: 60,000 ticks
- Duty cycle: 30,000 ticks
- ICU: eMIOS_0_ch_5
- Icu Measurement Mode: ICU_MODE_SIGNAL_EDGE_DETECT
- Icu Signal Notification: Emios0_Ch5_Notification
- Icu Sub Mode for Measurement: SAIC
Clock Divider Value from MCL eMIOS_1, along with Compare Value from GPT eMIOS_1_ch_0 generates a time-out period. Once time-out is reached its Emios Notification toggles GPIO1. This allows us to observe in scope 3 events (see Figure 15) that will be described later.
The eMIOS_0_ch_23 channel is configured as global counter bus A. In this setup, it can act as the time base for other eMIOS_0 channels—specifically PWM1 in this case.
ICU1 detect PWM1’s edges and generates an interrupt for each of them. At every interrupt, GPIO2 is toggled and g_icuCount is increased by one.
The three events shown in Figure 15 are described as follows:
- Initialization of eMIOS_0 counter, PWM channel and ICU instance. Additionally it enables edge detection.
- Set new period and duty cycle to PWM1.
- Set the state of output pin to LOW, deinitialization of PWM channel, stop the GPT counter and disable edge detection.
Application Software:
S32M276_RTD600_eMIOS_SAIC_Signal_Edge_Detect_Ip_example
S32K311_RTD600_eMIOS_SAIC_Signal_Edge_Detect_Ip_example
Figure 15. Signals of SAIC Example Project – Signal Edge Detect
When you suspend debug session, in Expressions tab (Figure 16) you can observe g_icuCount = 21, which correspond to edge count.
Note: ICU is initialized after PWM, so first edge is not counted.
Figure 16. Expressions tab of SAIC Example Project – Signal Edge Detect
7.5. ICU design considerations
During pin assignment for application, beyond the “eMIOS Channel Types” tables of reference manuals, consider the following points for each ICU mode.
Advantages of IPWM and IPM modes over SAIC mode:
- The size of the driver code to measure duty cycle is less for a channel which supports IPWM mode as compared to a channel which uses SAIC mode to capture the duty cycle.
- For every period of the measured signal, the interrupt generated is just 1 in IPWM mode as compared to a channel which uses SAIC mode where the number of interrupt generated is 2
- Because of these reasons the driver code execution speed is faster in IPWM mode as compared to SAIC mode.
Limitation of IPWM and IPM modes over SAIC mode:
- If we configure the EMIOS channel which uses IPWM mode to capture a duty cycle of a varying PWM Signal, we will get the interrupt during only one edge i.e. opposite edge of the starting edge. But to capture the duty cycle of a varying PWM Signal, we have to get the interrupt during both falling edge and rising edge. Hence in IPWM mode we get the delayed duty cycle values.
- Because of this limitation of IPWM mode, we can use EMIOS channel which uses SAIC mode to capture the duty cycle of a varying PWM Signal.
Overflow support
- Due to hardware implementation, the Icu Overflow Notification is just supported in ICU_MODE_EDGE_COUNTER.
Table 2 summarizes the support features available for each ICU mode.
| IPWM | IPM | SAIC | |
| Duty cycle measurement | x | x | |
| High time measurement | x | x | |
| Low time measurement | x | x | |
| Period time measurement | x | x | x |
| Edge counter | x | ||
| Edge detection | x | ||
| Timestamp measurement | x |
Table 2. Supported features across ICU modes
8. Conclusion
This document provides an overview of the driver structure, operating modes, and key features of the eMIOS module for the S32M27x and S32K3 series. It includes example codes to illustrate function implementation, helping users integrate the module effectively into their applications. Additionally, it outlines design considerations to support optimal usage and system integration.
9. References
- S32 Design Studio for S32 Platform
- Real-Time Drivers (RTD)
- S32M2xx Data Sheet [S32M2xx_DS]
- S32M27x Reference Manual [S32M27XRM]
- S32M27x PMSM/BLDC Motor Control Evaluation Board [S32M27XEVB]
- S32K3xx MCU Family Data Sheet [S32K3xx]
- S32K3xx MCU Family - Reference Manual [S32K3XXRM]
- S32K31XEVB-Q100 Evaluation Board for Automotive General Purpose [S32K31XEVB-Q100]
- S32K3XX Real Time Control: eMIOS (Public) [Training Slides]
10. Appendix
Following examples were built and tested using the following IDE and Driver versions:
- S32 Design Studio for S32 Platform Version 3.6.2
- S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0
10.1. Application Software Content:
S32M276_RTD600_eMIOS_Ip_examples.zip:
- S32M276_RTD600_eMIOS_GPT_Ip_example
- S32M276_RTD600_eMIOS_SAOC_Ip_example
- S32M276_RTD600_eMIOS_OPWMB_Ip_example
- S32M276_RTD600_eMIOS_DAOC_Ip_example
- S32M276_RTD600_eMIOS_OPWMT_Ip_example
- S32M276_RTD600_eMIOS_OPWMCB_Ip_example
- S32M276_RTD600_eMIOS_OPWFMB_Ip_example
- S32M276_RTD600_eMIOS_IPWM_Ip_example
- S32M276_RTD600_eMIOS_IPM_Ip_example
- S32M276_RTD600_eMIOS_SAIC_Edge_Counter_Ip_example
- S32M276_RTD600_eMIOS_SAIC_Signal_Edge_Detect_Ip_example
S32k311_RTD600_eMIOS_Ip_examples.zip:
- S32K311_RTD600_eMIOS_GPT_Ip_example
- S32K311_RTD600_eMIOS_SAOC_Ip_example
- S32K311_RTD600_eMIOS_OPWMB_Ip_example
- S32K311_RTD600_eMIOS_DAOC_Ip_example
- S32K311_RTD600_eMIOS_OPWMT_Ip_example
- S32K311_RTD600_eMIOS_OPWMCB_Ip_example
- S32K311_RTD600_eMIOS_OPWFMB_Ip_example
- S32K311_RTD600_eMIOS_IPWM_Ip_example
- S32K311_RTD600_eMIOS_IPM_Ip_example
- S32K311_RTD600_eMIOS_SAIC_Edge_Counter_Ip_example
- S32K311_RTD600_eMIOS_SAIC_Signal_Edge_Detect_Ip_example
