******************************************************************************** * Detailed Description: * * Example shows possible setting for PWM duty cycle update using DMA. * FTM0 ch0 is set to Edge aligned mode with 20KHz period. * Initialization trigger is routed back to HW trigger 1 using TRGMUX, so this HW * trigger can be used for CnV synchronization. * DMA on FTM0 ch0 is enabled (on ch0 CHF flag) and DMA ch0 configured to update C0V * from duty cycle variable. * NOte CHF is not set for 0% and 100% duty cycle, thus no DMA trigger is generated. * * Green LED is dimming as duty is changing. * * ------------------------------------------------------------------------------ * Test HW: S32K118EVB-Q64 * MCU: PS32K118LAMLH 0N97V * Compiler: S32DS.ARM.2.2 * SDK release: S32SDK_S32K1xx_RTM_3.0.3 * Debugger: Lauterbach, OpenSDA * Target: internal_FLASH * ******************************************************************************** Revision History: 1.0 Sep-16-2021 Petr Stancik Initial Version *******************************************************************************/

The purpose of this demo application is to show you the usage of the FlexCAN module configured to use Flexible Data Rate using the S32 SDK API. - In the first part, the application will setup the board clocks, pins and other system functions such as SBC if the board uses this module as a CAN transceiver. - Then it will configure the FlexCAN module features such as FD, Bitrate and Message buffers - The application will wait for frames to be received on the configured message buffer or for an event raised by pressing one of the two buttons which will trigger a frame send to the recipient. - Pressing SW3 button of board 1 shall trigger a CAN transfer that results in toggling the RED led on board 2. - Pressing SW2 button of board 1 shall trigger a CAN transfer that results in toggling the GREEN led on board 2. - This demo application requires two boards, one configured as master and the other one configured as slave (see MASTER/SLAVE defines in application code) or single board connected with CAN tool. - Both the event and error callbacks are installed, callback_test variable indicates event entering bit0 .. RX complete bit1 .. TX complete bit2 .. ERR INT flag set bit3 .. BOFF INT flag set - to enter bus off simply short CANH with GND and send message using either SW1 or SW2, FlexCAN enters bus off (error event) and blue LED is ON. Also TX MB is aborted. Remove short connection and send message again normally, blue LED is off.   ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: FS32K1441 0N57U * Compiler: S32DS.ARM.2.2 * SDK release: S32SDK_S32K1xx_RTM_3.0.3 * Debugger: Lauterbach, OpenSDA * Target: internal_FLASH  

******************************************************************************** Detailed Description: This example shows SRAM ECC injection. By default, a double-bit ECC error is injected on read access of a location in SRAM_U region. This can be changed with the SRAM_U and DOUBLE_BIT macros. The errors can be detected by both the ERM and MCM modules and the corresponding interrupts can be called. Although only ERM is needed, for demonstration purposes, the MCM interrupt is enabled as well with a lower priority than the ERM interrupts. The ERM interrupts that are called first disable the injection mechanism so that subsequent errors can not be detected during a stack read access. The default S32 Design Studio start_up file copies the vector table to the SRAM_L region. To be able to inject ECC errors in this SRAM region and call the interrupts, the copying is disabled by __flash_vector_table__ symbol  declared in the start_up.h file and defined in the S32K144_64_flash linker file. -------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 Target: internal_FLASH ********************************************************************************

*******************************************************************************************************  Detailed Description:  Configures the MCU to run system clock from XOSC.  LPUART1 is set to respond to LIN header sent from master.  Based on ID received the LPUART1 either receive frame's data and compare checksum  or publish requested data with calculated checksum. Enhanced checksum is used.  Interrupt is used for RX and TX operation and 2 versions of interrupt routine are available.  VER 1 ... during response transmission receiver disabled and transmit interrupt enabled  VER 2 ... during response transmission receiver is kept enabled  ------------------------------------------------------------------------------  Test HW: S32K116 EVB-Q048  MCU: PS32K116LAM 0N96V  Fsys: 40MHz  Debugger: Lauterbach  Target: internal_FLASH ******************************************************************************************************

An example implementation of SENT protocol receiver with S32K118 evaluation board. The input is expected in J106, TICK duration is 2,75us. CRC is calculated and check, the decoded output is printed into terminal via UART (ASCII)

Using S32k144 ISELD SDK driver and adding Touch Sensor software, a demo is created to show different light combinations when electrodes of S32K144 EVB are touched. ADK ISELED board is attached to S32K144 EVB.

******************************************************************************************************************************************** Detailed Description: This example shows use of RTC in VLPS mode. The MCU is put into the VLPS mode (Sleep-On-Exit). RTC alarm interrupt brings it to VLPR every 3s and toggles BLUE LED (PTD0). Since it works in the Sleep-On-Exit mode, after the ISR, the MCU goes to VLPS again without calling the WFI instruction. When BTN0 (S32K144 EVB) is pressed, the power mode switch from VLPS to VLPR and other way round. Interrupt is triggered on rising edge (PTC12), filtered by digital filter (clocked from LPO). In VLPR, RTC seconds interrupt is enabled as well and toggles RED LED (PTD15) in the ISR. RTC_CLKOUT (1Hz) and CLKOUT (bus_clk) can be monitored at PTD13 and PTD14 respectively. CLKOUT is not available in VLPS. The MCU needs to be power-cycled and run stand-alone. -------------------------------------------------------------------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K 0N57U Debugger: S32DS_ARM_2.2, OpenSDA Target: internal_FLASH ********************************************************************************************************************************************

Welcome to the S32K Microcontrollers forum. Get expert advice from the NXP developer community. Our support team also monitors these forums to provide answers and take your feedback.   Anyone can read the discussions, but only registered NXP Community members can post questions and comments. Before you ask a question, please search the community to find if someone has already offered a solution. If you don’t see a solution, then ask the community your question. S32K Web page S32K Reference manual S32K Data sheet S32K Application notes and other documents S32K Evaluation Board S32 Design Studio IDE https://community.nxp.com/docs/DOC-334170 

I write a doc and a demo about LPUART hardware flow control, runs on s32k144 evb board with RTM 3.0.0, the flow control function work normally. If you have any question please contact me. 

********************************************************************************  Detailed Description:  Example shows how to use FlexCAN 0 Pretended networking mode to allow FlexCAN  module to wake up MCU from STOP mode using SDK.  Wake up by Timeout and wake up by Match events are enabled.  Also pin interrupt can be used to exit STOP mode.  So MCU enters STOP mode by pressing SW3 button.  MCU exits STOP mode when one of following happens:  - no CAN message comes in 8sec (CAN PN timeout event)  - message with standard ID 0x554 or 0x555 comes (CAN PN match event)  - SW2 button is pressed (PTC12 interrupt)  In run mode blue LED is dimming and the rate is different for each wakeup event  ------------------------------------------------------------------------------  Test HW: S32K116EVB-Q48  MCU: PS32K116LAM 0N96V  Compiler: S32DS.ARM.2.2  SDK release: S32SDK_S32K1xx_RTM_3.0.0  Debugger: Lauterbach, OpenSDA  Target: internal_FLASH ********************************************************************************

******************************************************************************************** * Detailed Description: * LPIT_ch0 triggers DMA_ch0 periodically (1ms). * Every trigger starts a minor DMA loop (8 bytes) transfer to the LPSPI1 TX FIFO. * There are 8 minor loops per one major loop (64 bytes in 8ms). * LPSPI1 sends two 32bit frames every 1ms. * LPSPI1 RX data are masked, they are not stored in the RX FIFO. * ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: S32K144 0N57U * Debugger: S32DS 2.2, OpenSDA * Target: internal_FLASH ********************************************************************************************

******************************************************************************************************** Detailed Description: On WDOG timeout, the WDOG module requests reset in the Reset Control Module (RCM). The reset request to RCM can be delayed by 128 bus clock cycles if the WDOG interrupt is enabled (WDOG_CS[INT] = 1). If enabled, the WDOG interrupt vector is fetched or it becomes pending in NVIC. After the delay, the reset is requested in RCM. Independently of the WDOG interrupt, the RCM can again delay the reset by up to 514 LPO additional clock cycles if the corresponding RCM_WDOG interrupt is enabled (RCM_SRIE[GIE, WDOG] = 1). If so, instead of forcing reset immediately, the module requests the RCM interrupt in NVIC and forces the reset after the additional delay (RCM_SRIE[DELAY]). Either way, the reset is forced, it can’t be stopped only delayed. This example enables the WDOG interrupt in the WDOG_CS register but leaves this interrupt disabled in NVIC. That means that this interrupt becomes pending in NVIC on the WDOG timeout, it sets the WDOG_CS_FLG, but the vector doesn’t get fetched. The RCM interrupt is enabled and it gets asserted in NVIC after the WDOG interrupt delay (2.67us (48MHz BUS CLK)). The WDOG flag (WDOG_CS_FLG) is read in the RCM ISR instead. The execution stays in an infinite loop for 514 LPO (128kHz) cycles (~ 4ms) until the reset is forced. ------------------------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 OpenSDA Target: internal_FLASH ********************************************************************************************************

************************************************************************************************ Detailed Description: WDOG tested in SystemInit() function (system_S32K116.c) after POR. For debugging purposes: - WDOG counter reference clock is pre-scaled to slow the test (CS_PRES = 1). - During CNT_LOW test, BLUE LED (PTE8) ON. - During CNT_HIGH test, RED LED (PTD16) ON. - Once both tests have passed, GREEN LED (PTD15) ON. If either of the test fails, WDOG will stay in its default configuration and rest the MCU. ---------------------------------------------------------------------------------------------------------------- Test HW: S32K116EVB-Q048 REV.B MCU: S32K116 0N96V Debugger: S32DSR1, OpenSDA Target: internal_FLASH ************************************************************************************************

****************************************************************************************************************** Detailed Description: The example code shows CMP in Round-robin mode. CMP is clocked (125kHz) and triggered (80ms) by LPTMR, operates in VLPS. Input channels are CMP0_IN1 (PTA1), CMP0_IN2 (PTC4), CMP0_IN3 (PTE8), CMP0_IN4 (PTC3). The initial state of CMP outputs is 0 (Input analog pins < DAC input (Vin1/2)) The input pins are pulled down internally for debugging purposes. CPM will wake up the MCU if an input has changed. BLUE LED flashes 1x if CMP_IN1 has changed, 2x CMP0_IN2, 3x CMP0_IN3, 4x CMP0_IN4. After that, the MCU goes back to VLPS. ------------------------------------------------------------------------------------------------------------------------------------- Test HW: S32144EVB-Q100X MCU: S32K144 (0N47T) Debugger: S32DS2.0, OpenSDA Target: internal_FLASH ******************************************************************************************************************

Where can I get s32k14x data sheet or reference manual???

Abstract This example presents an use case for analogue data capturing using eMIOS, BCTU, SAR-ADC and DMA modules on S32K39-37-36 series based on the RTD low level API to support diverse application needs.   Connections: S32K396-BGA-DC1 -> Pin -> Signal -> Label J62-1 -> PTC30 -> siul2_gpio_xx -> GPIO1_GPT (D0) J58-1 -> PTE14 -> emios_0_ch_19_z -> PWM1 J58-2 -> PTG9 -> siul2_gpio_xx -> GPIO2_eMIOS_Trigger J62-2 -> PTC31 -> siul2_gpio_xx -> GPIO3_BTCU_Trigger J62-4 -> PTD6 -> siul2_gpio_xx -> GPIO4_BTCU_Watermark J62-24 -> PTB14 -> adc1_s21 -> ADC1 *To use the potentiometer of S32X-MB connect: J62-24 (in S32K396-BGA-DC1) to P26-1 (in S32X-MB) Note: Following line should be added in project/generate/src/Bctu_Ip_PBcfg.c every time the code is updated in Config Tools: #define DMA_LOGIC_CH_0 ((uint8)0U)   Detailed Description: The Compare Value of GPT eMIOS_0_ch_0 generates a time-out period. Once time-out is reached its Emios Notification toggles GPIO1. This allows us to observe in scope 2 events, which describe the start and the end of the signal sequence. The eMIOS_0_ch_23 channel is configured as global counter bus A. In this setup, it can act as the time base for other eMIOS_0 channels, enabling synchronization between other them—there is just one PWM in this case. This synchronization ensures that channels share the same time base, thereby defining a common period for their operation. The emios_0_ch_19_g channel is configured as OPWMT mode, which offer more flexibility for triggering. An interrupt is requested on every flag event, during which GPIO2 is toggled—happens at half the time high in this case. This flag event, can be configured using Trigger parameter. For more details about eMIOS, please refer to S32M27x/S32K3 – eMIOS Usage, considering differences for porting from S32K3 to S32K39-37-36 in AN14301. The BCTU implements a list for parallel conversions using ADC0 and ADC1. Which is triggered by the eMIOS channel, and the resulting data is stored in FIFO1, as follows: ADC0: VREFH_ChanNum51 -> BANDGAP_ChanNum48 ADC1: VREFL_ChanNum50 -> S21_ChanNum45 For debugging purposed the GPIO3 is toggled every BCTU Trigger Notification. Additionally, the GPIO4 is toggled in BCTU Watermark Notification, which happens every time the number of active entries in FIFO exceeds the watermark level, and therefore the data is available for reading. See full signal sequence in Figure 1: Figure 1. Signals of example project When you suspend debug session, in Expressions tab (Figure 2) you can observe results: g_fifo1Result, which corresponds to the BCTU list measurements, meanwhile g_fifo1Volts corresponds to the conversion in volts. Figure 2. Expressions tab of example project   References S32 Design Studio for S32 Platform Real-Time Drivers (RTD) S32K39, S32K37 and S32K36 Data Sheet [S32K39-S32K37-DS] S32K39, S32K37, and S32K36 Reference Manual [S32K396RM] S32K344 to S32K39/S32K37 Migration Guide [AN14301] S32K39/37/36 Electrification Microcontrollers Evaluation Board [S32K396-BGA-DC1] S32X-MB I/O Extension Evaluation Board for Real-Time Domain Control and Actuation [S32X-MB] S32M27x/S32K3 – eMIOS Usage [S32M Knowledge Base] S32M27x/S32K3 – eMIOS/BTCU/ADC/DMA – [RTD600] [S32M Knowledge Base] Application Software: - S32K396_RTD600_eMIOS_BCTU_SARADC_DMA_Ip_example Example was built and tested using the following IDE and Driver versions: - S32 Design Studio for S32 Platform Version 3.6.3 - S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0

This post presents two complementary FlexCAN communication examples for the S32K3X4EVB-T172 evaluation board, showcasing both low-level IP layer and AUTOSAR MCAL layer implementations. These examples are basic routines for configuring the component in normal/user mode, as the RTD examples are configured for loopback mode. To test CAN communication, another board or a CAN analyzer must be used. ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 * MCU: S32K344 * Compiler: S32DS 3.6.2 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH ------------------------------------------------------------------------------  Example 1: FlexCAN IP Layer This project demonstrates a basic FlexCAN setup using the IP-level driver. It configures a standard CAN message; with transmission through polling and reception using interrupts. The TJA1153 transceiver is initialized through a custom configuration sequence. An ACK message is sent upon each reception. The GREEN LED toggles every 10 received messages. Message buffer is configured to accept STD ID 0x123 with  FlexCAN_Ip_SetRxIndividualMask()  &  FlexCAN_Ip_ConfigRxMb() .  Example 2: FlexCAN MCAL Layer This project uses the AUTOSAR MCAL stack, leveraging  Can_43_FLEXCAN  and  CanIf  modules for CAN communication. Transmission is done via polling, while reception is configured via interrupts. STD ID is set to 0x123, and acceptance mask is set to 0x0 (accept all IDs). The same TJA1153 transceiver is used. CAN messages are sent and received using  CanIf  callbacks. The GREEN LED toggles every 10 received messages. TJA1153 is used in both examples with macros TJA1153 & TJA1153_EVB_TRCV respectively. If not defined, standard transceiver initialization is done (CAN0_STB & CAN0_EN pins set to HIGH).  These examples are provided as is with no guarantees and no support. These are basic routines meant to be used as reference only.

This simple example demonstrates how to configure and handle UART interrupts using the LPUART module on the S32K312-EVB. It sets up a UART callback function and initiates reception in single-byte mode. After each byte is received, the buffer is updated using  Lpuart_Uart_Ip_SetRxBuffer() , unless a newline character ( '\n' ) is detected, in which case a reception flag is set to signal the main loop. When the  LPUART_UART_IP_EVENT_END_TRANSFER  event occurs, reception is re-enabled using  Lpuart_Uart_Ip_AsyncReceive() . Only basic event handling is implemented; other UART events are acknowledged but not processed. The example uses LPUART instance 6, enabling serial communication via the USB port (J40) on the S32K312-EVB. If using TeraTerm, ensure the transmit setting is configured to LF (Line Feed) to properly send newline characters when pressing Enter.  ------------------------------------------------------------------------------ * Test HW: S32K312EVB-Q172 * MCU: S32K312 * IDE: S32DS3.6.2 * RTD release: 6.0.0 * Debugger: PE Micro * Target: internal_FLASH  ------------------------------------------------------------------------------ Test result:

* ================================================================================================== Detailed Description: * This example shows how to implement the UART RX/TX using interrupt/callback under FreeRTOS. * LPUART6 is set for 115200, 8N1 using interrupt processing. Callback is called for single byte received. * Reception is advanced until buffer is full or "\n" is received. * 2 tasks (receive/send) and 1 Queue are created. * ReceiveTask starts new UART reception, waits for completion and puts received message into Queue. * SendTask gets the message from Queue, echoes it back and toggle pin (LED_PIN <-> PTA29). * ================================================================================================== * Test HW: S32K3x4EVB-T172 Rev B * MCU: S32K344_172HDQFP * Compiler: S32DS 3.6.2 * RTD release: S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0 * Debugger: On-Board Debugger (J41) * Target: Internal_FLASH * Serial: 115200, 8N1 * ==================================================================================================   Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.