Some customers inquire about the FreeMASTER JumpStart Project mentioned in the Get Started with the S32K1xxEVB. So here to talk about the problems you may encounter and how to solve them. FreeMASTER JumpStart project download.png Where to download FreeMASTER JumpStart Project Customers may not find where to download FreeMASTER JumpStart Project at the moment. It should be downloaded from the Embedded Software under Design Resources of the development board. But the download link of S32K142EVB \ S32K144EVB \ S32K146EVB is missing. Design Resources Embedded Software.pngWe can search the keywords “* JumpStart” at www.nxp.com download embedded application software and PC host application software that you need. Search JumpStart.png Which version of S32 Design Studio should be used The readme file will tell us which version of S32 Design Studio the project was created. For example: the readme in the S32K144_EVB_JumpStart_Firmware package shows that the project for S32K14x EVB JumpStart SW was created in S32 Design Studio for ARM v2.0. created in S32 Design Studio for ARM v2.0.png Which version of SDK should be used You may get the Validation of S32K144_EVB_JumpStart_Firmware Kinetis SDK project when import the project : The project S32K144_EVB_JumpStart_Firmware was created for Kinetis SDK SDK_S32K14x_08 which is not installed in this product (repository SDK_S32K14x_08 not found).  S32K144_EVB_JumpStart_Firmware SDK_S32K14x_08.pngThe chapter Version Tracking of S32SDK_for_S32K1xx_RTM_3.0.3_ReleaseNotes shows that the SDK_S32K14x_08 means EAR 0.8.5. Version Tracking S32SDK_for_S32K1xx_RTM_3.0.3_ReleaseNotes.pngBy default only S32 SDK EAR 0.8.4 is installed in S32DS for ARM 2.0, so we need to update the S32 Design Studio for Arm® v2.0 Update 2 – S32 SDK 0.8.5 EAR & MQX by refer S32 Design Studio for Arm v2.0 - Update 2 available S32DS_ARM_v2.0_UP2_K14x_SDK_085_MQX_170928.png Incorrect UART baud rate setting The baud rate selected for LPUART in Processor Expert is 600 by default, which does not match the description in the readme file. 600 is not in the FreeMASTER serial port baud rate support list, so let us reconfigure the baud rate to 115200 and then click Generate Processor Expert Code. select Baudrate 115200.png Generate Processor Expert Code.pngWhen connect S32K144EVB with FreeMASTER by UART, you can see that the Baud rate 300 is not in the support list. This is the reason why using the default configuration of S32K144_EVB_JumpStart_Firmware is not able to connect with FreeMASTER. Probing UART Ports.png      

Hi,        ARM Cortex-M have a DWT (Data Watchpoint and Trace) unit implemented, and it has a nice feature in that unit which counts the execution cycles. The DWT is usually implemented on most Cortex-M3, M4 and M7 devices, including e.g. the NXP S32K14x.      Attachment is the sample project on S32K142 to measure the running time of a function.     Password of extraction is nxp.     Enjoy the measuring!   Cheers! Oliver BTW, Measure the running time of one function on PowerPC could also be gotten through the link.

This article provides a software package with additional example projects for wakeup use case using RTD6.0.0. All the wakeup example projects mentioned in this page are developed based on RTD, delivered with LLD and HLD.

This example for S32K312 is based on this, example on S32K344 :-- https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-PIT-BTCU-parallel-ADC-FIFO-DMA-DS3-5-RTD300/ta-p/1732444 *******************************************************************************  The purpose of this demo application is to present a usage of the  ADC_SAR and BCTU IP Driver for the S32K3xx MCU.  The example uses the PIT0 trigger to trigger BCTU conversion list to  perform parallel conversions on ADC0/ADC1. Three ADC channels  are selected to be converted on each ADC:  ADC0: S8 , P0, S8  ADC1: S10, S13, S17  Converted results from BCTU FIFO are moved by DMA into result array.  ADC channel S10 is connected to board's potentiometer.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE Micro * Target: internal_FLASH ******************************************************************************** Set PIT Freeze Enable :--- Dinesh_Guleria_0-1707202447324.png BCTU will be do the parallel conversion for channel mentioned in BCTU list :-- Dinesh_Guleria_3-1707204479195.png     Dinesh_Guleria_1-1707202600904.png   "NEW DATA DMA enable mask" :-- controls These bit field in MCR register Dinesh_Guleria_0-1707203759290.png     "ADC target mask" :-- It controls "ADC_SEL " bit field in "Trigger Configuration (TRGCFG_0 - TRGCFG_71)" for single conversions you can enable only one instance so the possible values for target mask: 1 (0b001) ADC0 2 (0b010) ADC1 3 (0b100) ADC2| for list of conversions we can enable also parallel con version for example 3 (0b011) parallel conversion of ADC0 and ADC1 The trigger is configured as a list of parallel conversions ADC0, ADC1 in “Adc Target Mask”. List of ADC channels is defined in “BCTU List Items” while order is given by the “Adc Target Mask”: BctuListItems_0 is ADC0, BctuListItems_1 is ADC1 etc.   Dinesh_Guleria_3-1707204011310.png Dinesh_Guleria_4-1707204043898.png   Dinesh_Guleria_2-1707203974137.png Result :-- I connected VDD from board on adc_0_p0 (PTD1 : J412-1)  and adc_1_p2 (PTE0 J412-13). Also POT value on S10 of ADC-1 & ADC-0-VREFH value coming correct & STABLE. Dinesh_Guleria_1-1707330412160.png     Dinesh_Guleria_0-1707330375235.png =========================Using  FIFO-2 ================= Dinesh_Guleria_0-1732514437470.png FIFO-2 Trigger & LIST Index :-- Dinesh_Guleria_1-1732514506589.png Dinesh_Guleria_2-1732514539640.png ADC channel conversion :-- Dinesh_Guleria_3-1732514707504.png

/******************************************************************************** Detailed Description: Example shows possible implementation of multiple ADC conversions using SDK. Here 7 channels are sampled periodically. 2 ADC modules and 2 PDBs are used. ADC0 is configured to sample 3 channels, ADC1 4 channels. PDBs are set to back-to-back mode to perform chain conversion as shown in RM's Figure 46-3. PDB back-to-back chain forming PDB0-PDB1 ring. Within ADC component you need to select ADC input to be measured for each item in configuration list. For ADC0 ch5 External input channel 28 is selected, as it is connected to potentiometer on the EVB. PDB0 is triggered by LPIT ch0 at 500ms rate. Two DMA channels are configured to read result registers from both ADCs. * ------------------------------------------------------------------------------ * Test HW: S32K148EVB-Q144 * MCU: FS32K144UAVLQ 0N20V * Target: Debug_FLASH * EVB connection: UART terminal 115200, 8N1 * Compiler: S32DS.ARM.3.4 * SDK release: S32SDK_S32K1XX_RTM_4.0.3 * Debugger: S32DS ******************************************************************************** Revision History: Ver Date Author Description of Changes 1.0 Feb-21-2023 Petr Stancik Initial version, based on adc_hwtrigger_s32k148 *******************************************************************************/

NXP has ported FreeRTOS SMP (V11.1.0) to the S32K389. Many customers are interested in how to enable the FreeRTOS SMP on the S32K3xx. The demo is implemented as a single project with a single linker file and a single ELF file. Demo SW/HW Environment: 1. S32DS3.6.4 2. RTD7.0 3.SW32K3_FreeRTOS_11.1.0_7.0.0_CD1_HF1_D2511_DesignStudio_updatesite 4. S32K389 EVB  Demo Code Key Features: 1.FreeRTOS SMP is running on the S32K389 with all cores active. 2.DTCM is used as the task stack. 3.The hardware semaphore (SEMA42) is enabled in FreeRTOS. 4.XRDC is enabled so that each core has a unique core ID for semaphore operations. 5.CAN0 runs on Core0, and CAN4 runs on Core2. 6.LPUART11 is used to print debug information. All cores can output their own messages via LPUART11.  Disclaimer: The code is provided as demo code. NXP makes no commitment regarding its quality.  

*******************************************************************************  The purpose of this demo application is to present a usage of the  FS26 watchdog timer refresh using the SBC_FS26 CDD  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * FS26 : CDD 2.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** Please Modify attached code, and add this line of code, in this function Sbc_Wdg_Refresh_Notification  :-- Gpt_StopTimer(GptConf_GptChannelConfiguration_GptChannelConfiguration_0);   Dinesh_Guleria_0-1758195360264.png   This change will make the example work for even starting FS26, driver at 6 msec and above. Dinesh_Guleria_0-1758195859088.png   Watchdog type :-- NXP eval boards has ASIL-D FS26 part with challenger watchdog. The OTP of FS26 on the board uses challenger watchdog. Dinesh_Guleria_0-1756718067313.png Change watchdog in code :-- FS26 watchdog is started in disabled mode (means infinite period). Later on we change the watchdog time in the code :-- Dinesh_Guleria_1-1756718132100.png   Dinesh_Guleria_2-1756718767003.png   Array Index for watchdog refresh timing  :-- Dinesh_Guleria_3-1756718995126.png Example will run once you press switch USER_SW0 connected on PTB26 on the Evaluation board :-- Please add this type of check in your code, during development process so that, avoid any error due to FS26 watchdog mis trigger. When you use Debug FLASH then in that case code goes to flash memory & can cause your MCU to frequent RESET, which caused issue for reprogramming the NEW firmware on the board FLASH memory. If we add this type of check then we can avoid the Faulty FS26 Software to stop misbehaving before flashing new firmware on the board.   Dinesh_Guleria_0-1756719751273.png In CDD-2.0.0, FS26 goes to INIT_FS state here  :--- Sbc_fs26_InitDevice() --> Sbc_fs26_CheckStateAndGotoInitFS() Dinesh_Guleria_0-1756801397854.png   In CDD-2.0.0, If we start the Watchdog in enabled mode, watchdog notification function to refresh watchdog is called from this function  :-- Sbc_fs26_InitDevice() --> Sbc_fs26_NormalFSSequence() -->  Dinesh_Guleria_1-1756801468887.png   Dinesh_Guleria_2-1756801505399.png   Dinesh_Guleria_4-1756801794626.png In CDD 2.0.0, Following function call will exit Debug mode & Release FS0b & FS1B pin :-- Sbc_fs26_InitDevice() --> Sbc_fs26_NormalFSSequence() :--- --> Sbc_fs26_ExitDebugMode() --> Sbc_fs26_ReleaseSequence() Dinesh_Guleria_5-1756801976481.png   In CDD 2.0.1, Following function call will exit Debug mode & Release FS0b & FS1B pin :-- Sbc_fs26_InitDevice() --> Sbc_fs26_NormalFSSequence() --> Sbc_fs26_ExitDebugMode() Dinesh_Guleria_6-1756802067148.png ===================== CDD-2.0.1 example ================= RTD used :-- S32K3XX_AASW_4_7_RTM_FS26_2_0_1_DS_updatesite_2311_signed.zip Watchdog started in the Disabled mode (i.e infinite Period) then watchdog period is changed in the code main() function :-- Dinesh_Guleria_0-1757654029498.png Dinesh_Guleria_2-1757654310161.png   Driver configuration :-- Dinesh_Guleria_1-1757654073235.png   These function get executed :--   Dinesh_Guleria_4-1757654554696.png   Dinesh_Guleria_5-1757654594171.png   Dinesh_Guleria_6-1757654613589.png One bug in RTD   ---> S32K3XX_AASW_4_7_RTM_FS26_2_0_1_DS_updatesite_2311_signed.zip :-- Dinesh_Guleria_7-1757655145135.png RTD driver Bug is corrected like this :--  Dinesh_Guleria_8-1757655226962.png  

*******************************************************************************  The purpose of this demo application is to present a usage of the  UART IP Driver for the S32K3xx MCU.  The example uses LPUART6 for transmit & receive five bytes using the DMA.  ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 * MCU: S32K344 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** Dinesh_Guleria_0-1718197381145.png   Dinesh_Guleria_1-1718197381161.png   Putty output :-- Dinesh_Guleria_2-1718197434242.png  

*******************************************************************************  The purpose of this demo application is to present a usage of the  ADC_SAR IP Driver for the S32K3xx MCU.  The example uses the PIT0 trigger to trigger  conversions on ADC1.  ADC channels  are selected to be converted on  ADC-1:  ADC channel S10 is connected to board's potentiometer. #define ADC_SAR_USED_CH_BANDGAP 48U /* Internal Bandgap Channel */ #define ADC_SAR_USED_CH_POT_0 34U  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** Dinesh_Guleria_0-1705393272443.png   Dinesh_Guleria_1-1705393287863.png Dinesh_Guleria_2-1705393446888.png    

******************************************************************************** * Detailed Description: * * FlexIO module is configured for UART RX and TX function. * Timer 0 and Shifter 0 is used for UART TX function. * Timer 1 and Shifter 1 is used for UART RX function. * Timer 2 is used for idle detection. * Baud rate = 115200 * HW connection: PTA0 - TX, PTA1 - RX, PTA7 is used to signalize idle detection. * Connect PTA0 and PTA1 to create external loopback for this test. * ------------------------------------------------------------------------------ * Test HW: S32K144EVB * MCU: FS32K144HAMLL 0N57U * Fsys: 80MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH ********************************************************************************

******************************************************************************************************* * Detailed Description: * DCF Record decouples CM7_0 and CM_1 on S32K344 * Find first available location in UTEST. * By default, first available address is 0x1B000768U * * NOTE: There is a bug in the RTD version. * Change FLS_MAX_VIRTUAL_SECTOR to 528 in C40_Ip_Cfg.h * ------------------------------------------------------------------------------ * Test HW: : S32K344EVB-Q257 * MCU: : S32K344 * Project : RTD AUTOSAR 4.7 * Platform : CORTEXM * Peripheral : S32K3XX * Dependencies : none * Autosar Version : 4.7.0 * Autosar Revision : ASR_REL_4_7_REV_0000 * Autosar Conf.Variant : * SW Version : 4.0.0 * Build Version : S32K3_RTD_4_0_0_P20_D2403_ASR_REL_4_7_REV_0000_20240315 *******************************************************************************************************

*******************************************************************************  The purpose of this demo application is to present a usage of the  UART IP Driver for the S32K3xx MCU.  The example uses LPUART6 for transmit & receive five bytes using the Interrupt.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** Dinesh_Guleria_0-1709212154702.png   Dinesh_Guleria_1-1709212155113.png   Dinesh_Guleria_2-1709212171004.png  

Symptoms Recently found the compatibility issue is a troublesome problem especially when we are supporting different version of RTD. Remove/install the RTD SDK and plug, but it is not a perfect way because reinstall the RTD would cause a lot of time, sometimes it is unreliable. Diagnosis After investigated the mechanism of CT and MEX file, and found a work around to let the old project can be run in new version of RTD basis. Solution Already tested it with several reference code and examples of RTD, it can work. Attached is the document.

*******************************************************************************  The purpose of this demo application is to present a usage of the  POWER & WKUP IP Driver for the S32K3xx MCU. In current example :-- SW-6 = PTB-19 -----> PRESS to enter the STANDBY mode. SW-5 = PTB-26 = WKUP[41] --> PRESS to exit the STANDBY mode. CAN-0-RX = PTA-6 = WKUP[15] --> send CAN message to exit the STANDBY mode. The example uses PIT-0 timer, to generate the periodic interrupt. The example uses FLEXCAN-0 for transmit & receive using following Message buffer :-- #define RX_MB_IDX_0 10U #define RX_MB_IDX 11U #define TX_MB_IDX 12U BAUDRATE : 500 KBPS  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************   Dinesh_Guleria_0-1718885427589.png   Push button :-- Dinesh_Guleria_1-1718885710580.png   Dinesh_Guleria_2-1718885752727.png Wake-up source, CAN-0-RX :-- According to the IOMUX table in RM, for example, PTA6 can be used as WKPU15 and CAN0_RX. It means that the WKPU15 input doesn't require specific MSCR configuration. So if its input buffer is enabled and the corresponding WKPU input channel is enabled/configured in the WKPU, it should be able to act as wake-up input. Dinesh_Guleria_3-1718885882871.png Wake-up source, SW-5 GPIO:-- Dinesh_Guleria_4-1718885972993.png Standby entry :-- Dinesh_Guleria_0-1721374048540.png   STandby clock :-- Dinesh_Guleria_1-1721374133669.png Enter Standby mode :-- Dinesh_Guleria_2-1721374180467.png  

This post presents two complementary FlexCAN communication examples for the S32K3X4EVB-T172 evaluation board, showcasing both low-level IP layer and AUTOSAR MCAL layer implementations. These examples are basic routines for configuring the component in normal/user mode, as the RTD examples are configured for loopback mode. To test CAN communication, another board or a CAN analyzer must be used. Since Rev. B2 of S32K3X4EVB-T172 was used to test the project, TJA1043 transceiver is mounted on the board and used to test the examples. ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 * MCU: S32K344 * Compiler: S32DS 3.6.2 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH ------------------------------------------------------------------------------ Example 1: FlexCAN IP Layer (LLD) This project demonstrates a basic FlexCAN setup using the IP-level driver. It configures a standard CAN message; with transmission through POLLING and reception using INTERRUPT. If TJA1153 transceiver is used, macro TJA1153 must be uncommented at the top of the project, and it will be initialized through a custom configuration sequence. If not used and the macro is commented, normal transceiver initialization is done (only CAN0_EN_PIN & CAN0_STB_PIN set to HIGH). Rx Filter mask type is individual and set to receive STD ID 123h.  Tx MB is set to STD ID 001h. FlexCAN bitrate was calculated with MPC5xxx/S32Kxx/LPCxxxx: CAN / CAN FD bit timing calculation. FlexCAN bitrate settings are 500kbps with 81.25% sample point  FPE_CLK: 24MHz Synch seg: 1 Prop seg: 4 Phase 1 seg: 8 Phase 2 seg: 3 Prescaler: 3 RJW: 3    Example 2: FlexCAN MCAL Layer (HLD) This project configures both Can_43_FLEXCAN and CanIf modules for CAN communication. Transmission is done via POLLING, while reception is configured via INTERRUPT.  Tx MB is set to STD ID 123h. Acceptance mask is set to 0x0 (accept all IDs). CAN messages are sent using Can_43_FLEXCAN_Write() and received using the CanIf_RxIndication() callback. After CanIf_bRxFlag is set, an ACK message is sent back. The GREEN LED toggles every 10 received messages. FlexCAN bitrate was calculated with MPC5xxx/S32Kxx/LPCxxxx: CAN / CAN FD bit timing calculation. FlexCAN bitrate settings are 500kbps with 81.25% sample point  FPE_CLK: 24MHz Synch seg: 1 Prop seg: 4 Phase 1 seg: 8 Phase 2 seg: 3 Prescaler: 3 RJW: 3  If TJA1153 transceiver is used, macro TJA1153_EVB_TRCV must be used. If not, use TJA1043_EVB_TRCV for standard transceiver initialization (CAN0_STB & CAN0_EN pins set to HIGH).    PCAN-View configuration   PCAN-View message logs     These examples are provided as is with no guarantees and no support. These are basic routines meant to be used as reference only.

******************************************************************************************** * Test HW: S32K312 EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE Micro * Target: internal_FLASH ******************************************************************************************** The objective of this demo application is to generate an interrupt by comparing DAC internal reference voltage against any analog input which is connected in analog mux input channels(IN0 : IN7). In this demo code,            1)LPCMP0 is used - DAC output is  given to comparator minus (INM) and                                                      AIN2 is given to comparator plus (INP).                From S32K3 RM, highlighted the channels used for reference.                Green color represents DAC, Pink color represents AIN2 which is selected from PMUX          2) From S32K RM,                "Compares two analog input voltages applied to INP and INM,                   COUT_RAW is high when the INP input voltage is greater than the INM input voltage,                   COUT_RAW is low when the INP input voltage is less than the INM input voltage"                So in this demo code,                RED LED is ON , if AIN2 Voltage > DAC Internal reference voltage(COUT is HIGH)                GREEN LED is ON, If AIN2 Voltage < DAC Internal reference voltage (COUT is LOW)   Modules used: LPCMP_ModulesUsed.png          Modifications in LPCMP module: LPCMP_CMP_modifications.png LPCMP_CMP_Modifications2.png   Modifications in IntCtrl_IP module: LPCMP_INTCtrl_IP_Modifcations.png Modifications in the "Cmp_Ip_IrqHandler" function in "Cmp_IP.c" source file: Note: Not sure how it got missed or from where to get COUT status, so added manually to get COUT status from CSR register in the Cmp_Ip_Irqhandler once code generation is completed. LPCMP_IRQHandler_codeChange.png GPIO selection details: LPCMP_PinSelectionDetails.png How to test ? a) Connect jumper wire at the PTC2 in the EVB as highlighted in EVB below. b) RED LED ON -> Jumper wire connects to 5V      GREEN LED ON-> Jumper wire connects to GND Connect male jumper wire at PTC2 Thanks & regards, Krishnakumar V

******************************************************************************* The purpose of this demo application is to present a usage of the Hardfault handling for the S32K3xx MCU. ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** An example on S32K312: Read an unimplemented memory (0x80000):   volatile uint32_t read = *((uint32_t*)0x00080000); Hardfault will occur :-- Dinesh_Guleria_7-1707886997375.png   Dinesh_Guleria_8-1707887021604.png Dinesh_Guleria_0-1707887578380.png   Read Stack pointer when the HARDFAULT occur :-- SP = 0x2000ffd0 Dinesh_Guleria_0-1707886133591.png Go to this memory location , 0x2000ffd0 :-- Dinesh_Guleria_1-1707886185039.png   Dinesh_Guleria_2-1707886314115.png   When the program enters an exception handler, the stack frame is pushed onto the stack including the program counter value of the fault instruction.  At exception entry, the processor saves R0 R3, R12, LR, PC and PSR on the stack. Dinesh_Guleria_3-1707886498124.png hardfault occurred at, 0x00400e48, this is how to decode the address :-- Dinesh_Guleria_5-1707886661636.png   Dinesh_Guleria_2-1707886314115.png Now How to reach this address 0x00400e48, using disassembly window :-- This is same place in main() function :-- volatile uint32_t read = *((uint32_t*)0x00080000); Dinesh_Guleria_6-1707886853788.png  

*******************************************************************************  The purpose of this demo application is to present a usage of the  FlexCAN IP Driver for the S32K3xx MCU.  The example uses FLEXCAN-0 for transmit & receive Tusing following Message buffer :-- #define RX_MB_IDX 1U #define TX_MB_IDX 0U. BAUDRATE : 500 KBPS  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** Dinesh_Guleria_0-1705387677471.png    

******************************************************************************** * Detailed Description: * CM7_0 starts CM7_2 using Power_Ip or directly in MC_ME (macro USE_RTD_POWER_IP). * Disconnect the debugger and power-cycle the MCU. * * ------------------------------------------------------------------------------ * Test HW: S32K3x8EVB-Q289 * MCU: S32K358 * Debugger: S32DS_ARM_3.5, S32K3_RTD_4_0_0_P24_D2405 * Target: internal_FLASH ******************************************************************************** Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.

*******************************************************************************  The purpose of this demo application is to present a usage of the FEE MCAL Driver for the S32K3xx MCU. This example read & write 4 byte FEE BLock. I have renamed the FEE block using a MACRO as FOUR_BYTE_EEPROM_FEE_VARIABLE.  ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** Driver configuration :-- Dinesh_Guleria_0-1733384979032.png   Three FEE blocks are created. Each FEE block can be considered as EEPROM variables  Dinesh_Guleria_0-1716468945422.png   How customer can use FEE block as EEPROM variable. Max size of FEE block :-- Dinesh_Guleria_0-1716470050164.png     You can declare a MACRO for the Variable of EEPROM :-- FOUR_BYTE_EEPROM_FEE_VARIABLE Dinesh_Guleria_1-1716469421192.png How to Read and write the FEE variables :-- Dinesh_Guleria_2-1716469771263.png