ADC Module clock is ideally the CORE clock :--
Dinesh_Guleria_0-1732083693587.png
Dinesh_Guleria_1-1732083711398.png
Prescaler In S32DS is this MCR[ADCLKSEL]) :--
Dinesh_Guleria_2-1732083809064.png
See below snippet from specs for calculation of ADC conversion clock :--
- ADC is controlled by one clock signal, the module clock.
- Internally, the conversion circuit is controlled by the conversion clock, which is derived from the module clock.
- You must configure the ADC conversion clock divider (MCR[ADCLKSEL]) so that the frequency of the conversion clock is within allowed limits.
Dinesh_Guleria_3-1732083835789.png
Dinesh_Guleria_4-1732083835803.png
S32K3 Datasheet, ADC MAX MIN clock limit :--
Dinesh_Guleria_5-1732083946772.png
