********************************************************************************************** * Detailed Description: * CMU_FM minimum reference count requirement: * RCCR[REF_CNT]_MIN = CEILING(MAX(3 * (f_reference_clock / f_bus_clock), * 8 + 5 * (f_reference_clock / f_monitored_clock))) * where: * f_reference_clock = FXOSC clock frequency * f_bus_clock = AIPS_SLOW_CLK frequency (40 MHz) * f_monitored_clock = metered clock frequency * * CMU_1 * ----- * FIRC clock frequency (fmonitored) = 48 MHz * FXOSC clock frequency (fref) = 16 MHz * * 3 * (fref / fbus) = 3 * (16 / 40) = 1.2 * 8 + 5 * (fref / fmonitored) = 8 + 5 * (16 / 48) = 9.667 * RCCR[REF_CNT]_MIN = CEILING(MAX(1.2, 9.667)) = 10 * The first term would dominate only at f_bus_clock < 4.96 MHz, for example. * * CMU_2 * ----- * SIRC clock frequency fmonitored = 32 kHz * FXOSC clock frequency (fref) = 16 MHz * * 3 * (fref / fbus)= 3 * (16 MHz / 40 MHz) = 1.2 * 8 + 5 * (fref / fmonitored) = 8 + 5 * (16 MHz / 32 kHz) = 2508 * RCCR[REF_CNT]_MIN = CEILING(MAX(1.2, 2508)) = 2508 * * * SR_FMTO (Frequency Meter Time Out): * --------------------------------------------------------------------- * FMTO could theoretically be triggered by configuring RCCR[REF_CNT] * to a value lower than the minimum number of reference clock cycles * required to observe one full monitored clock period. * This however cannot be guaranteed by NXP as the value is lower then RCCR_MIN. * NXP guarantees the MCU functionality only if RCCR > RCCR_MIN * When SR_FMTO is set, the SR_FMC is never set, and therefore the CMU_FM interrupt is never called. * * CMU_FM_1: * RCCR[REF_CNT] < f_FIRC / f_FXOSC < (48 MHz / 16 MHz) < 3 * CMU_FM_2: * RCCR[REF_CNT] < T_SIRC / T_FXOSC < 31.25 µs / 62.5 ns < 500 * * * POR_WDG: * --------------------------------------------------------------------- * In case CMU_FM_1 ISR is not executed within POR_WDG timeout, the MCU is reset by the POR_WDG. * Read DCMROPP1-4 * To inject this reset, select CMUFM_1_POR_WDG = 1 and CMUFM_1. * ------------------------------------------------------------------------------------- * MCU: S32K344 * FX_OSC: 16MHz * RTD: S32K3_RTD_7_0_1_D2602_ASR_REL_4_9_REV_0000_20260206 * Debugger: Lauterbach Trace32 * Target: Internal_FLASH **********************************************************************************************

This example project will show user how to use and configure the basic functionalities of WKPU + SIUL2 (GPIO) for wake-up from Standby mode on the S32K358 MCU, with RTC time preservation across Standby and functional reset clock sourced through SIRC. Test HW: FRDM-A-S32K358 / S32K3X8EVB-Q289 MCU: S32K358 IDE: S32DS v3.5 & S32DS v3.6.x SDK release: RTD 6.0.0 Debugger: PE Micro Target: internal_FLASH This example routine configures the WKPU unit for GPIO interrupt wake-up using pins PTH1 (WKPU0) and PTH3 (WKPU15). RTC time is preserved across Standby via the VDDBY supply domain. After wake-up, the functional reset clock is sourced from SIRC before transitioning to the main PLL. No fast wake-up path is used. The routine waits for SW5 to be pressed, then turns off the green LED, and enters Wkpu_EnterStandby() function which: Switches core clock to FIRC. Initializes the WKPU instance. Configures WKPU0 (PTH1) and WKPU15 (PTH3) as wake-up sources. Enters Standby mode (normal wake-up). After pressing USER0/SW4(PTH1), MCU wakes up, resets and polls for USER1/SW5 (PTH3)  or USER0/SW4(PTH1) to be pressed again. Terminal output Settings: 115200 baud — 8 data bits — No parity — 1 stop bit — No flow control (LPUART6) The terminal interaction follows three distinct phases each cycle: boot/wake-up banner → SW6 to read RTC time → SW5 to enter Standby. A representative session is shown below. 1 — Initial power-on (cold start) RTC Standby example, press SW5 to enter standby......... Press SW6 to print RTC date & time......... Reset reason: 15 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 0 seconds 0 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 0 seconds 2 2 — Enter Standby → Wake-up → RTC time preserved MCU will enter standby........ RTC Standby example, press SW5 to enter standby......... Press SW6 to print RTC date & time......... Reset reason: 28 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 0 seconds 13 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 0 seconds 14 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 0 seconds 14 3 — Multiple Standby cycles (RTC keeps incrementing) MCU will enter standby........ RTC Standby example, press SW5 to enter standby......... Press SW6 to print RTC date & time......... Reset reason: 28 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 0 seconds 59 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 1 seconds 0 MCU will enter standby........ RTC Standby example, press SW5 to enter standby......... Press SW6 to print RTC date & time......... Reset reason: 28 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 1 seconds 4 Current RTC date & time: year 1970 month 1 day 1 hour 0 minutes 1 seconds 6 Disclaimer — PTH3 pin on S32K3X8EVB-Q289: The EVB button mapped to PTH3 may fail to trigger a wake-up event. This is caused by the button connected to the VDD_HV_B (3.3 V) rail, while PTH3 belongs to the VDD_HV_A domain, which defaults to 5 V. The signal level mismatch prevents correct wake-up detection. Workaround: switch Jumper J23 from position 1-2 (default, 5 V) to position 2-3 (3.3 V) to align VDD_HV_A with the button voltage level before testing wake-up via PTH3. This example is provided as is with no guarantees and no support.

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* Detailed Description: * Updated the example lwip_FreeRTOS_s32K358 to enable pinging the lwIP stack from the command window * on the board RD-BESSK358BMU * *ping 192.168.0.209 * *Pinging 192.168.0.209 with 32 bytes of data: *Reply from 192.168.0.209: bytes=32 time=2ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 *Reply from 192.168.0.209: bytes=32 time=1ms TTL=255 * *Ping statistics for 192.168.0.209: * Packets: Sent = 4, Received = 4, Lost = 0 (0% loss), *Approximate round trip times in milli-seconds: * Minimum = 1ms, Maximum = 2ms, Average = 1ms * * * RD-BESSK358BMU: * - All jumpers in default positions * - SW2 needs to be ON * * Configuration: * - Updated pin configuration * - Updated GMAC clocks * - IP address set to 192.168.0.209 and enabled UDP_ECHO, etc. * - Eth_43_GMAC: configured for RGMII 1G * - Added DIO * * main.c * - Updated only the header * * device.c * - Added RTD workaround for DCMRWF* registers * * test.c * - Commented out the code that shuts down the TCP/IP stack after its predefined timeout * - Added LED task * * ------------------------------------------------------------------------------------------------ * Test HW: RD-BESSK358BMU SCH-91654 REV B1 * MCU: S32K358 * Debugger: Lauterbach Trace32 * Target: internal_FLASH * EVB connection: RJ45 <-> USB-to-Ethernet adapter <-> Laptop DELL, Windows 11

********************************************************************************************** * Detailed Description: * This example demonstrates the S32K344 internal flash UTest (User Test) sequence using the * Mem_43_INFLS AUTOSAR driver. It covers Array Integrity Check (MISR-based) and User Margin * Read Check, exercised over the full configured Block 3 address range (starting at * 0x00700000), as defined in the Mem_43_INFLS instance configuration. * * Setup: * ProgramBlock3() erases one sector (8 KB) at 0x00700000 and programs the first 512 bytes * with a sequential byte pattern (0x00..0xFF repeating). The remainder of the block * contains erased cells (0xFF). The UTest operations in Steps 1–3 are performed over the * entire Block 3 — not only the 512 programmed bytes. * * Step 1 — Array Integrity Check, Golden MISR Capture: * Runs the Array Integrity Check at NORMAL read margin using sequential addressing over * the full block. UM0–UM9 are seeded with 0xA5A5A5A5. MisrExpectedValues is intentionally * set to 0x0, so JOB_FAILED is the expected outcome. A custom wait function polls the AID * bit directly (without calling Mem_43_INFLS_MainFunction) so that the UM registers are * read before the driver clears them on job completion. The captured MISR becomes the * golden reference (goldenMisr) for Steps 2 and 3. * GETSTATEUTEST_JOB is called afterward to confirm no real hardware fault occurred * (ECC error, breakpoint, or suspension) during the capture run. * * Step 2 — Array Integrity Check, Verification Run: * Re-runs the identical Array Integrity Check over the full block (same seed, same * sequential addressing) with MisrExpectedValues = goldenMisr captured in Step 1. * JOB_OK confirms flash content is unchanged; JOB_FAILED indicates corruption. * GETSTATEUTEST_JOB is called to verify clean hardware completion. * * Step 3 — User Margin Read Check, Cell Margin Verification: * Re-reads the full block at a tighter read margin (C40_IP_MARGIN_LEVEL_PROGRAM). * Same seed and goldenMisr are used. If all cells retain sufficient voltage margin at * the tighter threshold, the MISR matches and JOB_OK is returned. A JOB_FAILED result * indicates one or more cells are degrading before they produce a detectable ECC error * under normal read conditions. * Note: both Array Integrity Check and User Margin Read Check must use sequential * addressing (C40_IP_SEQUENTIAL) to produce a comparable MISR signature. * * Results are accumulated in the utestResults structure (Utest_TestResultType), recording * both the MISR job outcome (Utest_JobResultType) and the hardware UTest state * (Utest_HwStateType) for each step independently. * * NOTE: This example must be executed from SRAM. The Mem_43_INFLS UTest operations * (Array Integrity Check, User Margin Read Check) place the internal flash controller * in UTest mode, during which the flash array is not available for normal read access. * ------------------------------------------------------------------------------------- * MCU: S32K344 * FX_OSC: 16MHz * RTD: S32K3_RTD_7_0_1_D2602_ASR_REL_4_9_REV_0000_20260206 * Debugger: Lauterbach Trace32 * Target: Internal_FLASH **********************************************************************************************