S32K Knowledge Base

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******************************************************************************* The purpose of this demo application is to present a usage of the MEM_InFls MCAL Driver for the S32K3x1 MCU. The example uses MEM_InFls driver to write 128 bytes to FLASH memory address 0x47_A000 starting of FLS_CODE_ARRAY_0_BLOCK_0_S61. ------------------------------------------------------------------------------ * MCU: S32K310 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ******************************************************************************** Flash end address = 0x480000 Size of each block = 8192 = 0x2000 Start Address of 63 block = 0x480000 - 0x2000 = 0x47E000 = 4710400 Start Address of 62 block = 0x480000 - 0x4000 = 0x47C000 = 4702208 Start Address of 61 block = 0x480000 - 0x6000 = 0x47A000 = 4694016 Ram location where FLASH writing erase code is placed :-- I placed the code at 0x256 byte below the MAX address of the RAM size 16*1024 = 16384 = 0x4000 End of RAM = 0x20400000 + 0x4000 = 0x20404000 0x20404000 - 0x256 = 0x20403DAA 0x20403DAA = 541081002 Size of RAM need to save the flashing routine, as per the MAP & linker file :-- 0x00407b80 - 0x00407b54 = 0x2C = 44 byte S32K3 FLASH Memory Terminology :--

****************************************************************************************************** * Detailed Description: These demos showcase how to configure the eMIOS module on the S32K3 series, highlighting various operational modes and their implementations using the RTD high-level drivers, commonly known as MCAL drivers. The implementations demonstrated in these examples follow the approach outlined in the community thread: S32M27x/S32K3 – eMIOS Usage. * Connections: ******************************************************************************************************* * Test HW: S32K31XEVB-Q100 * MCU: S32K311 * Debugger: S32DS 3.6.2, OpenSDA/ PEmicro Multilink Universal FX * Target: internal_FLASH ******************************************************************************************************* * Important information: The OPWMT channel does not support the notification function. In this mode, the Sn[FLAG] bit is only set upon an AS2 match, which defines the generation of a trigger event within the PWM period. As a result, OPWMT mode cannot support notifications based on signal edges. A bus exception may occur during the execution of Mcl_Init() if the eMIOS clock is not properly enabled. To avoid this issue, ensure that the eMIOS peripheral clock is activated in the configuration settings under: MCU driver → McuModuleConfiguration → McuModeSettingConf → McuPeripheral *******************************************************************************************************

Abstract This example presents an use case for complementary PWM outputs with dead-time insertion and hardware ADC triggering using eFlexPWM, TRGMUX, BCTU, SAR-ADC and DMA modules on S32K39-37-36 series based on the RTD low level API to support diverse application needs. Connections: S32K396-BGA-DC1 -> Pin -> Signal -> Label J62-1 -> PTC30 -> siul2_gpio_94 -> GPIO1_GPT J62-5 -> PTD2 -> pwm_0_a, 2 -> PWM1 J62-6 -> PTD3 -> pwm_0_b, 2 -> PWM2 J62-30 -> PTD24 -> pwm_0_a, 0 -> PWMT J62-2 -> PTC31 -> siul2_gpio_95 -> GPIO3_BTCU_Trigger J62-4 -> PTD6 -> siul2_gpio_102 -> GPIO4_BTCU_Watermark J62-24 -> PTB14 -> adc1_s21 -> ADC1 *To use the potentiometer of S32X-MB connect: J62-24 (in S32K396-BGA-DC1) to P26-1 (in S32X-MB) Note: Following line should be added in project/generate/src/Bctu_Ip_PBcfg.c every time the code is updated in Config Tools: #define DMA_LOGIC_CH_0 ((uint8)0U) Detailed Description: The Compare Value of GPT eMIOS 0 channel 0 generates a time-out period. Once time-out is reached its eMIOS notification toggles GPIO1. This allows us to observe in scope 2 events, which describe the start and the end of the signal sequence. The eFlexPWM0 module is used for generating PWMs and hardware ADC triggering. The eFlexPWM0 Submodule 2 is employed to generate center-aligned complementary PWM outputs (PWM1 and PWM2) with dead-time insertion. The eFlexPWM0 Submodule 0 generates another independent PWM output (PWMT) and is utilized to generate the trigger signal for analog data capturing within the same PWM period —happens at half the time high in this case—using VAL0 register. The BCTU implements a list for parallel conversions using ADC0 and ADC1. Which is triggered by the eMIOS channel, and the resulting data is stored in FIFO1, as follows: • ADC0: VREFH_ChanNum51 -> BANDGAP_ChanNum48 • ADC1: VREFL_ChanNum50 -> S21_ChanNum45 For debugging purposed the GPIO3 is toggled every BCTU Trigger Notification. Additionally, the GPIO4 is toggled in BCTU Watermark Notification, which happens every time the number of active entries in FIFO exceeds the watermark level, and therefore the data is available for reading. See full signal sequence in Figure 1: Figure 1. Signals of example project When you suspend debug session, in Expressions tab (Figure 2) you can observe results: g_fifo1Result, which corresponds to the BCTU list measurements, meanwhile g_fifo1Volts corresponds to the conversion in volts. Figure 2. Expressions tab of example project References S32 Design Studio for S32 Platform Real-Time Drivers (RTD) S32K39, S32K37 and S32K36 Data Sheet [S32K39-S32K37-DS] S32K39, S32K37, and S32K36 Reference Manual [S32K396RM] S32K344 to S32K39/S32K37 Migration Guide [AN14301] S32K39/37/36 Electrification Microcontrollers Evaluation Board [S32K396-BGA-DC1] S32X-MB I/O Extension Evaluation Board for Real-Time Domain Control and Actuation [S32X-MB] S32K39-37-36 – eMIOS/BTCU/SAR-ADC/DMA – [RTD600] [S32K Knowledge Base] Application Software: - S32K396_RTD600_eFlexPWM_TRGMUX_BCTU_SARADC_DMA Example was built and tested using the following IDE and Driver versions: - S32 Design Studio for S32 Platform Version 3.6.3 - S32K3_S32M27x Real-Time Drivers ASR R21-11 Version 6.0.0

The following article is intended to give an example on the use of the FS26 in standby mode with the S32K3 MCU also in standby to get lower consumptions on costumer designs and waking up both through an external wake (EXTWAKE) and the PGOOD SBC signal. Software requirements: The attached codes uses the following SW requirements: S32K3 RTD 4.0.0 HF02 FS26 SBC RTD 3.0.0 HW Requirements: There are a few reworks needed on the EVB in order to make the code work. S32K3X8EVB-Q289 Rev B2: 1.- Remove resistor R2301 and place R2304 instead, this change is because the PTA8 signal has the EXTWAKE option on the user push-button, this allows that when you send a WKPU request from the MCU (with the push-button) what the MCU does when it has PGOOD activated is that it sends an EXTWAKE signal to WAKE1 of the FS26. 2.- Change the J685 jumper position to 2-3, this jumper is the VDEBUG mode. 3*.- Optional: FS26 DS recommend FCCU lines with certain values of resistors on their lines that are not present by default on the S32K3X8EVB-Q289. I've attached the example program on a ZIP file, hope it helps.

*************************************************************************************************************** Detailed Description: Example shows implementation of Analog Comparator ‘45.7.5 Windowed mode (#s 5A & 5B)’ of S32K1XXRM using S32 SDK API. The Comparator is configured to compare analog input 0(AIN0) with half the reference voltage generated with the internal DAC. PDB is used to generate pulse output which is used as sampling windows of CMP block via TRGMUX. PDB period is 5ms, the first 2.5ms WINDOW=1 and the next 2.5ms WINDOW=0. Pdb0PulseOut not only be TRGMUX to Cmp0Sample but also to TrgmuxOut0, so that we are able to observe WINDOW at TRGMUX_OUT0(PTA1) pin. Based on the input from CMP0_IN0 (1kHz external triangle wave) the LEDs light by the following rules: 1) Vin < DAC voltage : RED on, GREEN off 2) Vin > DAC voltage : RED off, GREEN on 3) Unknown state : RED on, GREEN on EVB connection: Signal Function pin S32K144EVB-Q100 WINDOW TRGMUX_OUT0 PTA1 J5.5 2.5ms WINDOW=1 and 2.5ms WINDOW=0 Plus input CMP0_IN0 PTA0 J5.7 Need to connect external 1khz triangle wave COUTA CMP0_OUT PTE3 J1.16 square wave PTC1 PTC1 J5.13 If there is no external triangle wave, a square wave(PTC1) is generated and output to CMP0 (PTA1) * * ------------------------------------------------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: S32K144UAVLL 0N47T * Target: Debug_FLASH * Compiler: S32DS3.4 * SDK release: S32SDK_S32K1XX_RTM_4.0.3 * Debugger: PEMicro OpenSDA * ------------------------------------------------------------------------------------------------------------------------ Revision History: Ver Date Author Description of Changes 1.0 Nov-9-2023 Robin Shen Initial version, based on cmp_dac_s32k144 and pdb_periodic_interrupt_s32k144 ***************************************************************************************************************

Hi team, First let me explain about the code about what it does. ======================================= 1) From POR, LED starts blinking - In this state RTC won't be initialized. 2) Once SW5 is pressed in S32K312 EVB - RTC will be initialized before MCU goes to sleep. 3) RTCCNT will be incrementing during sleep 4) Once SW6 is pressed , MCU wakes from the sleep and we could able see the updated RTC time and date. WAR(Work Around)done to keep RTC alive during sleep: ======================================= Tried to test the RTC with sleep mode, observed that RTCCNT value is getting reset once after every wakeup. So that time and date was not able to preserve the value. In order to avoid this, I have done two workarounds to solve this RTCCNT value reset issue. 1) RTC will not be initialized for if MCU wakeup from the sleep - Made the check to initialize when MCU is not from the wakeup before it goes to sleep. wake_up_event will be incremented if MCU reset reason is wakeup as shown below. 2) Updating "Rtc_Ip_u32ChState" array variable for "ticksPerSecond" member in "Rtc_Ip.c" file manually after the code generation is completed. Note: With auto generated code the value of "ticksPerSecond "will be "0". Any other alternatives other than this approach is highly appreciated. Thanks in advance!

This document provides a brief explanation of the Excel-based calculator developed to assist with the computation of TX Arbitration Start Delay as described in the S32K3 reference manual. The tool implements the formula provided in the datasheet, allowing users to input relevant parameters and automatically calculate the delay values. It is intended to support engineers in evaluating CAN transmission timing and optimizing arbitration performance in S32K3-based applications. 1.Fill in the clock and CBT and FDCBT configuration parameters according to your requirements. For example, we fill the parameters according Case 3: Then we can get the TASD value for non-FD frames is 24.05. Please note that this summary is not officially released by NXP. It is a personal summary for reference only. If there are any errors, please contact me.

This post is an additional project to the S32K3 Low Power Management AN and demos. A simple FlexCAN routine is configured for RX/TX and wakeup through the CAN0_RX pin (PTA6/WKPU19). The example is based on the S32K3X4EVB-T172, meaning that transceiver TJA1443 is used. TJA1443 only needs CAN0_EN & CAN0_STB pins in HIGH for normal configuration. In the example, the GREEN led is used to indicate that the MCU is in RUN mode. Once SW5 is pressed, MCU enters low power (STANDBY), and led is turned off. BLUE led toggles each time a CAN frame is received. MCU can be woken up with SW6 (WKPU42) or through a CAN RX. Note that CAN is not enabled in low-power, rather PTA6 (WKPU19) is configured for wake up, and once a rising edge signal is detected on the pin, MCU wakes up and reconfigures CAN module. ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-T172 * MCU: S32K344 * Compiler: S32DS3.6.2 * SDK release: RTD 6.0.0 * Debugger: PE Micro * Target: internal_FLASH ------------------------------------------------------------------------------ This example is provided as is with no guarantees and no support.

This example code brief :-- 1> Tested without the SL of BMS, so no dependency on the BMS Safety library. 2> Its tested on 2 AFE MC33775 board connected in TPL 3> Change following macro in mc33775_cfg.h file to change the numbers of AFE connected in TPL. RTD : 3.0.0 P07 BMS SDK : 1.0.2 This example does this task :-- Application Measurement. SYNC measurement Periodic Measurement. Read AFE temperature. Cell balancing timer method. Reading the Cell balancing status register & fault registers. =================== Setup used ============ Attached code is tested with TWO MC33775 AFE connected in TPL mode. =============== MCU Pins used =========== FRDM665SPIEVB Jumper setting :--- K1, K2 & K4 connector of S32J344 EVB :-- K1 on MC33665 & S32K334 evb :-- K2 on MC33665 & S32K334 evb :-- K4 on MC33665 & S32K334 evb :-- ================= EVB Link ================== https://www.nxp.com/design/design-center/development-boards-and-designs/18-cell-battery-pack-emulator-to-supply-mc33774-bcc-evbs:BATT-18EMULATOR https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM665SPIEVB https://www.nxp.com/design/design-center/development-boards-and-designs/RD33775ADSTEVB https://www.nxp.com/design/design-center/development-boards-and-designs/automotive-development-platforms/s32k-mcu-platforms/s32k3x4evb-t172-evaluation-board-for-automotive-general-purpose:S32K3X4EVB-T172 ============= Using Debugger ============ Debugger breakpoint will cause the communication timeout at the AFE, which will RESET the AFE. To use the debugger while development you need to disable the communication timeout. In S32DS MEX file you cannot disable the timeout function ( limit the value of 0~255) Disable Communication timeout in code :-- ================= Results for TWO AFE ===========================

------------------------------------------------------------------------------ * Test HW: S32K31XEVB-Q100 * MCU: S32K311 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE Micro * Target: internal_FLASH ******************************************************************************** S32K31XEVB-Q100 :-- S32K31XEVB-Q100 Evaluation Board for Automotive General Purpose | NXP Semiconductors Example MCAL S32K311 MEM_InFls DS3.5 RTD300 :-- Example MCAL S32K311 MEM_InFls DS3.5 RTD300 - NXP Community

******************************************************************************** The purpose of this demo application is to show you how to use the Temperature Sensor module in S32DS. It includes two methods to obtain temperature. -The first one starts a normal software conversion with one-shot mode on temp sense channel and calculates the temperature on chip from the data conversion. -The second one calculates the temperature based on given data (if read directly using ADC). Note: Please adjust the ADC reference voltage according to the board you are using * ------------------------------------------------------------------------------ * Test HW: S32K344EVB-T172 * MCU: S32K344 1P55A * Compiler: S32DS.ARM.3.5/6 * SDK release: S32K3_RTD_6.0.0/5.0.0/4.0.0_P24 * Debugger: OpenSDA/PE&Micro * Target: internal_FLASH *Jumper:J18-1:2,5V used. ********************************************************************************* Note that if you use "sprintf", you need to check the following option.

**************************************************************************************************** * Detailed Description: * This code demonstrates how to inject an ECC (Error Correction Code) fault into either DTCM0 * (Data Tightly Coupled Memory) or SRAM0 using the EIM (ECC Injection Module). * * When the processor reads corrupted data from DTCM0 or SRAM0, an ECC error is detected, resulting in: * - A Bus Fault exception raised by the core. * - An error report generated by the ERM (Error Reporting Module), which can also trigger an interrupt. * * By default, the ERM interrupt has a lower priority than the Bus Fault exception. In this example, * the Bus Fault exception priority is intentionally lowered so that the ERM interrupt is serviced first. * This ensures the system can respond to the ERM interrupt before the core's Bus Fault handler executes. * * IMPORTANT: The interrupt vector table must not reside in SRAM0 or DTCM0 when injecting an * uncorrectable ECC fault into these memories. Otherwise, the ECC fault would corrupt the vector * table during a fetch, leading to unpredictable behavior. * Always check the VTOR (Vector Table Offset Register) * to confirm the vector table location before performing ECC fault injection. * * Memory Selection: * You can select which memory to inject the ECC fault into using the following macros: * #define SRAM0 * #define DTCM0 *************************************************************************************************** * ------------------------------------------------------------------------------------------------* * Test HW: S32K3X4EVB_Q257 * MCU: S32K344, 0P55A * SDK: NA * Debugger: Lauterbach Trace32 * Target: internal_FLASH ****************************************************************************************************

**************************************************************************************************** * Detailed Description: * * - CMU errors cannot be injected by any means other than manipulating the CMU thresholds, * except for FXOSC_CLK, which can be physically disrupted on the PCB. * * - CMU_FC_0 (FXOSC_CLK) is configured for **synchronous interrupt** on both LFF and HFF CMU events. * - CMU_FC_3 (CORE_CLK) is configured for **asynchronous destructive reset** triggered only by the LFF event; the HFF event is ignored. * - CMU_FC_4 (CORE_CLK) is configured identically to CMU_3: **asynchronous destructive reset** on LFF only; HFF is ignored. * - CMU_FC_5 (HSE_CLK) can be configured by the HSE_B core only. * Refer to the Reference Manual rev.10, Figure 122. Frequency checking (FC) instances * * - The configuration must be identical in both the MCU MCAL driver and the Clock Configuration Tool (clock details). * - To inject a specific CMU error, define one of the following macros: `INJECT_CMU_0`, `INJECT_CMU_3`, or `INJECT_CMU_4`. * * Behavior After Destructive Reset: * - Following a destructive reset (either `MCU_CORE_CLK_FAIL_RESET` or `MCU_AIPS_PLAT_CLK_FAIL_RESET`), * execution will halt in the `while(wait)` loop. * ------------------------------------------------------------------------------------------------ * Test HW: S32K3X4EVB_Q257 * MCU: S32K344, 0P55A * SDK: RTD 6.0.0 * Debugger: PEMicro Multilink FX * Target: internal_FLASH ****************************************************************************************************

*********************************************************************************** * Detailed Description: * The example locks * PFC PFCBLK2_SSPELOCK REG_PROT soft lock * and PFC REG_PROT hard lock. * ------------------------------------------------------------------------- * Test HW: : S32K344EVB-Q172 * MCU: : S32K344 * Project : RTD AUTOSAR 4.7 * Platform : CORTEXM * Peripheral : S32K3XX * Dependencies : none * * Autosar Version : 4.7.0 * Autosar Revision : ASR_REL_4_7_REV_0000 * SW Version : 5.0.0 * Build Version : S32K3_RTD_5_0_0_D2408_ASR_REL_4_7_REV_0000_20241002 ***********************************************************************************

******************************************************************************* The purpose of this demo application is to present a usage of the EMIOS IP Driver in Interrupt mode for the S32K3xx MCU. The example use to :-- EMIOS-1 - ch-0 --> PTC24 --> Generate the PWM EMIOS-1 - ch-1 --> PTC25 --> is the ICU channel to measure the duty Pins used :-- This example is tested for SAIC & IPWM mode both. You can change the mode by this setting in MEX file :-- Difference between SAIC & IPWM, ICU Driver User Manual :-- These Two Macro :-- SAIC_MODE --> this maco will enable variables to store for SAIC mode CUSTOM_IRQ --> this MACRO will enable customized IRQ or RTD available IRQ Result :-- Sometimes Compiling error comes, in Autogenerated RTD file. Change the Header file name :-- ------------------------------------------------------------------------------ * Test HW: S32K3X2EVB-Q172 * MCU: S32K312 * Compiler: S32DS3.5 * SDK release: RTD 3.0.0 * Debugger: PE micro * Target: internal_FLASH ********************************************************************************

************************************************************************************************* * Detailed Description: * DCF record disables or enables POR_WDG depending on the POR_WDG_EN macro in main.c. * Find first available location in UTEST, by default, first available address is 0x1B000780 * * NOTE: There is a bug in this RTD version. * Change FLS_MAX_VIRTUAL_SECTOR to 272 in C40_Ip_Cfg.h * ------------------------------------------------------------------------------ * Test HW: : S32K312EVB-Q172 * MCU: : S32K312 * Project : RTD AUTOSAR 4.7 * Platform : CORTEXM * Peripheral : S32K3XX * Dependencies : none * * Autosar Version : 4.7.0 * Autosar Revision : ASR_REL_4_7_REV_0000 * Autosar Conf.Variant : * SW Version : 3.0.0 * Build Version : S32K3_RTD_3_0_0_D2303_ASR_REL_4_7_REV_0000_20230331 *************************************************************************************************

***************************************************************************** *Detailed Description: *This example will show you how to configure Sbc_fs23 Driver. *It initialization of Sbc_fs23 with watchdog window disabled. The Sbc_fs23_InitDevice() must be done within the dedicated 256 ms INIT window. *It Disable regulator V2, then re-enable it again. FS0b pin is asserted due to V2 Undervoltage reaction setting configured in FailSafe Init Configuration tab. *If the example runs without errors, the D12 LED on S32K31XEVB-Q100 will light up Green; otherwise, it will light up Red. *The SPI data between FS23 and S32K311 are captured and attached to the project. *Use the analog input of a logic analyzer or an oscilloscope to monitor the signals of FS23_V2 (TP27) and FS23_FS0 (TP8) on the KITFS23SKTEVM board. *------------------------------------------------------------------------------ *Test HW: * S32K31XEVB-Q100 Board SCH-55131 REV A P32K311HV 0P98C * KITFS23SKTEVM Dev-kit SCH-53096 REV B2 MFS2320BMBB1EP * My S32K31XEVB-Q100 has an onboard PFS2320A0L1W1, but Step 13/14 of AN14041 mention that A0 devices are not supported, so S32K311 communicate with the FS23 on the KITFS23SKTEVM. *Connections: KITFS23SKTEVM | S32K31XEVB-Q100 ------------------------------|-------------------- SPI_CSB J28-2 | J12-5(PTB-17) SPI_MOSI J29-2 | J12-7(PTB-16) SPI_SCK J31-2 | J12-11(PTB-14) SPI_MISO J32-2 | J12.9(PTB-15) VCC J6-1 | J40-15 GND J6-2 | J40-13 - KITFS23SKTEVM: SW1 - position 2-3 , J30 - ON, J26 5-6 ON, J26 9-10 ON . - Connect KITFS23SKTEVM Dev-kit and S32K3 MCU via on-board Arduino headers. *SDK: * S32K3 RTD 4.0.0 (SW32K3_S32M27x_RTD_R21-11_4.0.0_D2311_DS_updatesite.zip) * FS23 RTD 1.0.0 (S32K3xx_SBC_FS23_R21-11_1.0.0_D2508_DesignStudio_updatesite.zip) *Debugger: S32DS 3.5.8, OpenSDA/ PEmicro Multilink Universal FX *Target: internal_FLASH *Reference Documentation: * AN14041 FS23 quick start guide (Rev. 2.0 — 23 January 2025) * AN14129 FS23 implementation and behaviors (Rev. 2.0 — 13 December 2024) * FS23, Safety System Basis Chip (SBC) with Power Management, CAN FD and LIN Transceivers Data Sheet (Rev. 8.0 — 30 June 2025) * RTD_SBC_FS23_UM.pdf C:\NXP\S32DS.3.5\S32DS\software\PlatformSDK_S32K3\SW32K3_FS23_R21-11_1.0.0_D2312\Sbc_fs23_TS_T40D34M10I0R0\doc * This example is migrated from Sbc_fs23_example_HLD_S32K344. The method of migrating refers to the video "2.S32DS CT MCAL demo porting K344 to K312 based on RTD500": https://community.nxp.com/t5/S32K-Knowledge-Base/S32K3-Tools-Part-How-to-port-RTD-s-existing-MCAL-demo-to-other/ta-p/1966315 ***************************************************************************** * Revision History: * Ver Date Author Description of Changes * 0.0 10-26-2025 Robin Shen Initial version * 0.1 11-21-2025 Robin Shen Upgrade FS23 RTD 1.0.0 from S32K3xx_SBC_FS23_R21-11_1.0.0_DS_updatesite_D2402_updated_D250115.zip to S32K3xx_SBC_FS23_R21-11_1.0.0_D2508_DesignStudio_updatesite.zip *****************************************************************************

S32K Knowledge Base

S32K Knowledge Base

Discussions

Example MCAL S32K310 MEM_InFls DS3.5 RTD300

Example S32K311 eMIOS MCAL S32DS 3.6.2 RTD 6.0.0

S32K39-37-36 – eFlexPWM/TRGMUX/BCTU/SAR-ADC/DMA – [RTD600]

RTD Example FS26 WKUP with PGOOD and EXTWAKE using a S32K3X8EVB

All Example MCAL S32K310 DS3.5 RTD-3.0.0

Example S32K144 CMP Windowed Mode use PDB S32DS3.4 RTM4.0.3

S32K312: RTC- Preserving RTC counter value from getting resets once after every wakeup

S32K3 FlexCAN TASD calculation

[RTD600 IP] S32K3X4EVB-T172 Classic CAN + WKPU

S32K344 + MC33665 + MC33775 : RTD 3.0.0 : BMS SDK 1.0.2

All Example MCAL S32K311 DS3.5 RTD-3.0.0

Example S32K344 TempSenser S32DS36 RTD600/500/400_p24

AUT-T4984 Hands-On Workshop Battery Management System Software Stack, Installation procedure

S32K389EVB Demo Code

Example_S32K344_EIM_ERM_DTCM_SRAM_Baremetal_v3_0_S32DS36

Example_S32K344_MCAL_MCU_ClockMonitor_v1_0_S32DS36_RTD600

Example_Reg_Prot_Flash_Controller_S32K344

Example ASR S32K312 EMIO PWM Generation & Duty capture using Interrupt DS3.5 RTD300

Example_S32K312_DCF_POR_WDG_EN_DS35_RTD300

Example S32K311 SPI Sbc_fs23 MCAL S32DS3.5.8 RTD4.0.0

S32K3 Motor control SW examples