S32K ナレッジベース

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******************************************************************************* * * The purpose of this demo application is to present a usage of the ADC_SAR and * BCTU IP Driver for the S32K3xx MCU. * * The example uses the PIT0 trigger to trigger BCTU conversion list. Five standard * ADC channels are selected to be converted. * Converted result from BCTU data register are moved by DMA into result array. * This result array should be placed into no cacheable area if data cache is enabled. * * ADC channel S10 is connected to board's potentiometer, and converted value is * used to dim board's LED. * * * ------------------------------------------------------------------------------ * Test HW: S32K3X4EVB-Q172 * MCU: S32K344 * Compiler: S32DS3.4 * SDK release: RTD 1.0.0 * Debugger: Lauterbach * Target: internal_FLASH ********************************************************************************

Hi, Firstly, you should get the flash block size of your S32K3xx. Table in RM could be the reference. Secondly, you should know that there are super sector and sector in S32K3xx. Sector Subdivision of the Flash Block that is independently erasable. Sector Size is always 8 KB. Super sector Subdivision of the flash block that includes a group of sectors. Super Sector Size is always 64 KB, and consists of 8 sectors. Thirdly, based on the information of PFCBLKx_SSPELOCK in RM, you can calculate the numbers of super sector and sector in each flash block. For example in S32K312, it has 2MB flash totally and each block is 1MB. So, in each 1MB, its first 768KB is with super sector granularity. The numbers of super sector is 768/64=12; the followed sector number is 256/8=32. Cheers! Oliver

******************************************************************************** * Detailed Description: * * Example shows possible setting for PWM duty cycle update using DMA. * FTM0 ch0 is set to Edge aligned mode with 20KHz period. * Initialization trigger is routed back to HW trigger 1 using TRGMUX, so this HW * trigger can be used for CnV synchronization. * DMA on FTM0 ch0 is enabled (on ch0 CHF flag) and DMA ch0 configured to update C0V * from duty cycle variable. * NOte CHF is not set for 0% and 100% duty cycle, thus no DMA trigger is generated. * * Green LED is dimming as duty is changing. * * ------------------------------------------------------------------------------ * Test HW: S32K118EVB-Q64 * MCU: PS32K118LAMLH 0N97V * Compiler: S32DS.ARM.2.2 * SDK release: S32SDK_S32K1xx_RTM_3.0.3 * Debugger: Lauterbach, OpenSDA * Target: internal_FLASH * ******************************************************************************** Revision History: 1.0 Sep-16-2021 Petr Stancik Initial Version *******************************************************************************/

The purpose of this demo application is to show you the usage of the FlexCAN module configured to use Flexible Data Rate using the S32 SDK API. - In the first part, the application will setup the board clocks, pins and other system functions such as SBC if the board uses this module as a CAN transceiver. - Then it will configure the FlexCAN module features such as FD, Bitrate and Message buffers - The application will wait for frames to be received on the configured message buffer or for an event raised by pressing one of the two buttons which will trigger a frame send to the recipient. - Pressing SW3 button of board 1 shall trigger a CAN transfer that results in toggling the RED led on board 2. - Pressing SW2 button of board 1 shall trigger a CAN transfer that results in toggling the GREEN led on board 2. - This demo application requires two boards, one configured as master and the other one configured as slave (see MASTER/SLAVE defines in application code) or single board connected with CAN tool. - Both the event and error callbacks are installed, callback_test variable indicates event entering bit0 .. RX complete bit1 .. TX complete bit2 .. ERR INT flag set bit3 .. BOFF INT flag set - to enter bus off simply short CANH with GND and send message using either SW1 or SW2, FlexCAN enters bus off (error event) and blue LED is ON. Also TX MB is aborted. Remove short connection and send message again normally, blue LED is off. ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: FS32K1441 0N57U * Compiler: S32DS.ARM.2.2 * SDK release: S32SDK_S32K1xx_RTM_3.0.3 * Debugger: Lauterbach, OpenSDA * Target: internal_FLASH

******************************************************************************** * File: main.c * Owner: David Tosenovjan * Version: 0.0 * Date: Mar-12-2021 * Classification: General Business Information ******************************************************************************** * Detailed Description: * Example code configures the whole 4kB FlexRAM area for SRAM use. * By default or after mass erase, S32K1 device has only address range * 0x1400_0000-0x1400_0DFF (3.5kB) accessible for SRAM use. * To enable remaining 0.5kB it is needed to perform Program Partition Command * (with the setting shown in the example), but only once with the blank new * device (or previously mass erased). It sets up address range * 0x1400_0000-0x1400_0FFF for SRAM use. * ------------------------------------------------------------------------------ * Test HW: S32K146EVB-Q144 * MCU: PS32K146UAVLQ 0N73V QAC1735D * Fsys: default * Debugger: Lauterbach Trace32, OpenSDA * Target: Debug_RAM * Terminal: none * EVB connection: default ********************************************************************************

******************************************************************************** Detailed Description: This example shows SRAM ECC injection. By default, a double-bit ECC error is injected on read access of a location in SRAM_U region. This can be changed with the SRAM_U and DOUBLE_BIT macros. The errors can be detected by both the ERM and MCM modules and the corresponding interrupts can be called. Although only ERM is needed, for demonstration purposes, the MCM interrupt is enabled as well with a lower priority than the ERM interrupts. The ERM interrupts that are called first disable the injection mechanism so that subsequent errors can not be detected during a stack read access. The default S32 Design Studio start_up file copies the vector table to the SRAM_L region. To be able to inject ECC errors in this SRAM region and call the interrupts, the copying is disabled by __flash_vector_table__ symbol declared in the start_up.h file and defined in the S32K144_64_flash linker file. -------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 Target: internal_FLASH ********************************************************************************

******************************************************************************************************* Detailed Description: Configures the MCU to run system clock from XOSC. LPUART1 is set to respond to LIN header sent from master. Based on ID received the LPUART1 either receive frame's data and compare checksum or publish requested data with calculated checksum. Enhanced checksum is used. Interrupt is used for RX and TX operation and 2 versions of interrupt routine are available. VER 1 ... during response transmission receiver disabled and transmit interrupt enabled VER 2 ... during response transmission receiver is kept enabled ------------------------------------------------------------------------------ Test HW: S32K116 EVB-Q048 MCU: PS32K116LAM 0N96V Fsys: 40MHz Debugger: Lauterbach Target: internal_FLASH ******************************************************************************************************

S32Kxxx Excel configurators MPC5xxx/S32Kxx: CAN / CAN FD bit timing calculation S32M24x/S32K1 Documents Solution for S32K14x which could be attached while couldn't be re-programmed Fault handling on S32K144 FRDM-S32K144 EVB Useful tips about S32DS for ARM v2018.R1 IDE and S32K1xx development Using S32K CMSIS-SVD Files in EmbSysRegView Eclipse Plugin FlexNVM used as code/data Flash S32M27x/S32K3 Documents Restrict the debug access with a password when HSE is not used S32M27x/S32K3 – eMIOS Usage S32M27x/S32K3 – eMIOS/BTCU/ADC/DMA – [RTD600] S32M27x/S32K3 – eMIOS/TRGMUX/LCU – [RTD600] S32K39-37-36 Documents S32K39-37-36 – eMIOS/BTCU/SAR-ADC/DMA – [RTD600] S32K39-37-36 – eFlexPWM/TRGMUX/BCTU/SAR-ADC/DMA – [RTD600]

******************************************************************************************************************************************** Detailed Description: This example shows use of RTC in VLPS mode. The MCU is put into the VLPS mode (Sleep-On-Exit). RTC alarm interrupt brings it to VLPR every 3s and toggles BLUE LED (PTD0). Since it works in the Sleep-On-Exit mode, after the ISR, the MCU goes to VLPS again without calling the WFI instruction. When BTN0 (S32K144 EVB) is pressed, the power mode switch from VLPS to VLPR and other way round. Interrupt is triggered on rising edge (PTC12), filtered by digital filter (clocked from LPO). In VLPR, RTC seconds interrupt is enabled as well and toggles RED LED (PTD15) in the ISR. RTC_CLKOUT (1Hz) and CLKOUT (bus_clk) can be monitored at PTD13 and PTD14 respectively. CLKOUT is not available in VLPS. The MCU needs to be power-cycled and run stand-alone. -------------------------------------------------------------------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K 0N57U Debugger: S32DS_ARM_2.2, OpenSDA Target: internal_FLASH ********************************************************************************************************************************************

Welcome to the S32K Microcontrollers forum. Get expert advice from the NXP developer community. Our support team also monitors these forums to provide answers and take your feedback. Anyone can read the discussions, but only registered NXP Community members can post questions and comments. Before you ask a question, please search the community to find if someone has already offered a solution. If you don’t see a solution, then ask the community your question. S32K Web page S32K Reference manual S32K Data sheet S32K Application notes and other documents S32K Evaluation Board S32 Design Studio IDE https://community.nxp.com/docs/DOC-334170

******************************************************************************** Detailed Description: Example shows how to use FlexCAN 0 Pretended networking mode to allow FlexCAN module to wake up MCU from STOP mode using SDK. Wake up by Timeout and wake up by Match events are enabled. Also pin interrupt can be used to exit STOP mode. So MCU enters STOP mode by pressing SW3 button. MCU exits STOP mode when one of following happens: - no CAN message comes in 8sec (CAN PN timeout event) - message with standard ID 0x554 or 0x555 comes (CAN PN match event) - SW2 button is pressed (PTC12 interrupt) In run mode blue LED is dimming and the rate is different for each wakeup event ------------------------------------------------------------------------------ Test HW: S32K116EVB-Q48 MCU: PS32K116LAM 0N96V Compiler: S32DS.ARM.2.2 SDK release: S32SDK_S32K1xx_RTM_3.0.0 Debugger: Lauterbach, OpenSDA Target: internal_FLASH ********************************************************************************

******************************************************************************************** * Detailed Description: * LPIT_ch0 triggers DMA_ch0 periodically (1ms). * Every trigger starts a minor DMA loop (8 bytes) transfer to the LPSPI1 TX FIFO. * There are 8 minor loops per one major loop (64 bytes in 8ms). * LPSPI1 sends two 32bit frames every 1ms. * LPSPI1 RX data are masked, they are not stored in the RX FIFO. * ------------------------------------------------------------------------------ * Test HW: S32K144EVB-Q100 * MCU: S32K144 0N57U * Debugger: S32DS 2.2, OpenSDA * Target: internal_FLASH ********************************************************************************************

******************************************************************************************************** Detailed Description: On WDOG timeout, the WDOG module requests reset in the Reset Control Module (RCM). The reset request to RCM can be delayed by 128 bus clock cycles if the WDOG interrupt is enabled (WDOG_CS[INT] = 1). If enabled, the WDOG interrupt vector is fetched or it becomes pending in NVIC. After the delay, the reset is requested in RCM. Independently of the WDOG interrupt, the RCM can again delay the reset by up to 514 LPO additional clock cycles if the corresponding RCM_WDOG interrupt is enabled (RCM_SRIE[GIE, WDOG] = 1). If so, instead of forcing reset immediately, the module requests the RCM interrupt in NVIC and forces the reset after the additional delay (RCM_SRIE[DELAY]). Either way, the reset is forced, it can’t be stopped only delayed. This example enables the WDOG interrupt in the WDOG_CS register but leaves this interrupt disabled in NVIC. That means that this interrupt becomes pending in NVIC on the WDOG timeout, it sets the WDOG_CS_FLG, but the vector doesn’t get fetched. The RCM interrupt is enabled and it gets asserted in NVIC after the WDOG interrupt delay (2.67us (48MHz BUS CLK)). The WDOG flag (WDOG_CS_FLG) is read in the RCM ISR instead. The execution stays in an infinite loop for 514 LPO (128kHz) cycles (~ 4ms) until the reset is forced. ------------------------------------------------------------------------------------------------------------------------- Test HW: S32K144EVB-Q100 MCU: S32K144 0N57U Debugger: S32DSR1 OpenSDA Target: internal_FLASH ********************************************************************************************************

************************************************************************************************ Detailed Description: WDOG tested in SystemInit() function (system_S32K116.c) after POR. For debugging purposes: - WDOG counter reference clock is pre-scaled to slow the test (CS_PRES = 1). - During CNT_LOW test, BLUE LED (PTE8) ON. - During CNT_HIGH test, RED LED (PTD16) ON. - Once both tests have passed, GREEN LED (PTD15) ON. If either of the test fails, WDOG will stay in its default configuration and rest the MCU. ---------------------------------------------------------------------------------------------------------------- Test HW: S32K116EVB-Q048 REV.B MCU: S32K116 0N96V Debugger: S32DSR1, OpenSDA Target: internal_FLASH ************************************************************************************************

****************************************************************************************************************** Detailed Description: The example code shows CMP in Round-robin mode. CMP is clocked (125kHz) and triggered (80ms) by LPTMR, operates in VLPS. Input channels are CMP0_IN1 (PTA1), CMP0_IN2 (PTC4), CMP0_IN3 (PTE8), CMP0_IN4 (PTC3). The initial state of CMP outputs is 0 (Input analog pins < DAC input (Vin1/2)) The input pins are pulled down internally for debugging purposes. CPM will wake up the MCU if an input has changed. BLUE LED flashes 1x if CMP_IN1 has changed, 2x CMP0_IN2, 3x CMP0_IN3, 4x CMP0_IN4. After that, the MCU goes back to VLPS. ------------------------------------------------------------------------------------------------------------------------------------- Test HW: S32144EVB-Q100X MCU: S32K144 (0N47T) Debugger: S32DS2.0, OpenSDA Target: internal_FLASH ******************************************************************************************************************

**************************************************************************************************** * Detailed Description: * This code injects an ECC (Error Correction Code) error into DTCM (Data Tightly Coupled Memory) * using the EIM (ECC Injection Module). * * When the core reads the corrupted DTCM data, it triggers a fault due to the ECC error: * - A Bus Fault exception is raised by the core. * - The ERM (Error Reporting Module) also detects the fault and can generate an interrupt. * * By default, the ERM interrupt has a lower priority than the Bus Fault exception. * In this example, the Bus Fault exception priority is intentionally lowered so that the ERM * interrupt is handled first. This allows the system to respond to the ERM interrupt before * the core's Bus Fault handler executes. *************************************************************************************************** * ------------------------------------------------------------------------------------------------* * Test HW: S32K3X4EVB_Q257 * MCU: S32K344, 0P55A * SDK: -- * Debugger: PEMicro Multilink FX * Target: internal_FLASH ****************************************************************************************************

特集記事

The S32K3 family of 32-bit AEC-Q100 qualified MCUs combines a scalable family of Arm® Cortex-M7-based microcontrollers built on long-lasting features with a comprehensive suite of production-grade tools. S32K3 MCUs are included in NXP’s Product Longevity Program, guaranteeing a minimum of 15 years of assured supply. The S32K3 offers dedicated peripherals set for rapid motor control loop implementation: enhanced Modular IO Subsystem(eMIOS), Logic Control Unit (LCU), TRGMUX, BodyCross-triggering Unit (BCTU), Analog to Digital Converter(ADC), and Analog Comparator (CMP). The comprehensive motor control ecosystem based on Automotive Math and Motor Control Library(AMMCLib) set, FreeMASTER with Motor Control ApplicationTuning (MCAT) tool and Model-Based Design Toolbox (MBDT) helps to enable S32K3 MCU in wide range of motor control use cases. The table below points to the articles with more detailed description each of S32K3 motor control use cases, hardware description, links to appropriate application notes and their addendums, and software repositories. Device HW Article S32K344 MCSPTE1AK344 12 V development kit engineered for 3-phase PMSM and BLDC motor control applications FOC with dual shunt current measurement Article focuses on solution based Field Oriented Control (FOC) technique (typically used for 3-phase PMSM motors) with dual shunt current measurement and without any position sensor (sensorless). The Encoder sensor is supported by SW option, but missing on HW kit. The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with high-level Autosar compliant API or low-level non-Autosar API. FOC with single shunt current measurement Article focuses on solution based Field Oriented Control (FOC) technique (typically used for 3-phase PMSM motors) with single shunt current measurement and without any position sensor (sensorless). The Encoder sensor is supported by SW option, but missing on HW kit. The single shunt current measurement is advanced technique that allows decrese the cost of Bill of Material (BOM). The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with high-level Autosar compliant API or low-level non-Autosar API. FOC integrated with FreeRTOS Article focuses on integration of motor control software (based on FOC with dual shunt current measurement) and Real Time Operating System (FreeRTOS). The available example code is based ANSI-C code and uses RTD drivers with low-level non-Autosar API. Six-step commutation control. Article focuses on solution based Six-step commutation (6-step) technique (typically used for 3-phase BLDC motors) with Hall position sensor and without any position sensor (sensorless). The available example codes covers both ANSI-C and Matlab Simulink approaches and uses RTD drivers with low-level non-Autosar API. Note: the list of use cases cannot cover all combinations of MCU, current measurement scenario, control technique and sensor inputs, but should work as a base reference for most common configurations. This list is not final, please follow this acticle to be notified about updates with new use cases.

S32K ナレッジベース

S32K Knowledge Base

ディスカッション

Example S32K344 PIT BTCU ADC DMA DS3.4 RTD100

How to find the sector number of each flash block in S32K3 family

Example S32K118 FTM PWM DMA S32DS 2.2

Example S32K144 FlexCAN TX/RX/Error ISR test S32DS2.2

Example S32K146-Set_whole_FlexRAM-as_RAM v0_0 S32DS.ARM.2.2

Example S32K14x SRAM ECC Injection

Example S32K116 LPUART LIN Slave TXRX ISR S32DS.ARM.2.2

SENT receiver for S32K118 Design Studio

S32K144 ISELED + Touch Sensor Demo

S32M/S32K – Documents & Tools

Example S32K144 RTC VLPS

S32K Launched!

S32K LPUART hardware flow control

Example S32K116 FlexCAN PN STOP S32DS.ARM.2.2

Example S32K144 LPIT DMA LPSPI

Example S32K144 WDOG RCM interrupt

Example S32K116 WDOG Fast Test

Example S32K144 CMP Round-robin S32DS2.0

Where can I get s32k14x data sheet or reference manual?

Example_S32K344_EIM_ERM_DTCM_Baremetal_v2_0_S32DS36

S32K3 Motor control SW examples