Hello NFC Community! This document demonstrates that multiple records can be also read from a Tag with TagXplorer. Please follow the steps below. Let's begin... Please make sure that you have written more than on record with NXP TagWriter app. For a more detailed explanation on this, please refer to the following document: Writing multiple NDEF text records with TagWrite app  The app can be found and downloaded from the Play Store: NFC TagWriter by NXP - Apps on Google Play  -> Connect the reader in TagXplorer -> Place the card on the reader and press Connect Tag -> Check for NDEF (1) and then, read NDEF (2). The Text Records can be visualized in the NDEF Payload Info below: I hope this is of great help! Ivan R.

SPIM module is one of the master interfaces provided by PN7462 , which is a 32-bit ARM Cortex-M0-based NFC microcontroller, and users may use this interface to connect with up to two SPI slave devices. The NFC reader library provides SPIM driver code in phHal/phhalSPIM, and users may directly use the following APIs in their application to implement simple SPI transaction, just like what is done  in the demo of "PN7462AU_ex_phExHif". While this demo has limitation with some SPI nor flash devices, which need a write-read operation in one NSS session, for example, the SPI nor flash device on OM27462 as below: Please note to solder R202 and connect it to 3V3 to make sure nHold pin has pull-up out of POR. The following is one of the command sets this device supports: This command contains 1 write(9F) followed by 3 read operations in one NSS session, but if you implement it with phhalSPIM_Transmit() and phhalSPIM_Receive() as below: status = phhalSPIM_Transmit(PH_EXHIF_HW_SPIM_SLAVE, PH_EXHIF_HW_SPIM_INIT_CRC, PH_EXHIF_HW_SPIM_APPEND_CRC, PH_EXHIF_HW_SPIM_CRC_INIT, 2, cmd_buf, PH_EXHIF_HW_SPIM_CRC_OFFSET);    status = phhalSPIM_Receive(PH_EXHIF_HW_SPIM_SLAVE, PH_EXHIF_HW_SPIM_INIT_CRC, PH_EXHIF_HW_SPIM_CRC_INIT, data_length, dst, PH_EXHIF_HW_SPIM_CRC_OFFSET);" You will have the following result: expected: NSS   \__________________________/ MOSI     CMD A7-A0 MISO                            DATA       actual:                         NSS   \____________||______________/ MOSI     CMD A7-A0 MISO                           DATA so the pulse between the write and read is the problem, and here we have to handle the NSS line manually, with the help of NSS_VAL and NSS_CONTROL bits in SPIM_CONFIG_REG. so the code should be like this:   Assert NSS   status = phhalSPIM_Transmit(PH_EXHIF_HW_SPIM_SLAVE, PH_EXHIF_HW_SPIM_INIT_CRC, PH_EXHIF_HW_SPIM_APPEND_CRC, PH_EXHIF_HW_SPIM_CRC_INIT, 2, cmd_buf, PH_EXHIF_HW_SPIM_CRC_OFFSET);    status = phhalSPIM_Receive(PH_EXHIF_HW_SPIM_SLAVE, PH_EXHIF_HW_SPIM_INIT_CRC, PH_EXHIF_HW_SPIM_CRC_INIT, data_length, dst, PH_EXHIF_HW_SPIM_CRC_OFFSET);"   De-assert NSS The NSS line assert and de-assert function can be implemented with register bit level APIs, just like below:             PH_REG_SET_BIT(SPIM_CONFIG_REG, NSS_VAL);//de-assert NSS             PH_REG_SET_BIT(SPIM_CONFIG_REG, NSS_CTRL);             PH_REG_CLEAR_BIT(SPIM_CONFIG_REG, NSS_VAL);//assert NSS Please also include the following header files in your application code. #include "ph_Reg.h" #include "PN7462AU/PN7462AU_spim.h" Please notice that phhalSPIM_Transmit() and phhalSPIM_Receive() are Rom based function, which clear NSS_CTRL bit by default. We can not change ROM API's behave but fortunately we have phhalSPIM_TransmitContinue() and phhalSPIM_ReceiveContinue() instead. so the final solution will be like below: Assert NSS   status = phhalSPIM_TransmitContinue(1, cmd_buf);    status = phhalSPIM_ReceiveContinue(3, dst);   De-assert NSS This doesn't mean phhalSPIM_Transmit() and phhalSPIM_Receive() are useless, because they can also help up to configure the SPI master interface, if you don't want to use register bit level API to initial the SPIM module manually. Please note to use 1 byte for write/read length to make these two functions work properly. so the whole pseudo code is like below: phhalSPIM_Init(PH_HW_SPIM_TIMEOUT) ; phhalSPIM_Configure(PH_HW_SPIM_SLAVE, PH_HW_SPIM_MSB_FIRST,                 \                                     PH_HW_SPIM_MODE, PH_HW_SPIM_BAUDRATE,  \                                     PH_HW_SPIM_NSSPULSE, PH_HW_SPIM_NSSPOL) ; status = phhalSPIM_Transmit(PH_EXHIF_HW_SPIM_SLAVE, PH_EXHIF_HW_SPIM_INIT_CRC, PH_EXHIF_HW_SPIM_APPEND_CRC, PH_EXHIF_HW_SPIM_CRC_INIT, 1, cmd_buf, PH_EXHIF_HW_SPIM_CRC_OFFSET);    status = phhalSPIM_Receive(PH_EXHIF_HW_SPIM_SLAVE, PH_EXHIF_HW_SPIM_INIT_CRC, PH_EXHIF_HW_SPIM_CRC_INIT, 1, dst, PH_EXHIF_HW_SPIM_CRC_OFFSET);" Assert NSS   status = phhalSPIM_TransmitContinue(1, cmd_buf);    status = phhalSPIM_ReceiveContinue(3, dst);   De-assert NSS The following steps show how to create a new project based on NFC reader library, please refer to https://www.nxp.com/docs/en/user-guide/UM10883.pdf  on how to import the NFC reader library. 1. Create a new project after importing the NFC reader library. 2. if you installed PN7462 support package, you will see this: 3. add a link to NFC reader lib: 4. add path and enable NFC reader lib in the project: 5. delete cr_startup.c and create the main code as well as the header file: 6. Build result: 7.Debug result: To fetch the ready demo, please submit a private ticket via the guide of https://community.nxp.com/docs/DOC-329745 . Hope that helps, Best regards, Kan

The TDAEV8035 evaluation board is inserted into the connector slot located on the top side of the PN7642 EVK, as shown in the figure below.     Dedicated jumper settings are required to ensure proper connection and operation of the TDAEV8035 extension board.   J23 - Position 2-3 J65, J63, J64 - Closed  J59 - Closed (Positions 1-2, 3-4, 5-6) Once the jumpers are configured correctly, users can run the example applications provided in the PN7642 MCUXpresso SDK.     After building the example project, select the right card slot (TDA8035) on the board. By default, the SIM card slot (Slot 1) is used. To use the contact card slot instead, modify the slot selection in the following section of the code.     E_AUX_SLOT1 - SIM slot (default)  E_AUX_SLOT2 - Contact card slot  The selected card slot is indicated by a red LED. D1 - SIM slot  D2 - Contact Card slot Once all required settings have been applied, the example application can be started and a contact card can be inserted into the selected card slot.    The results can be viewed in the console.  

Prerequisites:  CLRC663 plus Low Power Card Detection   1// Antenna Size  The stronger the coupling between reader and card, the better the detection range.  Ideally, the NFC reader antenna should have a size and form factor similar to that of the target NFC tag antenna. In practice, the reader antenna is typically designed to be slightly larger—by approximately 10% to 20%—to ensure reliable coupling and performance.   2// Antenna Q-factor  Higher Q-factor typically serves higher detection range. The Q-factor should be selected in accordance with the target communication bit rate.(e.g. Q≈30 for 106 kbit/s).  The antenna Q factor is mainly defined by the mechanical design of the antenna itself, as well as by external damping resistors. However, for LPCD-insensitive systems, a zero-ohm damping resistor can be used, and the system should then be evaluated through testing.  3// Target tuning  The CLRC663 should typically be used with the asymmetrical tuning as there is no internal power regulation implemented.  However, in some cases, symmetrical tuning may be beneficial, as it can improve detection range and sensitivity. Care must be taken to ensure that, under varying conditions—such as antenna loading by different NFC tags or the presence of nearby metal, the TVDD current does not exceed the specified maximum limits.   In CLRC663 LPCD operation, detection performance improves with higher TX power. However, this also increases current consumption, so an appropriate trade-off must be determined.   As a starting point, an antenna impedance of approximately Z≈ 50 Ω can be used.   4// Receiver setting (external Rx resistors) Based on the AN11019 (chapter 4.4.1), the peak voltage between RxN and GND (or RxP and GND) shall be in the range of 1.2Vp - 1.7Vp. Generally, higher Rx voltage levels improve detection range. To increase LPCD sensitivity and range, it can be advantageous to operate close to the upper limit of the allowed Rx voltage.   Please note that excessively high RX voltage may lead to immediate false wake-ups.   5//LPCD Settings As a starting point, we recommend using the following settings:   These settings provide robust immunity against false wake-ups and are highly efficient in terms of current consumption. The typical detection range for standard NFC tags is approximately 10 mm to 20 mm or even less in an application where the antenna is placed near a metal environment. Detection performance can be further improved by lowering the threshold settings +0 and -0. If this settings is used, we strongly advice using LPCD_FILTER feature as well. Alternatively, the user can use "high detection range option" + LPCD_FILTER. After using these settings, we recommend running "Endless LPCD" for a while and checking for any false wake-up rates. Note: The LPCD filter feature helps prevent false wake-ups. This is especially important when the threshold is set to +0 and -0. When using thresholds of +0 and −0 it is also recommended to set the "CWMAX" parameter (address 0x2A) to 1b. 5.1// LPCD RF ON time  If the RF on-time is shorter than approximately 20 µs - 30 µs , the primary detuning effect is dominated by the physical design of the NFC tag. For longer RF on-times, the NFC tag becomes energized, and its electrical parameters begin to contribute significantly to the overall detuning. Based on this understanding, a longer RF on-time can help increase LPCD detection range. However, this comes at the cost of higher current consumption. Therefore, it is recommended to compensate by adjusting the RF off-time. See an example below.   5.2// LPCD Charge pump  This function allows the TX power to be increased exclusively during the LPCD RF On time.   This can be beneficial if you want to avoid increasing the power in active mode (e.g., by reducing the tuning impedance) but only increase it during LPCD operation.   By activating the LPCD charge pump, detection performance can be improved, but at the cost of increased current consumption.   If this feature is enabled, it is recommended to verify the LPCD RF ping using an oscilloscope. It may be necessary to increase the RF On time to allow the amplitude to properly settle. Especially for TVDD= 3.3V or lower. 6// Summary   Mode  Tuning function Target impedance Q-factor Receiver voltage LPCD Threshold LPCD Filter LPCD Charge -pump RF On time  Standard Asymmetrical  20 Ω - 80 Ω  10 - 30 1.5 Vp +1 and -1 disable disable 10 us High detection range  Asymmetrical /Symmetrical (1) 20 Ω - 50 Ω >25 (2) 1.7 Vp +0 and -0 enable enable/ disable (3)  20 us-100 us   Note (1): Symmetrical tuning can only be applied if the TVDD current does not exceed the maximum allowable value after antenna loading caused by a card or metal object. Please ensure that this condition is met. Note (2): If high detection performance is required, the external antenna damping resistors are typically replaced with 0 Ω resistors, resulting in a higher antenna Q-factor. In this case, the user must verify that NFC communication continues to operate reliably. Due to the increased Q-factor, this configuration is typically limited to communication speeds of 106 kbit/s Note (3): Once the charge pump is enabled, the RF On time should be verified and adjusted if necessary. Please also note that the relationship between TX power and detection distance is not linear or unlimited. Beyond a certain point, enabling the charge pump provides only marginal improvements in detection distance.     Please note that the High Detection mode is generally more susceptible to false wake-ups and results in higher current consumption than the standard mode.

The PN7642/PN5190/PN7220 requires a calibration before the RF field is switched on for the first time with unloaded condition. "Unloaded" means: Without any additional metal in proximity of the antenna, except for the NFC reader components itself. During development of new readers, this calibration shall be done each time the antenna design, antenna matching, or EMC filter is modified. See a workflow of the Initial calibration for PN7642 done in NFC Cockpit.  During this procedure, the RF Field is switched on for approx. 11 ms, and the calibration data is saved in the memory. Note: Please note that the registers and EEPROM addresses might differ for a different products. Always check the Datasheet for the used product. 

Prerequities:  PN7642 design-in recommendations   1// Impedance tuning  PN76 family antenna design guide The target impedance is chosen based on the target application. If full power is required (e.g., POS terminals). The target impedance of 15-17 Ω is recommended. For lower power applications using ULPCD, the higher impedance is typically preferred, 30-50 Ω (symmetrical tuning).   2// Dynamic power control  PN7642 - Basic RF power limitation using DPC   3// H-Field check  There are given limits, especially for the maximum H-field radiated by the reader. Exceeding these limits might lead to destroying the NFC Card/NFC Tag.   The H-Field can be measured with the help of test equipment, as  ISO 10373-6 Test PICC EMVCo 3.0 Test PICC  For indication only, the customers can use "smart" Field Strength Probes as shown below :        Note: The most critical position occurs when the card is placed directly on the NFC antenna . In this case, if the H-field exceeds the maximum allowed level, the output power must be reduced using DPC settings. 4// HF Attenuator value  Turn on the RF Field with the DPC set and enabled from the previous step  Read the CLIF_RXCTRL_STATUS register and check the HF_ATT_VAL as shown below.    The value for the "unloaded" condition with full power shall be approximately 35-45dec.  If the value is out of this range, the customer is required to adjust the Rx resistors to reach this value.  5// Receiver settings  Check the "Power" range and Communication Range with the default settings provided by NXP.  Power Range -> The distance at which the NFC Tag can still generate its answer, but the NFC Reader does not see it  Communication Range -> The distance at which the NFC Tag can still communitate with the NFC Reader  Ideally, Power Range ≈ Communication Range Also, the NFC Reader should not generate any false communications as e.g., "HAL COLLISION ERROR".  The optimisation of the receiver can be done in the following way:  Enter DPC Calibration  Go to the "ARC" menu and "disable" the ARC algorithm     This will force the IC to use the RX settings from the following Register/EEPROM SIGPRO_RM_TECH_REG DGRM_RSSI_REG   5.1// SIGPRO_RM_TECH_REG (RM_MF_GAIN parameter) This parameter basically defines the gain of the input amplifier.  Select SIGPRO_RM_TECH_REG  Switch "operation" to EEPROM and choose the required technology  Increase the RM_MF_GAIN to 0x02 (it depends on the setup).     5.2// DGRM_RSSI_REG (DGRM_SIGNAL_DETECT_TH_OVR_VAL parameter) This parameter defines a threshold from which the internal logic starts to decode the incoming signal.  If the threshold is too low or very close to the noise floor, the system can detect the noise as an NFC Communication.  It is therefore,  Threshold + margin > noise floor The best routine is to perform "Signal Detection Threshold" analysis. This can be done with the help of the NFC Cockpit (described in PN7642 design-in recommendations) As a result, the user can obtain the mean value of the "Noise," and suggested "DGRM_SIGNAL_DETECT_TH_OVR_VAL" threshold based on the inserted "Margin."  Maring (m) + Noise mean value (μ) = Threshold  6+16=23 Then this value shall be written in "DGRM_RSSI_REG" EEPROM as shown below.      6// ULPCD Settings  We recommend the following ULPCD Settings as a starting point.  ULPCD VDDPA should be chosen in such a way that the HF Attenuator value is not 0x00! The typical value for HF Attenuator in ULPCD is around 0x05-0x0B.   6.1// RSSI Threshold evaluation  For a proper RSSI Threshold selection, it is recommended to perform the ULPCD Calibration, e.g., 20 times, and check the "jitter" of the RSSI signal for your device.    If you see that the RSSI value is jittering, e.g., 1 unit as shown above. The absolute minimum threshold for this case is 2. However, it is always recommended to include adequate margin (To prevent false wake-ups).   Generally, the margin of 2 units is sufficient. So in this case, the optimum threshold will be 4. 

PN5190-NTAG X DNA High Speed Communication Demo: This article describes important feature of these two chips when interacting with each other at contactless interface: Passthrough demonstrator at high bit rates for ISO/IEC14443-A between PN5190 and NTAG X DNA Scope of demonstrator: ▪ Demonstrating a unique feature of NXP Semiconductors. High bit rates for ISO14443 communication (up to 848 kbps) between a PN5190 reader IC and an NTAG X DNA when connected to MCXA153 host MCU, when simulating the transmission of a dummy file as big as 101 kbytes. ▪ Through MCUXpresso console, the user can configure the contactless bit rate: 106 kbps 212 kbps 424 kbps or 848 kbps The amount of data is fixed in this demo. ▪ transmission mode is implemented from NFC reader library at K82 MCU built in the PNEV5190BP evaluation kit. On the other side, NTAG X DNA + Level shifter (represented by evaluation kit NTAG-X-DNA-EVAL) is connected to a Freedom Board, equipped with MCXA153 - FRDM-MCXA153). ▪ The PN5190 prints on the MCUXpresso console (debug mode) the outcome of the transaction and average baud rate achieved. ▪ In order to handle full file transmission from K82 to MCXA153 (MCU <-> MCU communication), we are using NTAG X DNA GPIO wires as well as proper settings on the NTAG X DNA <-> MCXA153 side and hard coded timeout on the PN5190 + MCU side. For more details, please open attached file PN5190_NTAGXDNA_MCXA153_DualInterface_HBR_Demo_SetupInstructions_Q32025.pdf. Required hardware and software enablement: Hardware ▪ PNEV5190BP Development Board ▪ FRDM-MCXA153 Development Board ▪ NTAG X DNA Development Board ▪ 2 x USB micro cables (for PNEV5190BP dev. br., one for DC power, other for Jlink debug on MCUxpresso IDE) ▪ 1 x USB-C cable (for FRDM-MCXA153 dev. br., only for DC power) Software ▪ MCUxpresso project (firmware Source Code) for PNEV5190BP is attached to this article, containing keywork pn5190: pn5190-ntagxdna-highspeed-demo1.zip. Instructions will be given in from future release of NFC Reader Library public v07.14.00 (NxpNfcRdLib_PN5190_v07.14.00_Pub.zip). ▪ SDK_2.x_FRDM-K82F is already included in bundle mentioned above. ▪ Firmware Source Code for FRDM-MCXA153 is attached to this article, containing keyword MCXA153: MCXA153.zip ▪ MCUXpresso IDE recent version, for instance v24.12.148 or above. Demonstrator bring up: Hardware assembly for FRDM-MCXA153: • Connect NTAG X DNA to level shifter (see Fig. 1) • Connect bundle NTAG X DNA+ level shifter bundle to flat cable (contained in demokit box) to FRDM-MCXA153 according to Fig. 2. • Make sure each wire is connected to proper position in Arduino socket: - black wire IO2 goes to J1-14 - white wire IO1 goes to J1-16 - gray wire SCL goes to J2-20 - violet wire SDA goes to J2-18 - blue wire GND goes to J3-14 - green wire VCC goes to J3-8 • Connect FRDM-MCXA153 via J15 (MCU-Link) to your computer (Debug Link Input), for the first time that you have to flash binary in it. Then after storing binary, you may just connect USB-C cable from a power supply to J6 port (named Ext-debugger). • No additional power source is needed. Hardware assembly for PNEV5190B: • Connect two USB micro cables to PNEV5190B board for power, flashing firmware and UART connection (see Fig. 3): • microUSB on J7 is necessary for DC power. Check that jumper J9 is in the position USB dc supply • microUSB on J20 is the Jlink debug port, and it will be connected to your Windows computer, where MCUxpresso has been installed. • Red LED indicates power is enabled • Green LED debugging/UART status Alternatively, if you have a DC power supply (voltage above 7 V), you may change Jumper J9 to Ext power supply, and avoid using second microUSB cable. Software loading on FRDM-MCXA153: 1. Create a new workspace for MCXA153 MCUxpresso example: 2. Make sure you have installed MCXA153 SDK: - install MCXA153 SDK which can be downloaded from: https://mcuxpresso.nxp.com/  3. Unzip "MCXA153.zip" file in local C: directory, with reasonable path length. 4. Import existing projects from file system, into MCUXpresso IDE: 5. Select proper root directory (keyword is MCXA153): 6. Click "Finish" 7. If you get this warning, simply click "OK": 8. Highlight project, click "build", and check that there are no errors: Finished building target: MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf Performing post-build steps arm-none-eabi-size "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf"; # arm-none-eabi-objcopy -v -O binary "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf" "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.bin" ; # checksum -p MCXA153 -d "MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.bin";    text        data         bss         dec         hex     filename   23524          20        3684       27228        6a5c      MCXA153_NTAGXDNA_DualInterface_DataRead_Demo.axf 16:27:26 Build Finished. 0 errors, 0 warnings. (took 5s.787ms) 9. Now, flash the binary into MCXA153 MCU using GUI Flash tool; select suitable  MCUxpresso probe (CMSIS-DAP). Make sure USB-c cable is connected to J15 in Freedom board (MCU-link port for flashing FW). 10. Select binary file *.axf as indicated below: It may happen that your MCXA153 has outdated FW on CMSIS-DAP, but you can continue, it will make no harm; click then Ok to flash. 11. After flashing, reboot your board. Following LEDs should be on: - D15 RGB led should be "white" lit. - D7 should be blinking "red" - D8 and D4 should be "green" lit. D15 will blink "white" only during file transmission. You may disconnect USB-c from J15 (the one used with MCUxpresso for flah and connect it to J8. Then, plug the other cable tip to any USB  5 volt battery charger. Now your Freedom board FRDM-MCXA153 is ready to receive data from PNEV5190 board, once project will be imported too in MCUxpresso. Software loading on PNEV5190BP: 1. Unzip *.zip file in directory with reasonable path length. 2. Import existing projects from file system 3. Select Example 12 "NfcrdlibEx12_NTAGXDNA" 4. Uncheck the choice "copy projects into workspace" 5. Install SDK_2.x_FRDM-K82F if not yet done. Such SDK is included in project file tree: • ...Examples\Platform\SDK_2.x_FRDM-K82F • This specific SDK can be obtained from https://mcuxpresso.nxp.com/ by selecting following K82F tab related "PN5180" : • FRDM-K82F-PN5180 (MK82FN256xxx15) • SDK 2.0 is no longer officially available, but SDK 2.2 and newer are backward compatible and recommended by NXP • Build project and check that there are no errors ("warnings" are allowed). • Start Debug session to see available bitrate options on the console. Hardware combination of PNEV5190B and NTAG X DNA connected to FRDM-MCXA153: Under MCUXpresso: 1. Click "Debug" icon on quick access left panel. Accept agreement in case of J-Link tool: 2. Click on icon "Run" on top side of MCUxpresso, and observe the following on "Console" tab: [MCUXpresso Semihosting Telnet console for 'NfcrdlibEx12_NTAGXDNA_mcux JLink DebugFRDMK82F' started on port 59973 @ 127.0.0.1] SEGGER J-Link GDB Server V8.12a - Terminal output channel *** NTAG X DNA Example *** Please place NTAG X DNA Card and Select Demo option. 1 : Perform Data Read Write using AES128 Key Authentication 2 : Perform Data Read Write using ECC Sigma-I Authentication Host as Initiator with NIST P-256 Curve, session key AES128 3 : Perform Data Read Write using ECC Sigma-I Authentication Host as Responder with NIST P-256 Curve, session key AES128 4 : Perform HBR transfer to Microcontroller through NTAG X DNA. 5 : Configure NTAG X DNA for HBR transfer Enter your option : Menu options when two boards have NFC antennas facing each other: There are 5 options in console menu as soon as you "Run" the debug. 1 - options from 1 until and including 3 are related to crypto functionality (symmetric and asymmetric) and are out of the scope of this article. 2 - Then option 5 is used for the first time that you are configuring your NTAG X DNA product. It will set registers and GPIO properly for High bit rate transfer. Once you have run option 5, then go to option 4: 3 - Four options of bitrate are available for transfer a fixed amount of data from host (K82) to NTAG X DNA MCU (MCXA153) using PN5190 as tunnel: Please configure the required baud rate 1 : 106 Kbps 2 : 212 Kbps 3 : 424 Kbps 4 : 848 Kbps Enter your option : Demonstration flow: Once one of these option is selected, reader is ready to detect a tag. ▪ When tag is detected, reader configures selected bitrate and starts data exchange. ▪ Blinking RGB LED D15 indicates transfer ongoing and the console shows a progress. Here are some results of transaction at the different bit rates and data sizes offered by this demonstrator: 1 - 106 Kbps - Baud rate 7.6 kBytes/s - elapsed time: 13.99 s Type A Tag is discovered. ***** Perform Transfer sequence ******* Select Application Successful Select File Successful Data transferring NFC -> NTAG X DNA -> Microcontroller... Amount of data exchanged 101200 Bytes, Baudrate (total) = 7.6 kB/s, Time = 13.99 s Please Remove the Card   After removing the card, K82 firmware starts again prompting for a new selection, in the previous menu. First select 4 again and then chose again another new baud rate: 2 - 212 Kbps - Baud rate 10.51 kBytes/s - elapsed time: 9.39 s 3 - 424 Kbps - Baud rate 13.92 kBytes/s - elapsed time: 7.90 s 4 - 848 Kbps - Baud rate 16.60 kBytes/s - elapse time: 5.95 s   Using Example 12 of NFC Reader Library v.07.14.00 to prepare High Speed demo on PNEV5190BP and NTAG X DNA: 1. Go to https://nxp.com web site and type "NFC Reader Library" in Search tab. Follow the instructions until you get to this screenshot: 2. Start by downloading NFC Reader library V.07.14.00 from NXP website; agree with Terms and Conditions. Then download the bundle to your local C: drive: 3. Click on “down arrow” to download version 07.14.00. Once zip file is received, unzip previous bundle to a local drive directory.   4. Start a new workspace, then choose "Import from Existing Projects into Workspace": 5. De-select all useless Examples and keep only example 12; please including all other essential items; click "Finish": 6. If you find this error, it means you need to install K82F SDK: 7. Click install, then MCUxpresso SDKs pages will open. Select K82F from Processor tab: Click “Install” button; after installation is completed, you will get a screen showing all installed sdk's. Afterwards you may get the prompt "Make SDK persistent"; just click ok. 8. Highlight project NfcrdlibEx12_NTAGXDNA_mcux and click build; check if there are errors: Finished building target: NfcrdlibEx12_NTAGXDNA_mcux.axf Performing post-build steps arm-none-eabi-size "NfcrdlibEx12_NTAGXDNA_mcux.axf" ; arm-none-eabi-objcopy -O binary "NfcrdlibEx12_NTAGXDNA_mcux.axf" "NfcrdlibEx12_NTAGXDNA_mcux.bin" ; #checksum -p MK82FN256xxx15 -d "NfcrdlibEx12_NTAGXDNA_mcux.bin"    text        data         bss         dec         hex     filename  222400          92       86816     309308       4b83c      NfcrdlibEx12_NTAGXDNA_mcux.axf 17:32:59 Build Finished. 0 errors, 3 warnings. (took 33s.718ms) 9. Now, check in MCUxpresso the tab Windows > Preferences > Run/Debug. Untick the box related to General Options Build (if required) before launching; it will save you much time! Then, click button “Apply and Close”. 10. Using this Example 12 as it is given by NXP in this library, when you will debug it, you will realize that there are only 3 Menu options related to NTAG X DNA cryptography (and no high speed options). In order to “unlock” the high-speed demo option, please do the following. 11. Go to Quick Settings → Defined Symbols and open it in a new window: Now add after last symbol, the following line: "PH_EX12_ENABLE_DUALINTERFACE_HBR", by clicking on “add button” ("+" shown in green) on top right side of above window; add it manually then click OK two times. Now, build Ex12 again and check that there are no errors. 12. Debug Example 12, then press Run button and check if Console has 5 options in its Menu: Please place NTAG X DNA Card and Select Demo option. 1 : Perform Data Read Write using AES128 Key Authentication 2 : Perform Data Read Write using ECC Sigma-I Authentication Host as Initiator     with NIST P-256 Curve, session key AES128 3 : Perform Data Read Write using ECC Sigma-I Authentication Host as Responder     with NIST P-256 Curve, session key AES128 4 : Perform HBR transfer to Microcontroller through NTAG X DNA. 5 : Configure NTAG X DNA for HBR transfer Enter your option : 13. Let's focus on the last two options: 4 – perform HBR (high bit rate) transfer, and 5 – Configure your NTAG X DNA for HBR. 14. If this is the first time you are using this NTAG X DNA connected to MCXA153, then choose option 5 so that PN5190 will write proper configuration data to NTAG X DNA next to it. For this reason, turn on NTAG X DNA connected to FRDM-MCXA153 board (after powering it up with a simple 5V-USB source), and place NTAG X DNA antenna over PNEV5190BP board antenna (connected to MCUxpresso), as in picture shown above. Enter your option : 5 Ready to detect Type A Tag is discovered.       Select NDEF Application Successful       Authenticate Application Successful       SetConfig Successful       StdDataFile with File ID 0xE106 already exists. Please Remove the Card 15. Remove NTAG X DNA antenna from PN5190 antenna, until you get back to initial menu. Then, choose option 4 on previous menu: 4 : Perform HBR transfer to Microcontroller through NTAG X DNA. 5 : Configure NTAG X DNA for HBR transfer Enter your option : 4  Please configure the required baud rate 1 : 106 Kbps 2 : 212 Kbps 3 : 424 Kbps 4 : 848 Kbps Enter your option : 16. Now, choose the lowest speed "1"; check final result: Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller...       Amount of data exchanged 101200 Bytes, Baudrate (total) = 5.72 kB/s, Time = 17.25 s Please Remove the Card 17. Separate both antennas, and then, choose option "2"; check final result: Enter your option : 2 Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller… Amount of data exchanged 101200 Bytes, Baudrate (total) = 10.49 kB/s, Time = 9.41 s 18. Separate both antennas, and then, choose option "3"; check final result: Enter your option : 3 Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller...       Amount of data exchanged 101200 Bytes, Baudrate (total) = 13.89 kB/s, Time = 7.11 s Please Remove the Card 19. Separate both antennas, and then, choose option "4"; check final result:  Enter your option : 4 Ready to detect Type A Tag is discovered. ***** Perform Transfer sequence *******       Select Application Successful       Select File Successful       Data transferring NFC -> NTAG X DNA -> Microcontroller...       Amount of data exchanged 101200 Bytes, Baudrate (total) = 16.57 kB/s, Time = 5.96 s Please Remove the Card Conclusions: This demonstrator HW & SW can show that high speed interaction can be achieved between PN5190 (NFC Front end) and NTAG X DNA (NFC connected tag), making use of available commands described in its product support package (https://www.nxp.com/products/NTAG-X-DNA). Disclaimer:All SW available here is aimed only for evaluation purposes and NXP disclaims any direct or indirect liability damages, since referred SW bundles are not yet official part of PN5190/NTAG X DNA standard product support packages currently available at nxp.com.  

The PN7642 includes a USB interface, which allows USB communication with the PC.  Once the PN7642 USB communication is established, the NFC Cockpit tool can be used for RF debugging.  Note: This also requires flashing the NFC Cockpit application with the help of the mass storage mode or SWD interface.  Basically, the user has to connect a USB cable/Connector to the following PN7642 pins.  USB Signal  PN7642 Pin  5V  USB_VBUS Data - ATX_D Data + ATX_C GND GND   See an example below. This is a very basic connection (for evaluation or debugging only) where the USB cable is directly connected to the PN7642 pads.  This situation may arise during debugging on customer hardware where the USB interface is not yet implemented on the PCB. But a user wants to debug with the help of NFC Cockpit.    Please note that the proper USB interface might require special layout rules, such as impedance, overvoltage protection, etc.. For more info, see the PN7642 EVK reference schematic or USB PCB design guide. 

This might be convenient if the user wants to use NFC Cockpit on their device.  See the photo of PNEV5190BP EVK with the instructions.          1. Place R5 and R7, keep R6 open    2. Place R20, keep R19 open Note: This step depends on the voltage domain used in the external hardware. If R19 is placed -> 1.8V domain, if R20 is placed -> 3.3V domain.    3. Remove VBAT, VBAT_PWR, and VUP jumpers to disconnect the "internal" PN5190 located on the EVK    4. Connect the following SPI lines to external PN5190 (e.g., customer HW) SPI_CLK SPI_MOSI SPI_MISO SPI_CS NFC_IRQ GND Note: It is also necessary to disconnect the external PN5190 from the customer MCU. 5. Connect VEN to the external PN5190  NFC_VEN   Now, the external PN5190 HW should communitate with the MCU located in PNEV5190BP, and the NFC Cockpit can be used. The user should see that the blue LED is on. If the red LED is blinking, there is an issue, and the user should check the connections/supply. 

LPCD (Low Power Card Detection) works on the principle that the I and Q values are extracted from the RF signal captured on the RX pins. These values are then compared with the I and Q data obtained using LPCD calibration. If the difference is greater than the chosen I and Q threshold, the load is detected and the IC wakes up.  1// LPCD Way of working  Run LPCD Calibration  It is recommended to use an external power supply to supply the EVK board. If the USB supply is used, the value can fluctuate because of the transition effects.  Run "Single LPCD" and check the performance  Adjust the I and Q thresholds  Low value -> Better detection range, more false wake-ups  High value -> Worse detection range, fewer false wake-ups  The number of samples, RSSI, and VDDPA parameters typically remain at their default values.  2// Auto LPCD  When the "Auto LPCD" is used, the LPCD algorithm always performs LPCD Calibration before entering the LPCD. 3//Semi-autonomous LPCD mode (PN5190 only)   The user can evaluate the I and Q values behaviour under loaded/unloaded conditions. Based on that, the LPCD threshold can be properly selected.  Use the same "Register" RSSI Target and Hysteresis as for "EEPROM" Calibrate LPCD Run "Endless I/Q read"  Check how the I and Q values change With no card/object in the antenna proximity  with a NFC card/object in the antenna proximity

This document show the detail steps of following the Personalization example in AN12196. Tool : Pegoda3 and RFIDDiscover.    

A user can evaluate the current consumption of PN7642 in low power modes with the help of the PN7642 Evaluation Board (OM27642) and:  MCUXpresso SKD example (LPCD)  NFC Cockpit or MCUXpresso SKD example (ULPCD) NXP defines the current consumption in ULPCD/LPCD as VBAT current + VDDIO current for the LPCD/ULPCD cycle time of 330 ms. Make sure that DC/DC is disabled (for ULPCD).  Where:  VBAT current = VBAT_Current + VBATPWR_Current + VUP_Current See the snapshot from the PN7642 Datasheet below:    See where to measure the currents on PN7642 EVK: J63 and J64 are used for enabling/disabling the LEDs that are connected to PN7642 GPIOs. They must be disabled for a proper VDDIO current measurement.  A modification of R69 and R70 is necessary to perform the current measurement on VDDIO in LPCD mode.   1. ULPCD current consumption evaluation For the ULPCD evaluation, the NFC Cockpit or SDK example can be used. In this article, we will focus on evaluation using the NFC Cockpit.  See the used ULPCD configuration:  Note: The current should be measured as an average over, e.g., 30 seconds.  1.1 Overall ULPCD current measurement  To measure all currents together on PN7642 EVK, a user can create a measurement fixture as shown below:  Real setup :  Then the overall results look as follows: Note: The Antenna is tuned to approx. 35 Ohms  In this case, the ULPCD current is approximately 21 μA. This current can be further optimized, for more details, see -> AN14518(Start-up optimization in ULPCD (PN5190/PN7642/PN76AC)) 2. LPCD current consumption evaluation The user has to import the example (pnev7642fama_nfc_low_power_mode_Pub) from the PN7642 SDK.  Before building it, the following change in the code has to be made:  -> Comment line 84   A user can adjust the LPCD cycle time as shown below:   1.1 VBAT Current measurement    In this case, the VBAT current is approximately 123 μA. 1.2 VBATPWR current measurement  In this case, the VBAT_PWR current is approximately 91,8 μA. 1.3 VUP Current measurement  In this case, the VBAT_PWR current is approximately 32,8 μA.  Note: This current depends on the LPCD VDPPA settings + Antenna Impedance tuning  1.4 VDDIO Current measurement Note: Before VDDIO measurement, place jumpers J63 and J64 on PN7642 EVK. This will disable LEDs that are connected to PN7642 GPIOs.  The VDDIO current measurement requires the following steps:  Run the "pnev7642fama_nfc_low_power_mode_Pub" example  Once the example is running, disconnect the debugger (J-link, LPC-Link...) from J21 (NFC Debug connector)    Remove R70  Populate a 10K resistor on the R69 position (it disables the SWD interface) Once the measurement is done, change it back to the default state (R70=0R, R69=Open). Note: It is recommended to prepare the board with the option to easily populate or remove R70 and R69 when the LPCD example is running. E.g., with the help of jumpers/pin headers as shown below.   Only then will the correct VDDIO be measured on PN7642 EVK.  See the VDDIO current measurement below:    In this case, the VDDIO current is approximately 5,48 μA.  Then the overall current comsumption in LPCD is I_VBAT + I_VDDIO= (123 + 91,8 + 32,8 + 5,48) = 253,08 μA Note: For this measurement, the NFC Cockpit is not suitable because the IC does not go into standby mode between LPCD RF pings. Meaning LPCD works normally, but a user can measure higher current consumption. Used Ampere meter -> Power Profiler Kit II Measurement has been performed with FW 2.6  Board supply (jumpers J1, J2 and J4) -> 3.3V Please note that this measurement is indication only! 

Step 1:  Disable the DCDC in settings (Valid for PNEV5190B and OM27642EVK) Write 0x21 into EEPROM PWR_CONFIG (address: 0x0000) This disables the DCDC. & selects that the VUP must be supplied with the same supply voltage as VBAT = VBATPWR. Do not enable RF afterwards, before the hardware is modified properly! Enabling the RF without supplying the VUP might kill the PN5190/PN7642! Step 2: Supply VUP = VBATPWR  Connect jumper J13 positions: 1-2: This supplies the VUP with VBATPWR = 3.3V PN5190 EVK: Please note that for a final application using ULPCD, the "DC-DC" inductor (L2) has to be replaced by a zero resistor/short.    PN7642 EVK:  The OM27642EVK does not require any jumper settings (DC-DC is not used by default), the User must only disable DC-DC in EEPROM (address 0x0000, value 0x21) Then you can turn-on RF and perform ULPCD   Please note that for a final application using ULPCD, the "DC-DC" inductor (L2) has to be replaced by a zero resistor/short.  Also, R8 shall be placed   

Introduction NTAG5 offers a powerful energy harvesting feature (up to 30mW). One useful application can be charging the supercapacitor which then might be used as the supply of customer MCU, Sensor, etc.   See the typical schematic below:  C1 and C1P are used for the impedance tuning. The antenna is typically tuned at 13.56 MHz-14MHz.  R1 is used to limit the charging current of the supercapacitor. Its value depends on the selected VOUT voltage, keep in mind that the maximum output current is 12.5 mA.  E.g. VOUT=2.4V, Icharging=10mA -> R1=240 Ohm Keep in mind, that if the charging current is too high and/or the amount of the received magnetic field is not high enough, the VOUT may drop.  D1 should be a low-drop diode e.g. RB520CS30L Used super cap: CPX3225A752D Antenna size  Generally, it is best to attempt to match the tag and the reader antenna geometries for maximum efficiency. A significant difference between the reader and tag antenna dimensions result in bad communication and energy harvesting performance because of the small coupling factor. As smartphone NFC antennas can have different dimensions. It might be challenging to design one NFC Tag antenna that will deliver the best performance for multiple smartphones.  The phone's NFC Antenna dimensions are typically between approximately 25 mm vs 20 mm (NFC Forum Poller Class 6) & 50 mm vs 30 mm (NFC Forum Poller Class 3). Note: But this might be different e.g., iPhones  So customers can consider the following form factors of NFC antennas for their Energy harvesting NTAG5 Link design:  For bigger designs (NFC Forum Listener Class 3):    For circle NFC Antenna ->Outer diameter is approx. 44 mm    For smaller designs (NFC Forum Listener Class 6):  For circle NFC Antenna ->Outer diameter is approx. 25 mm     Tomas Parizek  Customer Application Support 

How to set the RF Settings can be found in -> https://www.nxp.com/docs/en/application-note/AN13218.pdf The list of the default values + values which shall not be changed is available in the attachment.  Tomas Parizek  Customer Application Support 

  NXP offers FW update code as part of the SW6705.   All PN7160 FW versions including ".c" files are available on PN7160 Github.    PN7160 is typically delivered with the initial FW 12.50.05. To ensure full reliable functionality, it is highly recommended to update the FW on 12.50.09 (or latest). The FW update might be also helpful if you need to restore the default EEPROM settings.  The FW source data are inside the sFWudpate folder.  phDnldNfc_UpdateSeq.c -> FW Version 12.50.05 phDnldNfc_UpdateSeq_12_50_09.c -> FW Version 12.50.09 The phDnldNfc_UpdateSeq.c is executed, which means what is inside of this "C" file is pushed to the PN7160 EEPROM.  So, if you want to update from 12.50.05 to 12.50.09. You need to copy content from phDnldNfc_UpdateSeq_12_50_09.c to The phDnldNfc_UpdateSeq.c.  Also, make sure that the content in phDnldNfc_UpdateSeq_12_50_09.c is commended.   Once that's done, you can debug the code.  Then you can check the progress in "Terminal"    Tomas Parizek  Customer Application Support 

The PN5180 offers a low-power card detection (LPCD) feature, which allows to power down the reader for a certain period of time to safe the energy. After this time the reader must become active again to poll for the cards. If no card has been detected, the reader can go back to the power down state. PN5180 LPCD cycle time includes standby time and VBAT time. In a normal case, standby time is 200ms (user can define it),   standby current is 15uA, VBATON current is 7500uA, FieldON current: 200mA.  Average current is about 200uA, it depends on your settings and application.   This article describes how to configure PN5180 LPCD using NXP Cockpit Tool and using NXP NFC Reader library.   1  PN5190 LPCD Overview PN5180 LPCD operates in two modes: auto calibration mode and self-calibration mode. Auto calibration mode:  everything done automatically Self-calibration mode:   calibration must be done manually before starting the LPCD.   1.1  Auto Calibration Mode ( 00b) The LPCD calibration is done automatically when the LPCD is started, using the gear and threshold as defined in the EEPROM. This mode always uses the same gear for the LPCD, and is the fast and easiest way to start the LPCD.  It is recommended to choose a gear, which always keeps the ITVDD and field strength limits, so normally, the highest gear number. Auto calibration mode is most commonly used, it is a standard use case. Below parameters need to be configured correctly in EEPROM   LPCD_REFERENCE_VALUE       LPCD_REFVAL_GPO_CONTROL      LPCD_THRESHHOLD  ( 0x37) LPCD wakes up, if current AGC during “ping” > AGC Reference + LPCD_THRESHOLD or< AGC Reference -LPCD_THRESHOLD Minimum LPCD_THRESHOLD = 03…08 (very sensitive) Maximum LPCD_THRESHOLD = 40 … 50 (very robust)    LPCD_FIELD_ON_TIME  (0x36) RF on time in 8µs, excluding the fix time .   Fix time = 62µs 01 => RF on = 70µs 02 => RF on = 78µs 03 => RF on = 86µs 10 => RF on = 190µs   1.2  Self Calibration Mode (01b) The LPCD calibration must be manually triggered, with reading or writing into the AGCREF_CONFIG register.   Reading from this register - without prior writing - starts an LPCD calibration. The calibration is executed using the gear which is resulting from the actual DPC setting under the actual antenna detuning condition. AGC_GEAR is used in the LPCD self-calibration.   Reading from this register - without prior writing - delivers in addition to the AGC_GEAR value the AGC_VALUE. The AGC_VALUE is used in the LPCD self-calibration. Writing to this register: Writing data to this register is required before starting the LPCD in Self-calibration mode. Either the previously read AGC_GEAR or a user-defined gear can be chosen. The previously read AGC_VALUE has to be written in any case. Writing data to this register defines the values for AGC_GEAR without taking the actual detuning condition into account. The value of AGC_GEAR to perform an LPCD calibration which derives the AGC_VALUE. This AGC_VALUE and the AGC_GEAR are used in the LPCD self-calibration.   Self-calibration mode always requires a Read AGC_REF_CONFIG, followed by a write AGC_REF_CONFIG, using the previously read AGC_VALUE.   The LPCD calibration can be done in two different options: Option 1:  Read AGC_REF_CONFIG register:  This command executes a standard RF Field on. So depending on the load condition the DPC adjusts the output power. The final gear is take as gear for the LPCD.  This option guarantees that the maximum output power is taken for the LPCD.   Option 2: Write AGC_REF_CONFIG register: This command executes a LPCD calibration ping with the gear number, as defined in the AGC_REF_CONFIG, bit 10:13. This option allows a flexible use of any of the defined gears for the LPCD.   PN5180 LPCD self-calibrate is executed, using Gear -> AGC_REF_CONFIG (Register) Threshold -> LPCD_THRESHOLD (EEPROM) RF on time-> LPCD_FIELD_ON_TIME (EEPROM)   2  How to configure PN5180 LPCD with Cockpit The NFC Cockpit allows the configuration and test of the low power card detection of the PN5180 as shown in below picture. The LPCD parameter, which are stored in the EEPROM, can be changed and the LPCD can be started. The LPCD tab allows to directly define and write the related EEPROM addresses:   LPCD Gear #: Defines the gear number, which is used for the LPCD in auto calibration mode, stored in addr. 0x34, bit 0:3 Threshold Value: Defines the threshold window, As soon as the AGC value during the LPCD ping exceeds the AGC reference value + threshold window, the IRQ will be raised and the PN5180 wakes up. Field On Time:  Defines the ping length Standby time :  This value defines the time between two pings in ms. FieldOn Current: This value is ITVDD under the loading condition, when RF field is on with the used gear. This value does not have any influence on the LPCD execution, but simply is used to estimate the overall  average current consumption. This current estimation is calculated, when the LPCD is started.         3   How to configure PN5180 LPCD with NXP NFC reader library. The LPCD works in two phases: First the standby phase is controlled by the wake-up counter (timing defined in the instruction), which defines the duration of the standby of the PN5180. Second phase is the detection-phase. The RF field is switched on for a defined time (EEPROM configuration) and then the AGC value is compared to a reference value.   Below is the flow chart for PN5180 LPCD          

DISCLAIMER APPLICABLE TO THIS DOCUMENT CONTENTS:   PN5190-NTAG 5 boost High Speed Communication Demo This article describes the unique feature of these two chips when interacting with each other at contactless interface: Passthrough demonstrator at high bit rates for ISO 15693 between PN5190 and NTAG5 Boost. Scope of demonstrator: ▪ Demonstrating a unique feature of NXP Semiconductors. High bit rates for ISO15693 communication (212 kbps) between a PN5190 reader IC and an NTAG5 boost connected to LPC55S69 host MCU, when implementing passthrough mode using the SRAM of the NTAG 5 boost. ▪ Through MCUXpresso console, the user can configure the contactless bit rate (26.4kbps or 212kbps options) as well as the amount of data to exchange using passthrough mode. ▪ Passthrough mode is implemented from NFC reader to LPC side only. ▪ The PN5190 prints on the MCUXpresso console the outcome of the transaction and baud rate achieved. ▪ In order to handle passthrough communication, we are using GPIO interrupt handlers on the NTAG 5 boost + LPC55S69 side and hard coded timeout on the PN5190 + MCU side. Required hardware and software material: Hardware ▪ PNEV5190BP development board ▪ LPCXpresso55S69 Development Board ▪ OM2NTA5332 - NTAG5 boost development kit ▪ 3 x USB micro cables Software ▪ Firmware Source Code for PN5190 is attached to this article, containing keywork pn5190: HIGHSPEED_PN5190_NTAG5boost1.zip ▪ SDK_2.x_FRDM-K82F is already included in bundle mentioned above. ▪ Firmware Source Code for LPCXpresso55S69 is attached to this article, containing keyword lpc55s69: NTAG5boost_LPC55S69.zip ▪ MCUXpresso IDE recent version (v24.12.148 or newer) Demonstrator bring up: Hardware assembly for LPCXpresso55S69: • Connect NTAG5 Boost board to LPCXpresso55S69 • Make sure SW6 is on position 2-3 to enable 5V power on tag side (it will also work at 3.3V but maybe with less readrange). • Connect LPCXpresso55S69 board to your computer (Debug Link Input). • No additional power source is needed. Hardware assembly for PNEV5190BP: • Connect two USB micro cables to PNEV5190B board for power and flashing firmware via UART connection (alternatively, you may change jumper J9 to position 2-3 and connect an external power supply, Vin > 7 Volts) • Red LED indicates power is enabled • Green LED debugging/UART status Software loading on LPC55S69: Import “lpcxpresso55s69_ntag5_passthrough_nolib” project (included in NTAG5boost_LPC55S69.zip) into MCUXpresso IDE. • Install SDK_2_12_0_LPCXpresso55S69. This SDK can be downloaded from • https://www.nxp.com/security/login?service=https%3A%2F%2Fmcuxpresso.nxp.com%2Flogin%2F  • Build project and flash a binary file using GUI Flash Tool. After flashing, reboot your board. Blue LED must be enabled which means tag is waiting for field to be detected. Under MCUXpresso: 1. Import project from file system 2. Select lpcxpresso55s69 project 3. Uncheck copy projects into workspace Software loading on PNEV5190B: • Unzip the “HIGHSPEED_PN5190_NTAG5boost1.zip” in a folder. • Import all projects inside “HIGHSPEED_PN5190_NTAG5boost1” project to MCUXpresso IDE • Install SDK_2.x_FRDM-K82F. Such SDK is included in project file tree: • nxp-connected-tags-pn5190\Platform\SDK_2.x_FRDM-K82F • Build project and flash a binary file using GUI Flash Tool. After flashing, reboot your board. Blue LED must be enabled which means reader is waiting for NTAG5 to be detected. • Start Debug session to see available bitrate options on the console. Under MCUXpresso: 1. Import project from file system 2. Select all the projects 3. Uncheck copy projects into workspace LED User Interface Specifications (same for LPCXpresso55S69 an PNEV5190B) • Steady blue - waiting for Tag - discovery loop, • Blinking green - passthrough transfer ongoing • Steady green - all data transferred successfully. • Steady red - error - tag lost during transfer. Menu options when two boards have NFC antennas facing each other: Two options of bitrate are available for transfer amount of data from host to NTAG5 Boost: ▪  standard 26.4 kbps or ▪  highest bit rate 212 kbps It is possible to configure amount of data to be exchanged between PN5190 and NTAG 5 boost (check option 3, and then choose among following file dimensions): ▪1KByte ▪2KBytes ▪10KBytes ▪512KBytes Demonstration flow: Once one of these options is selected, reader is ready to detect a tag. ▪ When tag is detected, reader configures selected bitrate and starts data exchange. ▪ Blinking green LED indicates transfer ongoing and the console shows a progress. Here are some results of transaction at the different bit rates and data sizes offered by this demonstrator: Data Size (Bytes) Selected bitrate (kbps) Result Bitrate (kbps) Transfer time (ms) 1024 26.4 2.8 357 1024 212 12.35 81 2048 26.4 2.8 714 2048 212 12.42 161 10240 26.4 2.7 3569 10240 212 12.41 806 512000 26.4 2.8 177739 512000 212 12.63 39576   High speed demo user manual can be also find attached to this article: 22-10-11 NXP - Connected Tags demonstrator User Manual.pdf Conclusions: This demonstrator HW & SW can show that high speed interaction can be achieved between PN5190 (NFC Front end) and NTAG 5 boost, making use of available commands described in product support package. Disclaimer: All SW available here is aimed only for evaluation purposes and NXP disclaims any direct or indirect liability damages, since referred SW bundles are not official part of PN5190/NTAG 5 boost standard product support packages available in nxp.com.  

AN13189 provides guidelines for the integration of PN7160 NXP NCI-based NFC controller to an Android platform from software perspective. But some developers found some compile issues when integrating PN7160 NFC package into Android 11.   This article describes how to fix the build error when you integrating PN7160 NXP NCI-based NFC controller to Android 11 system.  You need to follow the AN13189 (PN7160 Android porting guide ) first.  After you run the installation script install_NFC.sh, the following modification should be added to the source code. 1) Open package/apps/Nfc/nci/jni/Android.bp Add  "-DNXP_EXTNS=TRUE",   2 )  open system/nfc/src/Android.bp Add   "-DNXP_EXTNS=TRUE",     3 )   open packages/apps/Nfc/src/com/android/nfc/NfcService.java And add this: between isNfcSecureEnabled and setNfcSecure methods:             @Override         public IBinder getNfcAdapterVendorInterface(String vendor) {             if(vendor.equalsIgnoreCase("nxp")){                     return (IBinder) mNfcAdapter;             } else {                    return null;             }         }     Next, follow AN13189, complete the following steps in section 4.2. Then you can build the package successfully.  Thanks  @andraz_skupek .      

Using an alternative clock source to set up PN7462's contact interface clock , so that we have more options of the clock frequency.