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如何将 i.MX93 Cortex-M33 板和 SDK 导入 MCUXpresso IDE? 📌 背景: 我想开始使用 MCUXpresso IDE 在 i.MX93 Cortex-M33 (MCIMX93-EVK) 板上进行开发。我已经从恩智浦网站下载了SDK ZIP,但我无法成功导入板或使用其示例。 🛠️ 我做了什么? 从 mcuxpresso.nxp.com 下载 SDK ZIP: SDK_25_03_00_MCIMX93-EVK.zip 已打开MCUXpresso 集成开发环境(版本:请在此注明) 去了 已安装的 SDK> Import → 选择 ZIP 文件 SDK 出现在集成开发环境的已安装 SDK 下。 但是,当我进入 “导入SDK示例” 时,没有任何显示,或者我无法创建导入的项目的版本。 ❓ 我的问题: 将 i.MX93 Cortex-M33 板和 SDK 导入 MCUXpresso IDE 的正确和完整程序是什么,这样我就可以: 查看支持的板 访问演示/示例应用程序(如 hello_world) 无错误地版本和调试项目 🔍 其他说明: 我的目标是 i.MX93 的Cortex-M33 内核 我只想使用MCUXpresso 集成开发环境(而不是 IAR 或 VS Code)。 🧪 预期成果: 能够使用 MCUXpresso IDE 在 MCIMX93-EVK 板上导入和版本 cm33_core0 的 hello_world 或 led_blinky 等示例项目。 如果需要其他工具或配置,请告诉我。预先表示感谢! i.MX93EVK#i.mx93 cortex-m33i.MX93#MCUXpressoIDE ##MCUXpressoSDK Re: How to Import i.MX93 Cortex-M33 Board and SDK into MCUXpresso IDE? 你好@Manjunathb 我目前也在使用i.MX93 Cortex-M33。我安装了 MCUXpresso 集成开发环境,但在将 SDK 压缩文件下放到已安装的 SDK 视图时遇到了错误(根据指南)。 了解到您也在研究相同的 M33 核心,您是否介意与我们分享任何信息以及您目前的进展情况?我还应该为 VS 代码使用 MCUXpresso 吗? 如果您能分享一些关于如何开始 M33 开发的指南或程序,我将不胜感激。谢谢。 Re: How to Import i.MX93 Cortex-M33 Board and SDK into MCUXpresso IDE? 你好 Chavira, 我目前正在使用 i.MX93 Cortex-M33 内核,我知道这款设备不支持 MCUXpresso IDE,但推荐使用适用于 VS Code 的 MCUXpresso IDE。 我已经安装了:适用于 VS Code 扩展 的 mcuxPresso i.MX93 SDK 包 ARM GCC 工具链 而且我正在使用 J-Link 调试器。 请就以下几点为我提供指导: 如何将 i.MX93 Cortex-M33 SDK 正确导入 VS 代码?SDK 文件应放在哪里,扩展程序如何检测它们? 如何创建或打开 Cortex-M33 演示或模板项目(如 hello_world 或 led_blinky)? 如何配置版本设置(编译器、链接器路径等),以便使用 MCUXpresso VS Code 环境成功编译? 使用 J-Link 探头或 remoteproc(如果使用 Linux)闪存和调试已编译应用程序的正确方法是什么? 在使用 MCUXpresso for VS Code 时,是否有 i.MX93 特有的已知限制或额外步骤? 如果能提供完整的分步说明或相关文档链接,我将不胜感激。预先感谢您的支持! 最崇高的敬意, Manjunath Badiger Re: How to Import i.MX93 Cortex-M33 Board and SDK into MCUXpresso IDE? 好的 👍 感谢您的回复 Re: How to Import i.MX93 Cortex-M33 Board and SDK into MCUXpresso IDE? 嗨,@Manjunathb! 感谢您联系恩智浦支持中心! 遗憾的是,MCUXpresso IDE 与这种情况不兼容。不过,您也可以使用 MCUXpresso for VS Code,它支持并提供类似的功能。 致以最崇高的敬意, Chavira
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RW610 / RW612 Knowledge Hub The RW61x series is a highly integrated, low-power tri-radio wireless MCU with an integrated MCU and Wi-Fi® 6 + Bluetooth® Low Energy (LE) 5.4 / 802.15.4 radios designed for a broad array of applications, including connected smart home devices, enterprise and industrial automation, smart accessories and smart energy. The RW61x series MCU subsystem includes a 260 MHz Arm® Cortex®-M33 core with Trustzone™-M, 1.2 MB on-chip SRAM and a high-bandwidth Quad SPI interface with an on-the-fly decryption engine for securely accessing off-chip XIP flash. The RW61x series includes a full-featured 1x1 dual-band (2.4 GHz/5 GHz) 20 MHz Wi-Fi 6 (802.11ax) subsystem bringing higher throughput, better network efficiency, lower latency and improved range over previous generation Wi-Fi standards. The Bluetooth LE radio supports 2 Mbit/s high-speed data rate, long range and extended advertising.  The on-chip 802.15.4 radio can support the latest Thread mesh networking protocol. In addition, the RW612 can support Matter over Wi-Fi or Matter over Thread offering a common, interoperable application layer across ecosystems and products. NXP RW61x Block DiagramNXP RW61x Block Diagram Documents RW610 Datasheet: RW610 Datasheet RW612 Datasheet: RW612 Datasheet RW61x User Manual: UM11865: RW61x User Manual RW61x Register Manual: RM00278: RX16x Registers   Certifications FRDM-RW612 Radio Equipment Directive Declaration of Conformity  User Guide Getting Started with FRDM-RW612 Quick Start Guide - FRDM-RW612 UG10185: RW612 Matter-Zigbee Bridge User Guide UG10178: Matter Demo Using NXP Chip Tool App for FRDM-RW612 and FRDM-MCXW71  UG10612: NXP Wi-Fi and Bluetooth Feature Debug for FRDM-RW612 UG10182: NXP 802.15.4 Demo Applications for FRDM-RW612 UG10160: Getting Started with Wireless on FRDM-RW612 Board Running RTOS  UG10171: NXP Wi-Fi and Bluetooth Demo Applications for FRDM-RW61X     RW61x Modules Azurewave: RW612 - AW-CU570 is a highly integrated, low-power tri-radio Wireless RW612 MCU with an integrated MCU and Wi-Fi 6 + Bluetooth Low Energy (LE) 5.2 / 802.15.4 radios designed for a broad array of applications. RW610 - AW-CU598 is a highly integrated, low-power tri-radio Wireless RW610 MCU with an integrated MCU and Wi-Fi 6 + Bluetooth Low Energy (LE) 5.3 radios designed for a broad array of applications U-blox: RW612 - IRIS-W10 Series are small, stand-alone, dual-band Wi-Fi and Bluetooth Low Energy wireless microcontroller unit (MCU) modules. The modules are ideal for users looking to add advanced wireless connectivity to their end products. RW610 - IRIS-W16 Series are small, stand-alone, dual-band Wi-Fi and Bluetooth Low Energy wireless modules, with everything needed for integration into end-products. The modules are ideal for users looking to add advanced wireless connectivity to their end products.  Murata: RW612 - LBES0ZZ2FR-580 Murata’s Type 2FR is a small and very high-performance module based on NXP RW612 combo chipset, supporting IEEE 802.11a/b/g/n/ac/ax + Bluetooth LE 5.4 / IEEE 802.15.4. RW610 - LBES0ZZ2FP-580 Type 2FR/2FP is a family of small and highly integrated multi-radio modules with built-in high-performance MCU with advanced security features for connected smart devices in smart homes, enterprise and industrial automation, smart accessories, and smart energy. It supports the latest Matter smart home connectivity protocol. California Eastern Laboratories (CEL): RW612 - CMP4612 is a fully integrated Dual-Band, Tri-mode (Wi-Fi 6, BT5.4, 802.15.4) radio, that includes a host MCU, Flash, RAM, peripherals, and numerous interfaces (SDIO, UART, USB, Ethernet. SPI, I2C) to support both HOSTLESS (RTOS) and HOSTED (NCP mode) architectures. CEL's solution includes either an on-board antenna or connector.   Evaluation boards  FRDM-RW612 FRDM-RW612 is a compact and scalable development board for rapid prototyping of the RW61x series of Wi-Fi 6 + Bluetooth Low Energy + 802.15.4 tri-radio wireless MCUs. It offers easy access to the MCU’s I/O's and peripherals, integrated open-standard serial interfaces, external flash memory and on-board MCU-Link debugger. FRDM-RW612 Getting Started Getting Started with FRDM-RW612 FRDM-RW612 User Manual: UM12160: FRDM-RW612 Board User Manual Current Measurement configuration: Remove the 0-ohms resistor R103 Solder a couple of pins in JP5. When trying to measure the RW61x current consumption, connect your current meter using the pins in JP5. When using the FRDM board in normal operation, connect a jumper to the pins in JP5. David_Maciel_0-1746570099842.pngDavid_Maciel_0-1746570099842.png   u-blox   USB-IRIS-W1 The USB-IRIS-W1 development platform is built on the dual-band Wi-Fi 6 and Bluetooth LE module IRIS-W1, based on the NXP RW610/612 chip. The board is designed with a USB interface to simplify evaluation and prototyping directly from a PC. In addition to the IRIS-W1 module with integrated antenna, it also integrates four buttons, an RGB LED, and a USB/UART converter, to further support an easy evaluation. u-blox   EVK-IRIS-W1 The EVK-IRIS-W1 evaluation kit provides stand-alone use of the IRIS-W1 module series featuring the NXP RW610/612 chipset. Azurewave    AW-CU570-EVB Evaluation board for AW-CU570 module includes wireless MCU with Integrated Tri-radio Wi-Fi 6 + Bluetooth Low Energy 5.3 /802.15.4. Murata   2FR EVK Evaluation kit for Murata Type 2FR module (Murata part number LBES0ZZ2FR) includes 3 radios: Wi-Fi, BLE and 802.15.4. It is based on NXP’s RW612 chip. California Eastern Laboratories (CEL) CMP4612-2-EVB The CMP4612 Evaluation Board (CMP4612-2-EVB), based on the NXP RW612 chipset, features dual-band Wi-Fi 6, BLE 5.4 and 802.15.4 radios. The CMP4612 Evaluation Board includes an onboard Ethernet port and PHY hardware as well as an Arduino header, MCULink SWD, and USB ports. This board is designed to facilitate a seamless and efficient evaluation process for customers wanting a certified module for their end product.   Application Notes RM00287: Wi-Fi Driver API for SDK 2.16.100     The radio driver source code provides APIs to send and receive packets over the radio interfaces by communicating with the firmware images. This manual provides the reference documentation for the Wi-Fi driver and Wi-Fi Connection Manager.  UM12133: NXP NCP Application Guide for RW612 with MCU Host - User manual     This user manual describes: • The NXP NCP application for RW612 with MCU host platform i.MX RT1060 as example. • The hardware connections for one of the four supported interfaces to enable NCP mode on the NXP RW612 BGA V4 board (UART, USB, SDIO, or SPI). • The method to build and run the NCP applications on both the NCP host (i.MX RT1060) and the NCP device (RW612). The applications apply to Wi-Fi, Bluetooth Low Energy and OpenThread (OT)    UM12095:  NXP NCP Application Guide for RW612 with MPU Host - User manual      This user manual describes: • The NXP NCP application for RW612 with MPU host platform i.MX 8M Mini as example. • The hardware connections for one of the four supported interfaces to enable NCP mode on the NXP RW612 BGA V4 board (UART, USB, SDIO, or SPI). • The method to build and run the NCP applications on both the NCP host (i.MX 8M Mini) and the NCP device (RW612). The applications apply to Wi-Fi, Bluetooth Low Energy and OpenThread (OT).  AN14439: Migration Guide from FRDM-RW612 Board to Third-Party Module board This Application note provides an overview of what it means to migrate the application to a different board with different flash and pSRAM AN14111: Target Wake Time (TWT) on RW16x This application note describes the target wake time feature and provides examples for RW61X AN13006: Compliance and Certification Considerations This application note provides guidance and tips on how to test products on NXP Wi-Fi devices for regulatory compliance. AN13049: Wi-Fi/Bluetooth/802.15.4 M.2 Key E Pinout Definition This Application note defines M.2 usage for both NXP Wi-Fi/Bluetooth and Tri-Radio M.2 module design AN14489 – Wi-Fi Firmware Automatic Recovery on RW61x Describes Wi-Fi automatic recovery feature as well as how to enable and verify it on RW61x SDK. AN14464 - Low Power Checklist RW61x Family This document provides an overview on how to use the low power consumption features of the RW61x. AN13869 - RW61x Flashloader for Custom Flash Devices: This document provides guidance to program the application image and boot up RW61X from a third party FlexSPI NOR flash device.   AN14125 - Manufacturing Software Development Kit API Specification: This document explains the Labtool Software Development Kit (SDK) used to automate manufacturing test programs.   AN14002 - RW61x Design Guide: Provides design guidelines for RW61x RF: AN14476 - NXP Dual PAN Feature and Performance ResultsThis document provides a comprehensive exploration of the Dual Personal Area Network (Dual-PAN) feature on NXP Wireless Connectivity products implementing IEEE 802.15.4 low-rate wireless protocol area network standard. AN13639 - Calibration Structure for RW61X: This document describes the RF calibration parameters and data structure used to store calibration/configuration data for RW61x. The document explains how to adjust the RF calibration parameters to attain tighter tolerances. AN14282 - RF Test Mode on FreeRTOS:  This document provides an overview of how to enable and use the Radio Frequency (RF) test mode on a Real-time Operating System (RTOS)-based host. Using the RF test mode feature, users can easily set RF parameters, such as the operating channel, TX power, and channel bandwidth for regulatory compliance testing. AN14001 - RW61x TCP Throughput Optimization: This document explains how to optimize TCP throughput for RW61X with MCUXpresso SDK and analyze the test results after tuning with different parameter combinations. AN14463 - Antenna Diversity: This application note describes the antenna diversity feature capabilities of NXP wireless SoCs. Implementation of antenna diversity requires appropriate external hardware (Single Dipole Pole Throw (SPDT) or Double Dipole Pole Throw (DPDT) switches) in the customer design.  AN14714 - Wi-Fi Firmware Download Modes for FreeRTOS:  This document introduces the firmware download process and configuration for these two modes. AN14281 - Channel State Information (CSI) on FreeRTOS: This document explains how to get the CSI records from the Wi-Fi packets in STA mode AN13681 - Wi-Fi Alliance Derivative Certification Process for RW61x: The document presents the Wi-Fi Alliance derivative certification process. AN14466 - Antenna Auto Detection: Describes the antenna auto detection feature AN14121 - Coexistence Overview for RW61X:  Provides an overview of coexistence between Wi-Fi and Bluetooth LE or 802.15.4 radios. Security: AN14544 – EdgeLock 2GO Services for MPU and MCU This application note introduces various methods that the EdgeLock 2GO service can be used with MCU and MPU devices and the features available for each method. AN13813 – Secure Boot on RW61x Describes how to generate and run the secure boot (signed image) on RW61x. AN13814 – Debug Authentication on RW61x Describes the steps for debug authentication using the secure provisioning SDK tool. AN14705  - Using EdgeLock 2GO for Matter Provisioning on RW612 Devices: This document explains how to use the NXP EdgeLock 2GO service to provision an RW612 device for Matter. AN15038 - EdgeLock 2Go Provisioning MCUs via Product Type using Secure Provisioning (SEC) Tool: This document offers an outline of the EdgeLock 2GO platform and discusses the "Device provisioning via product type" flow. The document focuses on the initial device provisioning using secure objects from the EdgeLock 2GO cloud server. AN14670 - EdgeLock 2GO Provisioning via SPSDK for MCUs: This document offers an outline of the EdgeLock 2GO platform and discusses the “Device provisioning via proxy” flow. The document focuses on the initial device provisioning using secure objects from the EdgeLock 2GO cloud server.  AN14624 EdgeLock 2GO Provisioning via Secure Provisioning Tool (SEC) for MCUs: This document offers an outline of the EdgeLock 2GO platform and discusses the "Device provisioning via proxy" flow. Import Wrapped Blob using ELS Cryptolib - Uses ELS Cryptolib to import a blob from OTP that was wrapped using HSM_STORE_KEY trust provisioning command.  Import Wrapped Blob using PSA APIs - Uses PSA API to import a blob from OTP that was wrapped using HSM_STORE_KEY trust provisioning command. Training FRDM-RW612 Training Wi-Fi 6 Tri-Radio in a secure i.MX RT MCU RW61x Series Training - NXP Community   Equipment Wireless Equipment: This article provides the links to the wireless equipment to help you accelerate your project development Development Tools  SDK builder The MCUXpresso SDK brings open-source drivers, middleware, and reference example application to speed your software development. NXP MCUXpresso MCUXpresso IDE offers advanced editing, compiling and debugging features with the addition of MCU-Specific debugging and supports connections with all general-purpose Arm Cortex-M.  VSCode MCUXpresso for Visual Studio Code (VS Code) provides an optimized embedded developer experience for code editing and development. Zephyr RTOS  The Zephyr OS is based on a small-footprint kernel designed for use on resource-constrained and embedded systems: from simple embedded environmental sensors and LED wearables to sophisticated embedded controllers, smart watches, and IoT wireless applications. NXP Application Code Hub Application Code Hub (ACH) repository enables engineers to easily find microcontroller software examples, code snippets, application software packs and demos developed by our in-house experts. This space provides a quick, easy and consistent way to find microcontroller applications. NXP SPSDK Is a unified, reliable, and easy to use Python SDK library working across the NXP MCU portfolio providing a strong foundation from quick customer prototyping up to production deployment. NXP SEC Tool The MCUXpresso Secure Provisioning Tool us a GUI-based application provided to simplify generation and provisioning of bootable executables on NCP MCU devices. NXP OTAP Tool Is an application that helps the user to perform an over the air firmware update of an NXP development board. SDK Examples for Wireless MCUs The wireless examples feature many common connectivity configurations.   Useful Links Bluetooth Interested in Bluetooth technology? Bluetooth® Low Energy Primer – Essential reading for understanding BLE fundamentals. Bluetooth® Specifications – Full list of standards, protocols, and technical documents. Bluetooth Feature Overview Bluetooth_5.0_Feature_Overview  Bluetooth_5.1_Feature_Overview  Bluetooth_5.2_Feature_Overview Bluetooth_5.3_Feature_Overview Bluetooth_5.4_Feature_Overview Bluetooth_6_Feature_Overview   FRDM-RW612
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使用 J-Link 与 MIMXRT1170-EVKB 注意:有关类似的 EVK,请参阅: 使用 J-Link 与 MIMXRT1060-EVKB 或 MIMXRT1040-EVK 使用 J-Link 与 MIMXRT1060-EVK 或 MIMXRT1064-EVK 使用 J-Link 与 MIMXRT1160-EVK 或 MIMXRT1170-EVK 本文介绍了在该 EVK 上使用 J-Link 调试探针的详细方法。有两种方式:将板载 MCU-Link 调试探针更新为 Segger J-Link 固件,或将外部 J-Link 调试探针连接到 EVK。使用板载调试电路可免去对额外调试探针的需求。本文将详细介绍上述任一 J-Link 方式的使用步骤。 MIMXRT1170-EVKB jumper locationsMIMXRT1170-EVKB 跳线位置 使用外部 J-Link 调试探针 Segger 提供多种J-Link 探针选项。要使用这些探针配合这些 EVK,请按以下配置设置 EVK: 在JP5上安装一个跳线,以断开 SWD 信号与板载调试电路的连接。默认情况下,此跳线处于断开状态。 为EVK供电:默认选项是将电源连接到桶形插孔J43,并将电源开关SW5设置为开启位置 (3-6)。当EVK正常供电时,SW5旁边的绿色LED D16将会亮起。 将 J-Link 探头连接到 J1,20 针双排 0.1 英寸排针。 使用板载 MCU-Link 搭配 J-Link 固件 安装 MCU-Link 安装程序以获取驱动程序和固件更新工具 断开 EVK 上的所有 USB 连接线 为EVK供电:默认选项是将电源连接到桶形插孔J43,并将电源开关SW5设置为开启位置 (3-6)。当EVK正常供电时,SW5旁边的绿色LED D16将会亮起。 在 JP3 处安装跳线以强制 MCU-Link 进入 ISP 模式 将 USB 电缆连接到 J86,连接到 MCU-Link 调试器 转到 MCU-Link 软件包安装中的脚本目录,并双击运行 program_JLINK.cmd (Windows) 或 program_JLINK (Linux/MacOS) 脚本。按照屏幕上的说明操作。在 Windows 中,此脚本通常安装在 C:\nxp\MCU-LINK_installer_3.122\scripts\program_JLINK.cmd。 拔下 J86 处的 USB 线缆 移除 JP3 处的跳线 将 USB 线缆重新连接到 J86。现在,MCU-Link 调试器应以 J-Link 模式启动。 移除跳线 JP5,以连接来自 MCU-Link 调试器的 SWD 信号。默认情况下,此跳线处于断开状态。
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PTN3460, PTN3460I FAQs Q1: Why DisplayPort to LVDS adapter? DPRX-LVDS is an (embedded) DisplayPort to LVDS bridge device that enables connectivity between an (embedded) DisplayPort (eDP) source and LVDS display panel. It processes the incoming DisplayPort (DP) stream, performs DP to LVDS protocol conversion and transmits processed stream in LVDS format. NXP offers two eDP-LVDS devices: 1. PTN3460 is commercial grade, 0 – 70 C. It is in 56-pin HVQFN package, 7 mm x 7 mm, 0.4 mm pitch. Supports pixel clock frequency from 25 MHz to 112 MHz. 2. PTN3460I is industrial grade, -40 – 85 C. It is in 56-pin HVQFN package, 7 mm x 7 mm, 0.4 mm pitch. Supports pixel clock frequency from 6 MHz to 112 MHz. Q2. How to configure eDP-LVDS device?   The eDP-LVDS has embedded microcontroller and on-chip Non-Volatile Memory (NVM) to allow for flexibility in firmware updates. Both PTN3460 and PTN3460I have a built in configuration table in internal 1K SRAM, which allows users to program seven EDID and 128 configuration registers through M/S I2C-bus. Please follow the programming guides below for these devices. 1. AN11128 – Programming Guide for PTN3460 2. AN11606 – Programming Guide for PTN3460I Q3. What is maximum resolution DP-LVDS can support? The available bandwidth over a 2-lane HBR DisplayPort v1.4 link limits pixel clock rate support to: 1. 1-lane DP with single LVDS bus supports 800x600 @ 60 Hz display, 40 MHz pixel clock. 2. 1-lane DP with dual LVDS bus supports 1366x768 @ 60 Hz display, 85.5 MHz pixel clock. 3. 2-lane DP with single LVDS bus operation up to 112 mega pixel per second – supports 1440x900 @ 60 Hz resolution display. 4. 2-lane DP with dual LVDS bus operation up to 224 mega pixel per second – supports 1920x1200 @ 60 Hz resolution display. Q4. How to update the FW? FW for eDP-LVDS devices can be updated by the following methods: 1. Flash over AUX (FoA) – This is an executable window utility that can only run under Windows OS. FW is updated through DP AUX channel. AN11133 – PTN3460 FoA utility user’s guide. 2. Flash over DOS (FoD) – This is an executable DOS utility that can run under DOS without OS. FW is updated through M/S I2C bus. 3. Flash over I2C – FW is updated through external I2C device that is plugged in a M/S I2C header. Q5. How to check the FW version? FW version can be read out with DPCD utility that runs under Windows OS. Please follow DPCD Tool User Manual V1.0. Q6. How many DP lanes supported in NXP DP to LVDS bridge device? NXP DP to LVDS bridge device supports 2 lanes HBR/RBR. Q7. What does HBR/RBR mean? HBR means “High Bit Rate”, it runs 2.7 Gbit/s. RBR means “Reduced Bit Rate”, it runs 1.62 Gbit/s. Q8. What is DP AUX channel? DP AUX channel is used for communication channel between DP source and DP sink device. Q9. What is DP source device? DP source device is DP signal transmitter. Q10. What is DP sink device? DP sink device is DP signal receiver.
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OV5640 Interfacing with i.MX RT1170 (Without Display) Image Capture and Streaming to Desktop Hello, I am using the i.MX RT1170-EVKB board, and my goal is to capture images from the OV5640 camera and view either the captured image or a live video stream on my desktop PC without using an LCD display. I have tried the MIPI CSI SDK examples and was able to capture image data in RAW format. However, I am facing several issues. The captured output is in RAW format, and I could not find any documentation explaining how to properly convert or view these images. The captured images appear to have incorrect colors or filter-like artifacts, making it difficult to verify whether the camera output is correct. I could not find any official documentation, application notes, or video tutorials describing the complete workflow for capturing images from the OV5640 and viewing them on a desktop PC. There is no clear reference explaining how to stream the camera output over Ethernet or USB without using the onboard display. I also tried the sd_jpeg example, but I encountered multiple problems. During integration, the project reported missing JPEG library configuration files such as jconfig.h. After resolving some build issues, I continued to encounter compilation and integration errors while combining the JPEG encoder with the MIPI CSI camera example. I was unable to generate a valid JPEG image from the captured camera frame. My objective is to: Interface the OV5640 camera with the i.MX RT1170-EVKB board without using an LCD display. Capture images and transfer them to my desktop PC for viewing. Stream live video from the camera to my desktop PC over Ethernet, if supported. I would appreciate your guidance on the following questions: Is there an official SDK example or reference project for this use case? Is there any documentation explaining the complete image capture pipeline from the OV5640 through MIPI CSI, memory, JPEG or RAW processing, and Ethernet or USB transfer to a desktop PC? Is live streaming over Ethernet supported on the RT1170-EVKB? If yes, could you recommend the appropriate SDK example or middleware? Are there any known issues with the sd jpeg example or any additional configuration steps required to integrate it with the MIPI CSI camera examples? Any guidance, documentation, or reference projects would be greatly appreciated. Thank you for your support. Re: OV5640 Interfacing with i.MX RT1170 (Without Display) Image Capture and Streaming to Desktop HI @Sureshk123, We don't have an official example project or reference design for your application. That said, from my understanding, I would recommend you tackle the complete application as follows: Camera capture path (OV5640 > MIPI CSI > cameraBuffer) This part we do have an example application, which are the aforementioned MIPI CSI SDK examples. Keep in mind that, as per ERR051248: "Video Mux Controller (VIDEO_MUX), raw data and YUV422 (10 bit) formats to the MIPI_CSI2 block are not supported." Using the parallel CSI is an optional workaround, either that or a video decoder. Once you have the adequate data on your cameraBuffer, you can integrate example projects from our SDK based on USB or lwIP to transport this data to your PC. I would recommend looking into JPEG encoding only after the buffer is known to work. BR, Edwin.
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Building AI/ML Devices at the Edge? Start with FRDM From smart sensing and anomaly detection to computer vision, voice recognition, and multimodal GenAI—AI/ML use cases are rapidly moving onto the device. But if you're an engineer getting started, the real questions usually are: What hardware products should I use? What NXP tools actually work for embedded AI applications? Do I need the cloud for anything? Let’s break it down ! Why Edge AI is important? Running AI models directly on-device enables: Real-time decisions (low latency) Better security Offline operation (no cloud dependency) Optimized power consumption That’s exactly where the FRDM development platform comes in Quick Positioning: From MCU to Edge AI Processor Category Boards AI Capability Level Typical Use Case MCU (Low Power Edge ML) FRDM-MCXA156 + ⭐ sensor AI, TinyML MCU + Neural Acceleration FRDM-MCXN947 ++ ⭐⭐ Edge AI with vision/audio, TinyML Application Processor (Entry Edge AI) FRDM-IMX93 +++ ⭐⭐⭐ HMI + AI inference High-Performance Edge AI FRDM-IMX8MPLUS ++++ ⭐⭐⭐⭐ Vision AI, Advanced HMI Next-Gen AI + Safety FRDM-IMX95 / PRO +++++ ⭐⭐⭐⭐⭐ Gen AI, Advanced Edge Computing AI/ML applications can run on general-purpose hardware, but leveraging dedicated hardware acceleration significantly improves performance, enables faster results, and reduces power consumption. Below is a reference list of FRDM development boards that support AI/ML applications, helping you choose the right platform based on your target use case   Board Positioning AI Acceleration Hardware Capabilities (AI-relevant) Best For FRDM-MCXA156 Entry-level MCU (TinyML)  No NPU (CPU-only) Sensors via Expansion headers (Arduino, MikroBUS, Pmod) Parallel display support Sensor ML Anomaly detection Basic TinyML FRDM-MCXN947 MCU with neural acceleration NPU Parallel camera interface (basic) Parallel display Audio (PDM/I2S) Voice AI  Low-res vision Object classification Anomaly Detection FRDM-IMX93 Entry Edge AI MPU NPU  MIPI CSI camera Display (MIPI DSI/LVDS) Audio + connectivity Smart HMI Light vision AI Edge gateways FRDM-IMX8MPLUS Advanced Multimedia + Edge AI platform NPU Multi-camera (MIPI CSI) High-res display (HDMI/DSI)  Audio DSP Connectivity (Wi-Fi, BLE, Ethernet) Some PCIe expansion Computer vision Object detection Industrial AI FRDM-IMX95 Next-gen AI + real-time MPU Next-gen NPU + heterogeneous compute Multi-camera pipelines Advanced HMI Industrial connectivity M.2 expansion(Up to 1 AI accelerators) Robotics Industrial AI Safety applications FRDM-IMX95-PRO Full-featured AI dev platform High-performance NPU + scalable AI (Ara240 Discrete NPU)  Multi-camera Advanced display M.2 expansion (Up to 2 AI accelerators) Advanced AI prototyping Gen AI Edge servers Edge computing  Software and tools for ML/AI applications   GoPoint GoPoint accelerates AI/ML evaluation on FRDM platforms powered by i.MX application processors by providing a ready-to-use, graphical environment with pre-integrated demos. Developers can quickly run applications such as image classification, object detection, and voice recognition directly on the hardware without complex setup. These demos are already optimized for available compute resources—including CPU, GPU, DSP, and NPU—allowing users to immediately visualize performance and understand how AI workloads map to the system. This makes GoPoint an ideal starting point for exploring edge AI capabilities and validating use cases before moving into full application development. Application Code Hub (ACH) Application Code Hub complements rapid evaluation tools by offering a centralized repository of reusable, production-oriented software examples for FRDM boards. It provides full application projects, source code, and documentation that developers can directly import into MCUXpresso IDE or VS Code. With filtering based on use case—such as vision AI, audio processing, or anomaly detection, ACH enables developers to quickly find and customize reference implementations. This helps bridge the gap between proof-of-concept and real product development, significantly reducing development time while enabling scalable AI/ML application design. Application Code Hub Guide eIQ Time Series Studio (TSS) eIQ Time Series Studio is purpose-built for developing AI models based on sensor and time-series data, making it highly relevant for FRDM-based edge intelligence applications. It provides a guided workflow for data collection, labeling, model training, and validation, all optimized for MCU-class devices. Developers can easily transform raw sensor data—such as vibration, motion, or environmental signals—into deployable machine learning models for use cases like predictive maintenance, anomaly detection, and condition monitoring. With built-in analytics and seamless deployment to FRDM boards, TSS simplifies the path from data to intelligent behavior on the edge. eIQ AI/ML Software Environment The eIQ software environment is the foundation that enables AI/ML development across the entire FRDM ecosystem, providing an end-to-end workflow from model creation to on-device inference. It supports importing and optimizing models from popular frameworks such as TensorFlow, PyTorch, and ONNX, and integrates tightly with MCUXpresso and Linux-based environments. eIQ includes tools for model optimization—such as quantization and pruning—as well as runtime engines designed for efficient execution on CPUs, DSPs, and NPUs. By combining these capabilities with hardware acceleration available on FRDM boards, eIQ allows developers to build, deploy, and run real-time AI applications directly on embedded devices with minimal reliance on cloud computing. eIQ Training Curriculum FQA What is an NPU ? A Neural Processing Unit (NPU) in the FRDM platform is a dedicated hardware accelerator integrated into certain microcontrollers (such as the MCX-N family) that is specifically designed to execute machine learning and neural network workloads efficiently. Unlike general-purpose CPUs, the NPU is optimized for the mathematical operations used in AI models, enabling significantly faster inference—up to tens of times higher throughput—while consuming less power. In FRDM boards, the NPU works alongside the CPU and DSP to offload complex AI computations, allowing real-time processing for applications such as image recognition, voice detection, and sensor-based anomaly detection directly on the device. Combined with NXP’s eIQ® software environment, the NPU becomes the core execution engine that transforms FRDM platforms into efficient, low-power edge AI systems capable of running intelligent applications without relying on the cloud What is a Discrete NPU? A Discrete Neural Processing Unit (DNPU) is a standalone AI accelerator designed specifically to execute machine learning and neural network workloads efficiently. Unlike integrated NPUs that are built into a processor, a DNPU exists as a separate chip or module that can be added to a system. It offloads compute-intensive AI operations, such as matrix multiplications and deep learning inference from the main CPU or GPU, delivering significantly higher performance and better energy efficiency. This makes DNPUs ideal for advanced edge AI applications like computer vision, generative AI, and real-time multimodal processing. How do I use Ara modules (DNPU) with FRDM boards? Ara modules, based on NXP’s DNPU technology, can be used with compatible FRDM boards to extend AI processing capabilities. On supported i.MX-based FRDM platforms such as FRDM-IMX95 or FRDM-IMX95-PRO—developers can connect Ara modules (e.g., Ara240) through the M.2 expansion interface. Once connected, the Ara module works alongside the main processor to offload complex AI workloads, enabling faster inference, lower latency, and improved power efficiency. Using the eIQ® AI software environment, developers can prototype and validate models on FRDM, then scale performance by enabling Ara acceleration, creating a seamless path from development to high-performance edge AI deployment. From TinyML to advanced edge AI and GenAI, discover how to build intelligent systems directly on-device with FRDM, no cloud dependency required. FRDM-IMX8 FRDM-IMX8MP FRDM-IMX9 FRDM-MCXN i.MX Application Processors MCU
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RT1064 I2C 通信异常,频率为 400kHz RT1064 设备的 I2C2 接口连接到模块 A。在 400kHz 频率下出现通信异常,但在 100kHz 频率下工作正常。 1. 将同一系列中不同型号的模块 B 以 400kHz 的频率连接没有问题。 2. 从波形上看,这相当于主机时钟在连接到模块 A 后被拉伸然后恢复时发生的异常情况。 PS:将该设备的 I2C 驱动程序移植到另一台 1064 设备上,测试模块 A,在 400k 功耗下未发现问题。 原因可能是什么? 图 1 模块 A 逻辑分析仪在 400kHz 下的异常波形 foreverwlh2025_0-1782181859478.png 图 2:模块 A 在 100kHz 下的逻辑分析仪波形 foreverwlh2025_1-1782181977222.png 图3:模块B在400kHz时的波形 foreverwlh2025_2-1782182029028.png i.MX RT106x Re: RT1064 I2C communication abnormality at 400kHz 你好@foreverwlh2025 , 感谢您的进一步说明——这是一个非常重要的发现。   根据您的观察,该问题似乎更有可能是由于两级 ADUM1251 隔离链路导致的 400 kHz I2C 时序裕量不足,而不是模块 A 本身的异常。 即使上升时间在规格范围内,在 RT1064 上,我们仍然建议检查 LPI2C 主侧 400 kHz 配置,特别是 MCFGR2[FILTSCL/FILTSDA] 和 MCCR0/MCCR1,因为 RT1064 上的主同步延迟不仅受上升时间的影响,还受数字滤波器和定时参数设置的影响。 我们建议您阅读项目中实际使用的配置,并将其与 RT1064 参考手册第 47 章中的表 47-5“LPI2C 示例时序配置”进行比较。 请特别检查以下设置是否与您所选时钟条件的示例值相符: I2C模块时钟源 目标波特率:400Kbps 预分频 FILTSCL/FILTSDA SETHOLD CLKLO CLKHI DATAVD 希望对你有帮助 顺祝商祺! 5月 Re: RT1064 I2C communication abnormality at 400kHz 补充信息:昨天在定位方面取得了一些进展: 我们的硬件扩容计划如下: 主板:RT1064--- ADUM1251 3.3V 至 5 V 子板:ADUM1251-模块A 5V转3.3V 经验证,在硬件链路的两层中添加 ADUM1251 后,模块 A 的通信出现异常。但移除 ADUM1251 后,通信在 400k 处恢复正常。造成这种情况的原因可能是什么? PS:我们的硬件工程师认为 ADUM1251 只会增加通信延迟,不会产生其他影响。 Re: RT1064 I2C communication abnormality at 400kHz 你好,@mayliu1 我们的产品即将发布,我们已经调查这个问题好几天了。如果您能尽快回复,我们将不胜感激! Re: RT1064 I2C communication abnormality at 400kHz HI 补充信息 1.我们的两位硬件工程师使用示波器检查了故障波形,上升时间符合要求,在 100ns 以上。 2. 我将 I2C 初始化和读写功能驱动程序移植到另一种 RT1064 设备,并测试了模块 A,没有发现任何问题。 下图显示了另一个设备模块 A 的测试逻辑分析仪的波形。 foreverwlh2025_0-1782194338022.png 怀疑: 1.如果时钟在拉伸后恢复异常,还有哪些其他原因可能导致这种情况? 2. 是否有专门的功能来设置上次回复中提到的 MCFGR2 等设置?我没有看到在 I2C 初始化过程中需要设置任何接口。 ----如果上升时间满足要求,我们是否就不需要考虑这些寄存器设置了? Re: RT1064 I2C communication abnormality at 400kHz 嗨@foreverwlh2025 , 非常感谢您对我们产品的关注以及对我们社区的使用。 我认为这很可能不是 A 模块的问题,而是该特定 RT1064 LPI2C2 总线上的 400 kHz 时序裕量问题。 在 RT1064 上,LPI2C 时序受总线上升时间、总线负载、上拉电阻和毛刺滤波器延迟的影响。 RT1064RM 参考手册指出,上升时间越大,同步延迟就越高。(参见第 47.3.1.4 章)时序参数) 主故障滤波器 MCFGR2[FILTSCL/FILTSDA] 必须设置,使其延迟保持在最小 SCL 低/高周期以下,RT1064 在 MCCR0/MCCR1 中提供了 400 kbps 定时设置的示例。请查看表 47-5。LPI2C 示例时序配置 mayliu1_0-1782186916949.png 因此,如果模块 A 使总线边沿稍微变慢或改变有效负载,则总线可能在 400 kHz 时发生故障,但在 100 kHz 时仍然可以工作。 希望对你有帮助 顺祝商祺! 5月 Re: RT1064 I2C communication abnormality at 400kHz RT1064 参考手册中没有列出 400 kbps 的 10 MHz LPI2C 功能时钟。 虽然可以使用此时钟生成 400 kbps 波特率,但应根据 I2C 规范仔细验证自动生成的定时参数,特别是 tLOW、tHIGH、建立/保持定时和数据有效定时。 为降低设计风险,建议使用经过验证的时钟源,例如 48 MHz,如参考手册所示。 Re: RT1064 I2C communication abnormality at 400kHz 以下是打印配置。可能需要调整哪个参数? PS:显然是由于自动接口分配造成的 foreverwlh2025_0-1782704741259.png Re: RT1064 I2C communication abnormality at 400kHz 你好@foreverwlh2025 , 您可以尝试直接设置寄存器。 例如,当使用 60 MHz I2C 时钟时,可以采用以下配置。 mayliu1_1-1782813580334.png 希望对你有帮助 顺祝商祺! 5月 Re: RT1064 I2C communication abnormality at 400kHz 当前的 I2C 时钟是基于 SDK2_13_0-EVK-MIMXRT1064 板 \ boards \ evkmimxrt1064 \ river_deamples \ lpi2c 目录中的示例配置进行配置的。 #define LPI2C_CLOCK_SELECT (0U) #define LPI2C_CLOCK_DIVIDER (5U) CLOCK_SetMux(kCLOCK_Lpi2cMux, LPI2C_CLOCK_SELECT); CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_DIVIDER); 我该如何修改才能获得精确的 8MHz 或 48MHz 频率?(时钟树似乎看不见) Re: RT1064 I2C communication abnormality at 400kHz 我尝试将频率修改为 60MHz 和 8MHz,但仍然无效。下图中的红色方框显示的是修改后打印的值,这些值与手册中的值不同。 foreverwlh2025_0-1782813239395.png Re: RT1064 I2C communication abnormality at 400kHz 你好@foreverwlh2025 , 配置 I2C 时钟有多种方法。 建议您尝试 8 MHz 和 60 MHz,因为这两个时钟设置相对容易实现。 我正在使用 SDK 演示版: "evkmimxrt1064_lpi2c_edma_b2b_transfer_master" 方法一:将 LPI2C 时钟源配置为 60 MHz 只需将时钟分频器设置为 0 即可。 mayliu1_3-1782806044116.png 方法二:将 LPI2C 时钟源配置为 8 MHz 使用 MCUXpresso IDE 时钟工具并按如下所示进行配置。选择 OSC_CLK 作为时钟源,并将分频器设置为 3,这将为 LPI2C (I2C) 模块生成 8 MHz 时钟。 mayliu1_0-1782804733641.png mayliu1_4-1782806209573.png 希望对你有帮助 顺祝商祺! 5月 Re: RT1064 I2C communication abnormality at 400kHz 如图所示,我尝试修改寄存器设置以匹配参数,但在 60MHz 下性能没有提升;即使是性能良好的模块在 8MHz 下也无法正常工作。 foreverwlh2025_0-1782882582056.png Re: RT1064 I2C communication abnormality at 400kHz 原因已查明,出现问题的模块将在 400k 时出现时钟拉伸现象。 但是我们使用的隔离器芯片不支持 SCL 双向。更换隔离芯片后, 测试结果正常;此订单可以结案。
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What are industrial Ethernet protocols? Explanation of EtherCAT, PROFINET, and EtherNet/IP (Japanese blog) table of contents Introduction What is industrial Ethernet? Basic structure of industrial networks 1. EtherCAT (Ultra-high speed, low latency orientation) 2. Profinet (Flexibility/Interoperability) 3. Ethernet/IP (IT affinity/standardization) summary Introduction   Communication in industrial equipment is rapidly shifting from traditional fieldbuses to Ethernet-based systems. At the heart of this shift is the Industrial Ethernet protocol .   This article focuses on three widely used protocols and clearly explains the differences in their technical structure and design philosophy . EtherCAT PROFINET EtherNet/IP (※Evaluation and implementation methods will be explained in a separate article.) What is industrial Ethernet ?   In short, industrial Ethernet is a communication technology that enhances "real-time performance," "robustness," and "diagnostic capabilities" compared to general-purpose Ethernet. Standard Ethernet has the following challenges in industrial applications:   This is a best-effort communication method, and the delay varies depending on the load and switching processes. Frame loss (packet loss) may occur. TCP/UDP/IP is not designed for real-time control. To address these challenges, industrial Ethernet protocols employ unique approaches to achieve the following requirements:   Real-time communication Synchronization control Redundant configuration Diagnostic function   ■ Key points for understanding industrial Ethernet: OSI model   One of the key points in understanding industrial Ethernet is the perspective of "at which layer real-time performance is achieved," and the OSI reference model is helpful in understanding this. The OSI model is a framework that divides communication functions into seven layers, and each layer plays a different role, from the transmission of physical signals to application processing. Industrial Ethernet achieves real-time performance and reliability by using each of the OSI layers as a base and extending and optimizing specific layers for each protocol. OSI reference model in industrial Ethernet: hierarchy name The role of industrial Ethernet 7 application Contents of communication data (device control, status, settings) 6 presentation Data encoding, compression, and encryption 5 session Establishing, maintaining, and terminating communications 4 transport Communication quality control (TCP/UDP), data delivery assurance. 3 network Routing by IP address (determining packet destination) 2 Data Link Data delivery by MAC address, creation of Ethernet frames 1 physics Cables (Cat5e/6, etc.), connectors, and physical signal transmission. Layers used for each industrial Ethernet protocol: ZHOU_XIAO_0-1779432108374.png Characteristics of each Ethernet protocol: protocol hierarchy Features EtherCAT 2 High speed without using IP PROFINET RT/IRT is L2 NRT L3/4 Differentiated usage between RT and IRT. EtherNet/IP 3/4 Standard Ethernet based These differences in characteristics directly lead to the following: Speed (real-time performance) Implementation cost Applicable use   Basic structure of industrial networks   Industrial Ethernet generally shares a common basic structure regardless of the protocol, and the three protocols discussed in this article (EtherCAT, PROFINET, and EtherNet/IP) are no exception. ■ System and Device Structure   Industrial networks can be broadly divided into the "controller side" and the "device side."   Main device (controller): It plays a central role in controlling the entire network. Starting communication and setting connection parameters Sending output data and receiving input data Communication management and termination process Typical examples: PLCs, industrial PCs Sub-device (device): Respond to connection requests and send and receive necessary data. Receiving output data and transmitting input data Self-notification on the network Alarms sent as needed Typical examples: sensors, servos, actuators ■ Communication method: cyclic communication vs. aperiodic communication Once a connection is established, I/O data is continuously exchanged between the MainDevice and SubDevice at very short intervals. This communication is divided into "periodic communication" and "aperiodic communication" depending on the application. Cyclic communication (periodic communication) Application: For real-time control - Essential for applications requiring real-time performance, such as motor control and I/O control. Acyclic communication Uses: Configuration, diagnostics, and event management. - Used for reading and writing configuration data, diagnostic information, and notifications of unexpected events. ■Key concept supporting real-time performance: Synchronization ( Clock ) In industrial systems, it is extremely important that "all devices operate on the same time standard." For example, if multiple devices acquire data at different times, Δt₁, Δt₂, and Δt₃, as shown in the diagram below, the information received by the controller (PLC) will not be data from the same time, but rather "separate snapshots" that are staggered in time. the result: Occurrence of positional misalignment Incorrect control judgment In particular, critical synchronization errors in motion control This can lead to problems like these. Therefore, in Industrial Ethernet , a mechanism for synchronizing clocks between devices is a crucial element. ZHOU_XIAO_2-1779431627985.png Summary of the technical comparison of the three protocols   EtherCAT PROFINET EtherNet/IP Operating Organization Bechoff / ETG (EtherCAT Technology Group) Siemens / PNO (PROFIBUS & PROFINET International) Rockwell / OVDA (Open Device Net Vendors Association) Communication method Summary frame (SubDevice reads and writes data as it passes through the frame) Layer 2-based real-time communication (RT/IRT) CIP: Explicit (TCP) / Implicit (UDP) communication model Main use Motion control, ultra-high-speed control General-purpose FA, process control, and a wide range of industrial applications Factory automation, PLC networks, robots Cycle time ~31.25μs level (implementation dependent, very fast) RT: A few milliseconds IRT: 31.25μs (implementation-dependent, TSN/IRT) Generally, 10ms level (UDP-based) Synchronization method Distributed Clock (DC) IRT: Precision Synchronization (PTCP) CIP Sync (IEEE1588) Device Model PDO / SDO (CANopen over EtherCAT) Slot / Subslot (GSDML) Class / Instance / Attribute Object Model topology Line, tree, ring (low latency) Line, Star, Ring (MRP/MRPD) Line, Star, Ring (DLR) advantage In short, high speed and low latency / hardware processing. Various classes and diagnostic functions, high interoperability Widely used in standard Ethernet infrastructure, easy to understand. From here, we will explain the technical characteristics of each. 1. EtherCAT (Ultra-high speed, low latency-oriented) ■ EtherCAT Overview Developed by Beckhoff Automation, managed by ETG. It operates at Layer 2 and has no IP/TCP/UDP overhead. Cycle time: ~ 31.25 μs ( implementation dependent ) Synchronization accuracy: ±1μs or less ZHOU_XIAO_0-1779258860716.png ■ Network Configuration Main device (master) and  Multiple sub-devices (slaves) The sub-device is equipped with an ESC ( EtherCAT Slave Controller ) and uses dedicated hardware for high-speed processing. While a line configuration is the basic setup, it also supports redundant configurations using a ring structure. ZHOU_XIAO_0-1780967472867.png Figure: EtherCAT network configuration image The most distinctive feature of EtherCAT is "on-the-fly processing. " A single frame is processed as it passes through all devices, with each device reading and writing data during transit. Because processing is handled by dedicated hardware (ESC) without involving the CPU, it achieves extremely low latency.   ZHOU_XIAO_3-1780967819685.png Figure: EtherCAT network transfer image ■ Related protocol conversion: EtherCAT (IEC 61784-2-12) • CoE (CAN over EtherCAT): Enables CANopen communication to be used by tunneling it over an EtherCAT frame. • FoE (File over EtherCAT): A protocol for transferring files via EtherCAT. EoE (Ethernet over EtherCAT): A mechanism for encapsulating and transmitting regular Ethernet frames (such as TCP/IP ). ZHOU_XIAO_4-1779258860793.png Figure: EoE protocol conversion by master device (MDevice) 2. PROFINET (Flexibility/Interoperability) ■ PROFINET Overview Developed by Siemens, managed by PNO. Standard Ethernet based Use RT/IRT/NRT depending on the application. Producer/Consumer Model ■ Network Configuration Flexible support for various topologies such as line, star, and mixed configurations. It also supports ring redundancy via MRP ( Media Redundancy Protocol ) / MRPD (IRT) . PROFINET 's communication performance is classified by " Conformance Class ( CC )". CC-A : Basic real-time, all IT services (e.g., TCP/IP ) can be used without restrictions. CC-B : Adds network diagnostics and other features to the general FA 's RT . CC-C ( IRT 😞 Motion applications in the 31.25 μs class ■ Communication type NRT: Record Read/Write: Sends and receives parameters and settings aperiodicly. Alarms: Notifies of abnormalities from the device. RT: Periodic I/O communication, generally 1ms IRT (Isochronous): Time-synchronized high-speed periodic communication , typically 31.25us. → Achieves high flexibility, detailed diagnostics, and high interoperability. ZHOU_XIAO_5-1779258860863.png 3. EtherNet/IP ( IT compatibility/standardization) ■ EtherNet/IP Overview EtherNet/IP is managed by ODVA (Open DeviceNet Vendors Association). It adopts CIP (Common Industrial Protocol), which operates at a layer above TCP/UDP/IP (L3/L4). Object-Oriented Model ZHOU_XIAO_6-1779258860900.png ■ Network Configuration Supports line, star, and ring topologies. Supports high-speed redundancy using DLR ( Device Level Ring ). Main device → Scanner : Functions as a controller and typically initiates requests. Subdevice → Adapter : The device that responds to that request. ■ EtherNet/IP's key feature: "Object-Oriented Model" Each device is defined as a collection of objects consisting of " Class ," " Instance ," " Attribute ," and " Service ." Class : Type of function (e.g., Identity , Assembly ) Instance : A specific instance of that class. Attribute : The specific value that each instance possesses. Service : Operation details such as reading and writing. This results in a very clear structure for the device's functions, enabling high compatibility across manufacturers. ZHOU_XIAO_7-1779258860986.png ■ Communication type Explicit Messaging Connection Uses TCP , reads and writes configuration values, performs self-diagnosis, and logs. Give instructions such as "Read" and "Write" once each. Implicit Messaging- I/O Connection Using UDP , it enables real-time communication such as cycle I/O , with the scanner sending and receiving I/O data at regular intervals.   The key feature of EtherNet/IP is its ability to enable high-speed I/O communication using implicit ( UDP ) protocols. summary Industrial Ethernet is not just a communication tool; it's a system technology that enables real-time control . The three protocols introduced here each achieve this through a different approach. protocol design philosophy Main uses EtherCAT High speed, low latency Motion control PROFINET Flexibility and Integration General-purpose factory automation (FA) EtherNet/IP IT integration PLC Network   As a future trend, industrial networks will move in the following direction. TSN ( Time Sensitive Networking ) Security (including CRA compliance) Integration with OPC UA In other words, the key lies in the fusion of "real-time × IT integration × security" . Next time, Why is the i.MX RT1180 suitable for industrial Ethernet protocols? Actual implementation and evaluation procedures We will explain this in detail. ============================= We are currently unable to respond to comments left in the " Comment " section of this post . We apologize for the inconvenience, but please refer to " Technical Questions to NXP - How to Contact Us( Japanese Blog) " when making inquiries.(If you are already an NXP distributor or have a relationship with NXP, you may ask your representative directly.) Communication in industrial equipment is rapidly shifting from traditional fieldbuses to Ethernet-based systems. At the heart of this shift is the Industrial Ethernet protocol . This article focuses on three widely used protocols and clearly explains the differences in their technical structure and design philosophy . EtherCAT PROFINET EtherNet/IP (※Evaluation and implementation methods will be explained in a separate article.)   This article will cover the three major protocols that dominate industrial Ethernet: EtherCAT, PROFINET, and EtherNet/IP, and provide a clear explanation of the differences in their technical structures and design philosophies.   (Reading time: 15 minutes) i.MX RT Processors Introduction Japanese Blog
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VLM Edge Studio VLM Edge Studio In this post, I want to share a quick walkthrough of VLM Edge Studio, an NXP launcher application designed to interact with supported Vision-Language Models running locally on FRDM i.MX platforms with Ara240 DNPU acceleration. VLM Edge Studio provides a Qt/QML-based GUI for model selection, prompt input, and visual interaction with locally running VLMs at the edge. It communicates with the Ara240 Runtime SDK through the eIQ AAF Connector using a REST-based interface and streaming token responses.   Key Features Local Vision-Language Model inference on supported i.MX platforms Ara240 DNPU acceleration GUI-based model selection and prompt input Streaming token output Integration with eIQ AAF Connector and Ara240 Runtime SDK Support for camera-based visual input using a USB-C HD camera   Supported Model Qwen2.5-VL-7B-Instruct-Ara240 This model is provided as an Ara240-compatible model.dvm file and is intended for local execution on the target platform.   Basic Installation After making sure the Ara240 Runtime SDK is installed on the target board, copy the Debian package: scp vlm-edge-studio.deb root@ : Install it with: dpkg -i vlm-edge-studio.deb The installation may take a few minutes because the model needs to be extracted during setup.   Running VLM Edge Studio Start the application with: run_vlm_edge_studio Before launching, make sure the Ara240 runtime service is running: systemctl status rt-sdk-ara2.service --no-pager -l Once the GUI appears, click LOAD to load the model. After the model is ready, enter a prompt and submit it to interact with the VLM locally on the i.MX platform.   Walkthrough Video In the attached video, I show how to launch VLM Edge Studio, load the supported Vision-Language Model, submit a prompt, and interact with the model running locally with Ara240 DNPU acceleration. (function() { var wrapper = document.getElementById('lia-vid-6396694743112w960h540r549'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos) Summary VLM Edge Studio is a useful tool for evaluating local Vision-Language Model inference on NXP i.MX platforms using Ara240 DNPU acceleration. It provides a simple workflow for loading the model, entering prompts, and interacting with visual-language AI directly at the edge.   Link VLM Edge Studio repository ARA2-M2-16G-GT ARA240 Hands-On Training
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EIQ Connector eIQ AAF Connector In this post, I want to share a quick walkthrough of eIQ AAF Connector, a REST-based server that enables LLM and VLM inference on NXP i.MX platforms using the Ara240 DNPU. The connector provides a simple HTTP interface for client applications to send prompts and receive streaming token responses from models running locally on Ara240. It is also the communication layer used by applications such as LLM Edge Studio and VLM Edge Studio.   Key Features REST API server for Ara240-accelerated model inference Chat Completions-style HTTP endpoint Streaming token responses Support for text LLMs and Qwen2.5-VL models Model configuration through server_config.json Optional tool calling and guided generation support for compatible text models Optional semantic prompt caching for text models OpenAPI documentation available through the /docs endpoint   How It Works The eIQ AAF Connector runs on the i.MX host and exposes a REST API. Client applications send prompts to the connector, which communicates with the Ara240 Runtime SDK and the loaded model.dvm running on the Ara240 DNPU. The response is returned as generated tokens, with support for streaming output.   Basic Setup After installing the Debian package, activate the connector virtual environment: source /usr/share/eiq/aaf-connector/venv/bin/activate Run the connector: connector By default, the server starts on: 127.0.0.1:8000 To allow access from another device, start it with: connector --host 0.0.0.0   Configuration The connector uses a JSON configuration file named server_config.json to define server settings and available models. This includes model paths, tokenizer paths, model type, prompt size, tool calling support, and whether the model should be loaded at startup. { "log_level": "INFO", "model_config_path": "/usr/share/llm/{}/", "model_tokenizer_path": "/usr/share/llm/{}/tokenizer", "available_models": [ { "name": "qwen2_5-7b", "description": "Qwen2.5 7B instance", "type": "text", "tool_calling": "native", "max_prompt_size": 2047, "enabled": true } ] }   Sending a Test Request Once the server is running, a basic request can be sent to the chat completions endpoint: curl -H 'Content-Type: application/json' \ -d '{ "model": "Qwen2.5-7B-Instruct", "messages": [ { "role": "user", "content": "Who are you?" } ] }' \ -X POST 0.0.0.0:8000/v1/chat/completions The API can also be tested from the OpenAPI UI at: http://0.0.0.0:8000/docs   Walkthrough Video In the attached video, I show how to start the eIQ AAF Connector, verify the server is running, configure a model, and send a sample request to the /v1/chat/completions endpoint. (function() { var wrapper = document.getElementById('lia-vid-6396694348112w960h540r959'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos)   Summary The eIQ AAF Connector provides the REST API layer for running edge AI models on NXP i.MX platforms with Ara240 DNPU acceleration. It allows applications to send prompts, receive generated responses, and integrate local LLM or VLM inference into demos, prototypes, and edge AI workflows.   Link eIQ AAF Connector repository   ARA2-M2-16G-GT ARA240 Hands-On Training
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LLM Edge Studio LLM Edge Studio In this post, I want to share a quick walkthrough of LLM Edge Studio, an NXP launcher application designed to test supported Large Language Models running locally on i.MX platforms with Ara240 DNPU acceleration. LLM Edge Studio provides a simple GUI to select a model, load it, enter prompts, and interact with an LLM directly at the edge. It communicates with the Ara240 Runtime SDK through the eIQ AAF Connector, using a REST-based interface for prompt submission and streaming token responses.   Key Features Local LLM inference on supported i.MX platforms Ara240 DNPU acceleration GUI-based model selection and prompt input Streaming token output Integration with eIQ AAF Connector and Ara240 Runtime SDK Support for prebuilt Debian package installation or building from source   Supported Models Qwen2.5-coder-1.5B Qwen2.5-7B-Instruct These models are provided as Ara240-compatible model.dvm files and are intended for local execution on the target platform.   Basic Installation After making sure the Ara240 Runtime SDK is installed on the target board, copy the Debian package: scp llm-edge-studio.deb root@ : Install it with: dpkg -i llm-edge-studio.deb The installation may take a few minutes because the required models are downloaded during setup.   Running LLM Edge Studio Start the application with: run_llm_edge_studio Before launching, make sure the Ara240 runtime service is running: systemctl status rt-sdk-ara2.service --no-pager -l Once the GUI appears, click LOAD to load the selected model. After the model is ready, enter a prompt and submit it to start interacting with the LLM.   Walkthrough Video In the attached video, I show how to launch LLM Edge Studio, load a supported model, submit a prompt, and view the generated response running locally on the i.MX platform with Ara240 DNPU acceleration. (function() { var wrapper = document.getElementById('lia-vid-6396693184112w960h540r329'); var videoEl = wrapper ? wrapper.querySelector('video-js') : null; if (videoEl) { if (window.videojs) { window.videojs(videoEl).ready(function() { this.on('loadedmetadata', function() { this.el().querySelectorAll('.vjs-load-progress div[data-start]').forEach(function(bar) { bar.setAttribute('role', 'presentation'); bar.setAttribute('aria-hidden', 'true'); }); }); }); } }})(); (view in My Videos)   Summary LLM Edge Studio is a useful tool for quickly evaluating local LLM inference on NXP i.MX platforms using Ara240 DNPU acceleration. It provides a simple workflow for model loading, prompt testing, and observing token streaming directly at the edge. Link LLM Edge Studio repository: https://github.com/nxp-imx-support/llm-edge-studio ARA2-M2-16G-GT ARA240 Hands-On Training
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PN7161 同时移除标签时的 NFC 发现阻塞问题 我正在使用 PN7161 芯片识别 NFC 卡。 当我同时标记 MIFARE Classic 卡和智能手机的 NFC 时,然后同时移除它们,函数NxpNci_WaitForDiscoveryNotification 就会被阻止。 打印 " WAITING FOR 设备 DISCOVERY " 后,程序无法继续打印 " test_1 "。 我使用的是 SW6705。 /////////////////////////////////////////////////////////////// /* 开始探索 */ 如果(::NxpNci_StartDiscovery(RW_DiscoveryTechnologies, sizeof(RW_DiscoveryTechnologies)) != NFC_SUCCESS) { LOG_ERR("无法开始发现"); 返回; } 虽然(_nfcRfMode == NFC_RF_MODE_RW) { LOG_INF( " 等待设备发现 "); /* 等待,直到发现对等设备 */ 而(::NxpNci_WaitForDiscoveryNotification(&RfInterface) != NFC_SUCCESS) { 日志文件("test_1"); 如果(_nfcRfMode != NFC_RF_MODE_RW) { ::NxpNci_StopDiscovery(); 日志文件("模式已更改,退出 RW 模式"); 返回; } } 如果((RfInterface.ModeTech & MODE_MASK) == MODE_POLL) { ////////////////////////////////////////////////////////////////////////////// 以下是出现问题时显示的 NCI 信息。之后,即使将卡靠近,也无法识别。只有在关闭电源并重新打开后,才能再次识别该卡。 [00:03:24.623,321] Iso14443_4Handler: === ISO14443-4 Scenario Complete === NCI>> 2f 11 00 NCI<< 4f 11 01 00 [00:03:25.265,533] NfcManager:CARD REMOVED NCI>> 21 06 01 00 NCI<< 6f 11 01 00 NCI<< 41 06 01 00 NCI>> 21 03 07 03 00 01 01 06 01 NCI<< 61 06 02 00 00 NCI>> 21 03 07 03 00 01 01 06 01 NCI<< 41 03 01 00 [00:03:25.288,543] nfcManager:等待设备发现 NCI < < 41 03 01 a0 NCI < < 60 07 01 a1 a1 NCI < > 21 06 01 03 NCI < < 41 06 01 00 NCI < < 61 06 02 03 00 NC I < < 61 03 0f 01 80 00 0a 04 00 04 aa 4e 46 0e 0e 01 08 00 02 NC I < < 61 03 0f 02 00 04 00 04 08 c0 b9 fa 01 20 00 02 02 02 02 04 00 04 04 08 c0 fa 01 20 00 01 //////////////////////////////////////////////////////////////////////////// 是否有人遇到过这个问题,或者是否有建议的方法来处理同时删除标签的问题,以避免在发现通知功能中阻塞? Re: PN7161 NFC Discovery Blocking Issue with Simultaneous Tag Removal 你好@Jaden_jung 希望你一切顺利。 能否请您提供有关设置的更多详细信息?您使用的主机平台是什么?你使用的智能手机是iOS设备,还是安卓设备? 我使用 SW6705 Rev 1.2(使用未修改的 LPC55S6x RW 演示)、OM27160、LPCXpresso55S69 并同时移除 Pixel 3 和 MIFARE Classic,都无法重现这种行为。您能否使用 PN7160 开发套件 (OM27160) 重现这种行为? Eduardo。 Re: PN7161 NFC Discovery Blocking Issue with Simultaneous Tag Removal 照片显示了症状再现时的电流值。据怀疑,即使在取出卡之后,系统仍无法恢复到轮询状态。 capture_260324.png Re: PN7161 NFC Discovery Blocking Issue with Simultaneous Tag Removal 主机是 nrf52840,手机是安卓手机。(Samsung Galaxy s25 和 flip) 同时访问两张 MIFARE 经典卡时没有问题。 将 OM27160 板与树莓派搭配使用(使用 linux_libnfc-nci)时没有问题。 定义 REMOVE_P2P_SUPPORT 可以解决问题。 出现问题时,它是否按照下面的流程工作? 0. at 946line if (Answer[1] == 0x05) // true { pRfIntf->Interface = Answer[4]; // = 0x02 = INTF_ISODEP pRfIntf->Protocol = Answer[5]; // = 0x04 = PROT_ISODEP ...... NCI<< 61 05 19 01 02 04 01 ff 01 0c 0b 64 c6 b2 a3 00 00 00 80 81 71 01 00 00 02 01 00 1.在 WaitForDiscoveryNotification 处分支(第 962-963 行): 在未定义 REMOVE_P2P_SUPPORT 时执行分支。 NCI>> 21 06 01 03 (NxpNci_HostTransceive) NCI<< 41 06 01 00 (NxpNci_WaitForReception) 2.从 do-while 循环退出: 收到以下通知后,循环终止(第 966 行): NCI<< 61 06 02 03 00(成功退出循环) 3.多张卡片检测(找到 2 张卡片): 该设备可识别野外两个目标: 目标 1:61 03 0f 01 80 00 0a 04 00 04 aa 4e 46 0e 0e 01 08 00 02 目标 2:61 03 0f 02 04 00 0a 04 00 04 04 08 c0 b9 fa 01 20 00 02 02 02 04 04 08 c0 b9 fa 01 20 00 01 4.处理条件分支:(第 986 行) 由于接收到的响应与条件不符(Answer[0] == 0x61&& Answer[1] == 0x05),逻辑会跳转到 if (AnswerSize != 0) 块。 5.第 989 行的潜在阻塞: 在第 989 行,条件 while(Answer != 0) 似乎总是为真,导致潜在的无限循环或阻塞状态。这似乎是启用 P2P 支持时系统挂起的根本原因。
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RT685: SDK 25.12 に HASHCRYPT アクセラレーションがない こんにちは、 最近、SDK 25.12 にアップデートしたところ、TLS 復号化率が半分に低下していることに気付きました。 mbedTLS v3.x は、 fsl_hashcryptハードウェア機能を使用して高速化されなくなりました。 以下は、以前の SDK 25.09 を使用してmbedtls_ssl_readを呼び出すコールスタックです。ご覧のとおり、最終的にはHASHCRYPT_AES_EncryptEcbが使用されます。 hashcrypt_aes_one_block_aligned() at fsl_hashcrypt.c:437 hashcrypt_aes_one_block() at fsl_hashcrypt.c:581 HASHCRYPT_AES_EncryptEcb() at fsl_hashcrypt.c:1,284 mbedtls_internal_aes_encrypt() at aes_alt.c:1,959 mbedtls_aes_crypt_ecb() at aes_alt.c:1,323 aes_crypt_ecb_wrap() at cipher_wrap.c:114 mbedtls_cipher_update() at cipher.c:521 mbedtls_gcm_update() at gcm.c:358 mbedtls_gcm_crypt_and_tag() at gcm.c:456 mbedtls_gcm_auth_decrypt() at gcm.c:491 mbedtls_cipher_aead_decrypt() at cipher.c:1,407 mbedtls_cipher_auth_decrypt_ext() at cipher.c:1,613 mbedtls_ssl_decrypt_buf() at ssl_msg.c:1,242 ssl_prepare_record_content() at ssl_msg.c:3,667 ssl_get_next_record() at ssl_msg.c:4,551 mbedtls_ssl_read_record() at ssl_msg.c:3,817 mbedtls_ssl_read() at ssl_msg.c:5,237 <...more frames...> MBEDTLS_USE_PSA_CRYPTOが定義された SDK 25.12 のコールスタックを以下に示します。このバージョンでは、 mbedtls_internal_aes_encryptはすべて C コードで、ハードウェアアクセラレーションは使用されていません。 mbedtls_internal_aes_encrypt() at aes.c:894 mbedtls_aes_crypt_ecb() at aes.c:1,062 aes_crypt_ecb_wrap() at cipher_wrap.c:166 mbedtls_cipher_update() at cipher.c:611 gcm_mask() at gcm.c:546 mbedtls_gcm_update() at gcm.c:641 mbedtls_gcm_crypt_and_tag() at gcm.c:726 mbedtls_gcm_auth_decrypt() at gcm.c:753 mbedtls_psa_aead_decrypt() at psa_crypto_aead.c:270 psa_driver_wrapper_aead_decrypt() at psa_crypto_driver_wrappers.h:4,114 psa_aead_decrypt() at psa_crypto.c:5,023 mbedtls_ssl_decrypt_buf() at ssl_msg.c:1,625 ssl_prepare_record_content() at ssl_msg.c:4,093 ssl_get_next_record() at ssl_msg.c:5,068 mbedtls_ssl_read_record() at ssl_msg.c:4,323 mbedtls_ssl_read() at ssl_msg.c:5,983 <...more frames...> 以下は、 MBEDTLS_USE_PSA_CRYPTOが定義されていない SDK 25.12 のコールスタックです。このバージョンでは、 mbedtls_internal_aes_encryptはすべて C コードであり、HW アクセラレーションはなく、PSA は使用されません。 mbedtls_internal_aes_encrypt() at aes.c:899 mbedtls_aes_crypt_ecb() at aes.c:1,062 aes_crypt_ecb_wrap() at cipher_wrap.c:166 mbedtls_cipher_update() at cipher.c:611 gcm_mask() at gcm.c:546 mbedtls_gcm_update() at gcm.c:628 mbedtls_gcm_crypt_and_tag() at gcm.c:726 mbedtls_gcm_auth_decrypt() at gcm.c:753 mbedtls_cipher_aead_decrypt() at cipher.c:1,528 mbedtls_cipher_auth_decrypt_ext() at cipher.c:1,674 mbedtls_ssl_decrypt_buf() at ssl_msg.c:1,639 ssl_prepare_record_content() at ssl_msg.c:4,093 ssl_get_next_record() at ssl_msg.c:5,068 mbedtls_ssl_read_record() at ssl_msg.c:4,323 mbedtls_ssl_read() at ssl_msg.c:5,983 <...more frames...> RT685 HASHCRYPT ハードウェア アクセラレーションを mbedTLS に復元する予定はありますか?特定の PSA Crypto ドライバーが実装されていないようです。 よろしくお願いします。 Re: RT685: SDK 25.12 no HASHCRYPT acceleration こんにちは、エドウィン。 移行ガイドを確認しました。ただし、このバージョンの SDK では、PSA なしの mbedTLS 2.x または mbedTLS 3.x がどのようにハードウェア アクセラレーションされるかはわかりません。aes_alt.c が削除され、HASHCRYPT 機能は PSA ドライバでのみサポートされるようになりました。 SDK 25.12 ではアプリですべてが動作し、接続には間違いなく TLS 1.3 を使用したいと考えていますが、現状ではパフォーマンスが大幅に低下します。 これについては引き続き調査していきます。例の 1 つを変更して、パフォーマンスの低下を再現できるかどうかを確認します。 よろしくお願いいたします。 アミルカル Re: RT685: SDK 25.12 no HASHCRYPT acceleration こんにちは、エドウィン。 EVKで問題を再現しました。2つのサンプルに、200回の反復処理のループを追加して修正しました。 mbedtls_gcm_self_test RTC クロックを使用して全体の実行時間を計測しました。 evkmimxrt685_mbedtls_selftest_cm33 SDK 25.09からテストを実行しました 1087ミリ秒 このコールスタックでは: HASHCRYPT_AES_EncryptEcb() at fsl_hashcrypt.c:1,260 mbedtls_internal_aes_encrypt() at aes_alt.c:1,959 mbedtls_aes_crypt_ecb() at aes_alt.c:1,323 aes_crypt_ecb_wrap() at cipher_wrap.c:114 mbedtls_cipher_update() at cipher.c:521 mbedtls_gcm_starts() at gcm.c:294 mbedtls_gcm_crypt_and_tag() at gcm.c:452 mbedtls_gcm_self_test() at gcm.c:826 evkmimxrt685_mbedtls3x_psatest_cm33 SDK 25.12からテストを実行しました 8990ミリ秒 このコールスタックでは: mbedtls_internal_aes_encrypt() at aes.c:896 mbedtls_aes_crypt_ecb() at aes.c:1,062 aes_crypt_ecb_wrap() at cipher_wrap.c:166 mbedtls_cipher_update() at cipher.c:611 mbedtls_gcm_starts() at gcm.c:441 mbedtls_gcm_crypt_and_tag() at gcm.c:718 mbedtls_gcm_self_test() at gcm.c:1,075   evkmimxrt685_mbedtls3x_psatest_cm33 SDK 25.12以降 MBEDTLS_PSA_ACCEL_KEY_TYPE_AES 定義されたテストを実行した 8744ミリ秒 このコールスタックでは: HASHCRYPT_AES_EncryptEcb() at fsl_hashcrypt.c:1,255 hashcrypt_cipher_encrypt() at mcux_psa_hashcrypt_common_cipher.c:187 psa_driver_wrapper_cipher_encrypt() at psa_crypto_driver_wrappers.h:2,353 psa_cipher_encrypt() at psa_crypto.c:4,766 mbedtls_block_cipher_encrypt() at block_cipher.c:177 mbedtls_gcm_starts() at gcm.c:439 mbedtls_gcm_crypt_and_tag() at gcm.c:718 mbedtls_gcm_self_test() at gcm.c:1,075 例の変更点の要点は次のとおりです。 BOARD_InitHardware(); test_rtc_init(); psa_crypto_init(); uint64_t ms_start = test_rtc_get_msecs(); for (int i = 0; i < 200; ++i) { PRINTF("test iteration %d\r\n", i+1); mbedtls_gcm_self_test(0); } uint64_t ms_end = test_rtc_get_msecs(); PRINTF("test time = %ums\r\n", (unsigned)(ms_end - ms_start)); ...ここで、 test_rtc_get_msecs は、1 秒未満の精度を使用して現在の RTC 時刻を返します。 ご覧のとおり、新しい SDK で GCM/AES を暗号化すると、速度が約 8 倍低下します。 ご希望であれば、修正したサンプルを添付することもできます。 よろしくお願いいたします。 アミルカル Re: RT685: SDK 25.12 no HASHCRYPT acceleration こんにちは@hrc-amilcar 、 この質問にご辛抱いただきありがとうございます。社内チームからの返答を受け取りましたので、以下をご覧ください。 コールスタックから、従来の mbedtls_xxx 暗号 API を使用していることがわかります。実際、HW アクセラレーションではありません。mbedTLS3.xCrypto 用の新しい API が導入されました。これは PSA です。mbedtls/docs/psa-transition.md は v3.6.5 · Mbed-TLS/mbedtls · GitHub で高速化されています。レガシー暗号 API は MbedTLS4.x でさらに削除されます。 RT600 用の SDK で psa_crypto_examples を確認したところ、 PSA_CRYPTO_DRIVER_HASHCRYPT が定義されているため、暗号ドライバー ラッパーが暗号計算を HW にオフロードできるようになり、HASHCRYPT HW アクセラレーションがデフォルトで有効になっています。一方、MbedTLS3.x+ はより複雑で、PSA API 仕様に準拠しているため、一部のユースケースでは実際にパフォーマンスが低下する可能性があります。TLS の場合、この IP は bignum アクセラレーションのみをサポートし、HW IP がアルゴリズム全体を実装することを期待する PSA API との互換性があまりないため、むしろ非対称暗号化 (CASPER HW IP) がパフォーマンスのボトルネックになると予想されます。少なくとも一部の ECC 操作 (署名、検証) を高速化するために最善を尽くしましたが、ECDHE キー交換中の keygen などの他の操作では速度が低下する可能性があります。 ここで、パフォーマンス測定に PSA API を使用して、PSA_CRYPTO_DRIVER_HASHCRYPT が定義され、コール スタックがそれを使用していることを確認できるとよいでしょう。参考までに: Hashcrypt は AES-GCM アクセラレーションをネイティブに提供していないため、HW IP の実際のメリットを確認するには、AES-CBC または AES-CTR をベンチマークすることをお勧めします。 BR、 エドウィン。 Re: RT685: SDK 25.12 no HASHCRYPT acceleration こんにちは@hrc-amilcar 、 mbedTLS 2.x (PSA なし) から mbedTLS 3.x (PSA あり) に移行すると、次の理由によりパフォーマンスが低下する可能性があります。 PSAドライバインターフェースはまだ部分的にしか実装されていません。そのため、ドライバ作成に必要な成果物や、ドライバをMbed TLSに統合する方法は、高速化対象となる操作によって異なります。( https://mcuxpresso.nxp.com/mcuxsdk/latest/html/middleware/mbedtls3x/docs/psa-driver-example-and-guide.html) 現時点では、2.xから3.xへの適切な移行方法に関するガイドラインに従うことをお勧めしています: Mbed TLS 2.xからMbed TLS 3.0への移行 — MCUXpresso SDKドキュメント PSA APIへの適切な移行ガイド: PSA APIへの移行 - MCUXpresso SDKドキュメント ご不便をおかけして申し訳ございません。 BR、 エドウィン。 Re: RT685: SDK 25.12 no HASHCRYPT acceleration こんにちは@hrc-amilcar 、 SDK をアップデートした後に何か変更を加えましたか?SDK のサンプルコードでも同様の現象が見られますか?スタンドアロン IDE を使用していますか、それとも VS Code 拡張機能を使用していますか? BR、 エドウィン。 Re: RT685: SDK 25.12 no HASHCRYPT acceleration mbedTLS設定ファイルに MBEDTLS_PSA_ACCEL_KEY_TYPE_AES を 定義したのです が、HASHCRYPTまで呼び出されるようになりました。しかし、mbedtls_ssl_readの読み取り速度がさらに遅くなっています。他に定義が不足しているのか、PSAレイヤーが余分なオーバーヘッドを加えているのか、疑問に思っています。   TLS ソケット経由で WiFi から 4KB パケットをダウンロードする速度: SDK 25.09: 205KB/秒 (PSAなし、ksdkポートファイルありのmbedTLS 2.x) SDK 25.12: 138KB/秒 (MBEDTLS_PSA_ACCEL_KEY_TYPE_AES なし) SDK 25.12: 125KB/秒 (MBEDTLS_PSA_ACCEL_KEY_TYPE_AES 使用時) MBEDTLS_PSA_ACCEL_KEY_TYPE_AES を使用した新しいコールスタックは次のとおりです。 HASHCRYPT_AES_EncryptEcb() at fsl_hashcrypt.c:1,255 hashcrypt_cipher_encrypt() at mcux_psa_hashcrypt_common_cipher.c:203 psa_driver_wrapper_cipher_encrypt() at psa_crypto_driver_wrappers.h:2,353 psa_cipher_encrypt() at psa_crypto.c:4,766 mbedtls_block_cipher_encrypt() at block_cipher.c:177 gcm_mask() at gcm.c:543 mbedtls_gcm_update() at gcm.c:628 mbedtls_gcm_crypt_and_tag() at gcm.c:726 mbedtls_gcm_auth_decrypt() at gcm.c:753 mbedtls_psa_aead_decrypt() at psa_crypto_aead.c:270 psa_driver_wrapper_aead_decrypt() at psa_crypto_driver_wrappers.h:4,114 psa_aead_decrypt() at psa_crypto.c:5,023 mbedtls_ssl_decrypt_buf() at ssl_msg.c:1,625 ssl_prepare_record_content() at ssl_msg.c:4,093 ssl_get_next_record() at ssl_msg.c:5,068 mbedtls_ssl_read_record() at ssl_msg.c:4,323 mbedtls_ssl_read() at ssl_msg.c:5,983 <...more frames...> Re: RT685: SDK 25.12 no HASHCRYPT acceleration こんにちは@EdwinHz 、 MCUXpresso IDEを使用しています。 SDK を更新した後、追加の変更はありません。 SDK を更新するときは、「SDK マネジメント」→「SDK コンポーネントの更新」を再実行して、新しい更新されたファイルを取得します。 次に.cprojectを比較します同様の機能が有効になっているサンプルの1つに構成を変更します(例:evkmimxrt685_wifi_wpa_supplicant_cm33) PSA_CRYPTO_DRIVER_CASPER=1 PSA_CRYPTO_DRIVER_HASHCRYPT=1 CONFIG_WPA_SUPP_CRYPTO_MBEDTLS_PSA=1 等... メインの mbedTLS 構成ヘッダーとしてデフォルトのmcux_mbedtls_config.h を使用し、 evkmimxrt685_wifi_wpa_supplicant_cm33の例のwpa_supp_mbedtls_config.hとほぼ同じ独自のユーザー構成ファイルを使用しています。 mbedtls3x_examples を試して、どのように動作するか確認します。おそらく、いくつかの定義が欠落しているのでしょう。 コードをステップ実行しているときに、 gcm 操作を高速化するために、おそらくMBEDTLS_BLOCK_CIPHER_C を定義する必要があることに気付きました。 ヘッダーmbedtls3x/include/mbedtls/config_adjust_legacy_crypto.hがこれに関係しているようですが、何らかの理由でそのマクロが定義されません。 Re: RT685: SDK 25.12 no HASHCRYPT acceleration 他人の利益のために... mbedTLS 3.xのmbedtls_xorは、一度に4バイトのデータをループして呼び出しているようです。 mbedtls_get_unaligned_uint32 そして mbedtls_put_unaligned_uint32 どちらも単一の uint32 に対して memcpy を使用します。 mbedTLS の作者たちは、一度に 4 バイトの XOR ブロックを計算する (剰余ループを使用) ことでパフォーマンスの向上を試みていることは承知していますが、memcpy の完全な呼び出しによって、実際にはコードの速度が低下しています。 逆アセンブリを調査した結果、プロジェクトが -fno-builtin でコンパイルされており、小さな memcpy がコンパイラによってインライン化されないことが判明しました。 このオプションを削除すると、AES-GCM 操作に使用されていない HASHCRYPT ハードウェアのパフォーマンス損失の多くが回復しました。SO、私が投稿した例では、実行時間が 8600 ミリ秒から 2100 ミリ秒に短縮されました。mbedTLS 2.x + ksdk alt (1087 ミリ秒) のレベルには達していません。しかし、復元されたパフォーマンスは十分良好です。 -アミルカル
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RTD- Need support for using Wdg(watchdog )driver for saf9000 RTD driver version (R23-11 v1.0.0) We are from the Quantum rfp team, working for the SAF9000 chip. We are trying to use RTD's-Wdg (watchdog) driver and see some issues like wdg calls trying to suspend all interrupts and then resuming interrupts.This is affecting some of the features. So wanted some support to help identify root cause/proper usage of wdg and fix the issues we are facing. Could you please support. Current RTD Configuration we are trying to use are attached (wdg and platform xdm files): wdg- in enable direct service mode. using below calls:  For initialization:  Wdg_43_Instance0_Init((Wdg_ConfigType*)NULL_PTR); //since using post build variant   For toggle/feeding watchdog regularly we are using: Wdg_43_Instance0_SetMode(WDGIF_FAST_MODE); Let me know in direct service mode the calls to be used to initialize and feed watch dog are correct or not? Will any of these calls disturb any other interrupt, causing us other functionality issues? RTD Re: RTD- Need support for using Wdg(watchdog )driver for saf9000 Thanks Cuong. To start with we started using indirect servicing, but since we were using GptChannelConfiguration_0 for some other timer purpose already, we could not use the same in wdg configuration for "Wdg External Trigger Counter  " . We tried defining  GptChannelConfiguration_1 in addition and tried to use it for "Wdg External Trigger Counter  " in wdg tresos configuration, but it was not allowing it for some reasons(was getting red cross mark). That is when we switched to direct mode. As per your suggestion i will try using   function Wdg_43_Instance0_Service function. If problem persists then i will again try to use indirect servicing, and for configuration problem, i will approach you. Re: RTD- Need support for using Wdg(watchdog )driver for saf9000 Hi @renukasc  I see that you used SetMode to feeding watchdog is wrong. With direct service: use Wdg_43_Instance0_Service function With indirect service: use Wdg_43_Instance0_SetTriggerCondition function. Please check our example in Wdg module to refer how we use Wdg_43_Instance0_SetTriggerCondition  Path: \plugins\Wdg_TS_T40D34M50I0R0\examples Furthermore: Wdg_43_Instance0_Init((Wdg_ConfigType*)NULL_PTR) -> Using with Precompile, not Post-built Re: RTD- Need support for using Wdg(watchdog )driver for saf9000 i could try using Wdg_43_Instance0_Service. Watchdog functionality fine as said before.If not fed , watchdog isr is triggering as expected.But problem is when watchdog apis are used,i could see it affecting all our other functinalities.Looks like it is affecting interrupts. Could you please provide one WDT example application, that has timer and other ISR like UART in which WDT is not affecting these ISRs using direct service mode .   Re: RTD- Need support for using Wdg(watchdog )driver for saf9000 One more update, as indicated earlier when wachdog calls are used in our app, looks like other interrupts like timer(gpt) are not getting served, we dont get isrs triggering for this any more. Tried changing priority of the interrupts,not helping. Also tried commenting OsIf_SuspendAllInterrupts(), OsIf_ResumeAllInterrupts()  in /RTD/eclipse/plugins/Rte_TS_T40D94M10I0R0/src/SchM_Wdg.c . This is also not helping. Could you please provide one WDT example application, that has timer and other ISR like UART in which WDT is not affecting these ISRs using direct service mode.   Re: RTD- Need support for using Wdg(watchdog )driver for saf9000 Below is the flow when WDG service is called:  Wdg_43_Instance0_Service()   → Wdg_ChannelService(WDG_IPW_INSTANCE0)       → Wdg_Ipw_Service(Instance)           → Swt_Ip_Service(Instance)               → SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09();   // This can call OsIf_SuspendAllInterrupts()               → ...               → SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09();    // This can call OsIf_ResumeAllInterrupts() So, If you call Wdg_43_Instance0_Service and in your RTE, the definition of SchM_Enter_Wdg_WDG_EXCLUSIVE_AREA_09 and SchM_Exit_Wdg_WDG_EXCLUSIVE_AREA_09 are call OsIf_SuspendAllInterrupts/OsIf_ResumeAllInterrupts then yes it could affect to interrupt. However, after call this function, the interrupt should be back to normal.  Do you mean that even exit this function Wdg_43_Instance0_Service, interrupts still cannot be triggered? Can you share me how do you implemented OsIf_SuspendAllInterrupts(), OsIf_ResumeAllInterrupts()  in your project?   Re: RTD- Need support for using Wdg(watchdog )driver for saf9000 @renukasc  When "Development Error Detection" is enabled, Wdg APIs use Wdg_ChannelValidateGlobalCall and Wdg_ChannelEndValidateGlobalCall. These functions use SchM_Enter/Exit_Wdg_WDG_EXCLUSIVE_AREA_06 and SchM_Enter/Exit_Wdg_WDG_EXCLUSIVE_AREA_07. Please verify in your SchM implementation how SuspendAllInterrupts and ResumeAllInterrupts behave. In particular: after ResumeAllInterrupts is called, do all interrupts return to their normal state? Re: RTD- Need support for using Wdg(watchdog )driver for saf9000 what we finally observed when debugged is the normal timer interrupt will stop and will not resume if Wdg_43_Instance0_Init and Wdg_43_Instance0_Service calls are made with tresos configuration "Development Error Detection " is set. When we disabled 'Development Error Detection ' in tresos, we observe that other interrupts are fine when enabled with wdg calls.  
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i.MX RT1064:在 GPIO_AD_B1_09 上启用 FlexPWM 的问题 我正在使用 i.MX RT1064,并尝试在以下引脚上生成 PWM 信号。尽管通过 MCUXpresso SDK 配置了 IOMUX 并初始化了 FlexPWM 模块,但我在引脚上看不到任何输出。 GPIO_AD_B1_09:配置为 ALT1 (FLEXPWM4_PWM1_A) 当前设置: 我正在按照 SDK 中的示例——exkmimxrt1064_pwm 作为设置 PWM 的参考。 我使用标准的 50% 占空比进行测试。 问题 RT1064 上的这些特定引脚是否存在已知的内部冲突? 对于GPIO_AD_B1_09,是否需要特定的焊盘属性(DSE、速度)来覆盖默认的 USDHC 功能? 另外,我想在 GPIO_SD_B1_04 和 GPIO_AD_B1_05 上启用 PWM,但在 FlexPWM 下看不到这些引脚,有没有办法在这些引脚上也启用 PWM? 感谢您的帮助。 i.MX RT106x Re: i.MX RT1064: Issues enabling FlexPWM on GPIO_AD_B1_09 您好 ,对于 GPIO_AD_B1_09,请确保 IOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = IOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT_GPIO_AD_B1_09_ALT1; 已被设置(值为 0x00000001),否则输出将被 GPIO_EMC_02(默认值)取代。 确保驱动设置 IOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 设置为启用驱动强度,因为将其设置为 0 不会启用输出驱动。 GPIO_SD_B1_04 和 GPIO_AD_B1_05 没有柔性定时器功能: 在此查看 1064 引脚复用器电子表格: https://www.utasker.com/iMX/iMXRT1064/iMX_RT_1064.xls Regards Mark Re: i.MX RT1064: Issues enabling FlexPWM on GPIO_AD_B1_09 你好@shreya1、 你使用的是自定义板还是 EVK?我知道您是根据示例代码将引脚初始化为 PWM,但您修改了示例代码的哪些具体部分?此外,还可以让 ConfigTools 将 GPIO_AD_B1_09 引脚配置为 PWM,甚至整个 PWM 模块。 BR, Edwin. Re: i.MX RT1064: Issues enabling FlexPWM on GPIO_AD_B1_09 嗨 @EdwinHz, 我使用的是自定义板,从示例代码中我根据自己的密码更改了 PWM 编号、子模块和通道。我尝试了另一种方法,也使用了外设工具,让它来管理整个配置,但我没有看到任何输出。 你好@mjbcswitzerland, ,我确保完成了你提到的两项设置,但仍然看不到任何输出。我确定引脚已被路由,因为在将其配置为 GPIO 时,我看到了切换。 Re: i.MX RT1064: Issues enabling FlexPWM on GPIO_AD_B1_09 你好@shreya1、 感谢您的澄清。如果你能分享代码,我可以看一看,以便更好地理解初始化,更好地确定问题是与软件还是硬件有关。 BR, Edwin.
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FRDM-IMXRT1186 I want to use FRDM-IMXRT1186. Application 1 > Board Should work with Internal 1.5MB RAM and with External QSPI Flash. A> Ethernet 1 MII port (Named with Label ECAT0) can be configured with TCP/IP MODBUS Master ?  B> Ethernet 2 MII port (Named with Label ECAT1) can be configured with ETHERCAT Master ? Application 2 > Board Should work with Internal 1.5MB RAM and with External QSPI Flash. Arduino & MC Interface connector. A> Ethernet 1 MII port (Named with Label ECAT0) & Ethernet 2 MII port (Named with Label ECAT1) can be used for Ethercat Slave & Arduino & MC Interface connector Analog/Digital GPIO ? Re: FRDM-IMXRT1186 Hi @sarikaautomations , Thanks for your interest in NXP MIMXRT series! 1. A: It's recommend using J56A/J56B (RGMII ports for ETH0/ETH2) for TCP/IP/Modbus communication. Using J57A (ECAT0 port) is not advised. B: No. The RT1180 integrates ESC, not an ECAT master. 2. Yes, this is supported. For more detailed information, please refer to this guide: UM12450: FRDM-IMXRT1186 Board User Manual Best regards, Gavin
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MPXV5050GC6U <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> - 该部件是否可以清洗(使用无铅、可水洗的焊料)? 压力传感器 Re: MPXV5050GC6U <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 谢谢。我也是这么想的,但想核实一下。 Re: MPXV5050GC6U <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,辛迪、 任何进入传感器压力开口的清洁剂都可能对设备产生不利影响。因此,绝对建议使用卡普顿胶带密封部件上的检修孔。也可以在清洗前用盖子堵住部件。 此致, 托马斯 PS: I如果我的回答有助于解决您的问题,请标记为"正确" 或 "有帮助"。谢谢。
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TPMS お客様向けの NDA を取得できますか? <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> NXP様 私はNXPの代理店であるZLGのメンバーです。Anjia は現在バス TPMS を開発中であり、詳細な情報が必要です (FXTH871511DT1 REG #: R691261)。NDAの申請を手伝っていただけますか? Anjiaの情報は次のとおりです。 公司名(中文): 佛山市安驾科技有限公司 会社名:FoShan Angel Technology Co,.Ltd. 公司地址(中文):广东省佛山市南海区獅山镇北园中路王氏车灯西门装配车间2楼 住所:中国広東省仏山市南海区石山鎮北園中路王石ランプ西門組立工場2階 連絡先担当者:陈琼霓(Chen Qiongni) 職種: ソフトウェアエンジニア 電話:13727457848 企業メールボックス:[email protected] プロジェクト: バスTPMS ありがとう! よろしくお願いします オーウェン 圧力センサ
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i.MX8M plus、チャネル B のシングル チャネル DDR i.MX8M plus でチャネル B にのみ接続されたシングル チャネル LPDDR4 16 ビットを使用することは可能ですか? A が B にコネクテッドされ、B が A にコネクテッドされているデザインがありますが、単一チャネルの LPDDR4 に交換した場合、このデザインは機能しますか? i.MX 8M | i.MX 8M ミニ | i.MX 8M ナノ Re: i.MX8M plus, single channel ddr on channel B こんにちは@johan_carlsson 、 NXP サポートにお問い合わせいただきありがとうございます。 iMX8MP ハードウェア設計ガイド、iMX8MP データシート、および iMX8MP リファレンス・マニュアルに基づいています。 いいえ。NXP は、i.MX 8M Plus のチャネル B にのみ接続されたシングルチャネル LPDDR4 (16 ビット) 設計を文書化も検証もしていません。ドキュメントおよびリファレンス デザインで想定されている単一チャネル構成は、チャネル A にあります。 A <-> B が交差するデザイン (A が B に配線され、B が A に配線される) はサポートされていません。 よろしくお願いいたします。 チャビラ Re: i.MX8M plus, single channel ddr on channel B こんにちは、チャビラさん。これについては確かですか? TRMはこう言っています、 dav1_0-1770225981863.png SO、DqLnSel レジスタを変更すると (バイト レーン / スライスごとに) A から B に変更できるようになるのではないでしょうか。 Re: i.MX8M plus, single channel ddr on channel B こんにちは@dav1さん、 ここでいくつかの誤解に気づきました。 リファレンスマニュアルによると: 「1 バイト内で PHY dq から DRAM dq へのマッピング (スウィズル) をサポートします… dbyte ごとに… DqLnSel のバイト セット内の各レジスタには一意の値が必要です…」 つまり、PHY を使用すると、単一の 8 ビット スライス (dbyte) 内でボード レベルのビット間のスクランブルを元に戻すことができるということです。たとえば、PHY レーン 3 が同じ dbyte 内の DRAM DQ0 にルーティングする場合、その dbyte に対して Dq0LnSel = 3 を設定します。これにより、スウィズルが論理的に元に戻された後、MRR バイナリ カウンターなどが正しい値を返すようになります。 Re: i.MX8M plus, single channel ddr on channel B こんにちは@dav1 、 現時点では、この構成は検証されておらず、可能になるとは予想されていません。 テストを試みることはできますが、これは RAM PHY の目的の機能の範囲外であるため、信頼性の高い動作は期待できないことに注意してください。 よろしくお願いします、 チャビラ Re: i.MX8M plus, single channel ddr on channel B この回避策を実行することは可能でしょうか - DDRを2チャネルとして設定する - AとBにまたがってインターリーブしないように設定する - Bセクションのみを有効として定義する Re: i.MX8M plus, single channel ddr on channel B 私の回答に何か誤りがありましたら、ご指摘ください。もし、何も問題がなく、この投稿が前回と同様に再度削除されたら、これを Facebook に投稿します。 しかし、RPA ツールがなぜスワップを実行できるのかを示します。 MX8M_Plus_LPDDR4_RPA_v10.xlsx https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8MPlus-m865S-DDR-レジスタ-プログラミング-エイド-RPA/ta-p/1235352 3-1.png 1.png 2.png Re: i.MX8M plus, single channel ddr on channel B 試してみましたか?     i.MX8M plus, single channel ddr on channel B.png     Re: i.MX8M plus, single channel ddr on channel B @dav1スワップの問題が発生すると、テーブルが赤くなり、警告が表示されます。ただし、チャネル A とチャネル B が入れ替わると、この RPA ツールは緑色のまま表示され、対応するレジスタも変更されます。 したがって、可能性は 2 つしかありません。 RPA ツールが間違っています。 リファレンスマニュアルが間違っています。 2 つのうち 1 つは真実である必要があります。これは、 @Chaviraが明確に/回答する必要があることです。
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Probes Not Found Error when attempting to connect to FRDM46lz board Probes not found error M4 Pro Macbook Sequoia 15.6 while attempting to connect to FRDM46lz board in MCUXpresso. Fellow students with Macs have not encountered this issue. Have been working hard with university staff but not found a solution. Have already attempted plugging into difference ports, restarting device, changing privacy settings, creating a new project, and uninstalling and reinstalling MCUXpresso, among other things. Help would be greatly appreciated, thank you! Screenshot 2026-01-22 at 6.51.16 PM.png Screenshot 2026-01-23 at 5.37.17 PM.png Re: Probes Not Found Error when attempting to connect to FRDM46lz board Hello @ottofhalb , Thanks for your post. Please open Device Manager and check whether the serial port has been successfully enumerated. In addition, have you ever tried to update the OpenSDA? OpenSDA Serial and Debug Adapter | NXP Semiconductors You may refer to attached "Updating the OpenSDA Firmware.pdf". Hope it helps. BR Celeste
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