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S32K396 中的以太网问题 你好, 我正在使用 MCPTR2AK396 评估板,并成功测试了 Gmac_IP_internalloopback_s32K396 示例项目的以太网功能。现在,我想实现一个 PING 示例,在不使用 Free RTOS 的情况下,通过以太网与外部主机 PC 通信。你能否提供一个独立组网 (SA) 的示例项目来演示如何实现这一目标。 Re: Ethernet issue in S32K396 你好@bINDU3123 与 TCP/IP 协议栈一起,还有一个名为 lwip_baremetal_s32k396.它可以演示基本功能,例如从主机 PC 对板执行 ping 操作,这可能会有所帮助。 BR、VaneB
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Can IW612 act as Central and Peripheral Roles simultaneously in BLE? Hello, I'm trying to run BLE in both Central and Peripheral Roles, while i was able have multiple connections in Peripheral role, having Central and Peripheral role simultaneously is not possible in my case probably because of my GATT server configuration. Before i proceed i wanted to check if IW612 support both roles simultaneously and if there is any example which i can try to test this. Thanks.
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mcuexpresso Selecting the clock, pins and peripherals configuration buttons from MCUXpresso IDE with a project for MK81FN256 I get the following error which prevents me to configure and autogenerate the code.
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mcuexpresso Selecting the clock, pins and peripherals configuration buttons from MCUXpresso IDE with a project for MK81FN256 I get the following error which prevents me to configure and autogenerate the code. Re: mcuexpresso Hi @opetrone, Unfortunately, the MK81 is not supported on ConfigTools. As you can see from the following image of the ConfigTool's Data Manager, it only supports MK80 and MK82. I apologize for the inconvenience this may cause. BR, Edwin.
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緊急: EB Tresos ライセンスのエラー APチームの皆さん、こんにちは。 弊社のお客様(SWS社と東海理化社、日本の2社)は、以下のエラーを経験しました(図1)。昨夜 EB Tresos ツールを使用しましたが、お客様はまだライセンスを取得できません。 ライセンスの数量に誤りがあるのではないでしょうか?(NXPシステムの通信トラブル? 多くのアジアのお客様が同時に EB Tresos を使用しているのでしょうか? お客様は時々この問題に遭遇します... そのため、この問題のせいでプロジェクトの開発を再開できず、お客様はSOイライラしています... 彼らのプロジェクトスケジュールは非常にタイトです。 この問題を解決するアイデアはありますか? 一時的にお客様にライセンスの一部を与えることは可能でしょうか(難しいとは思いますが…)? ライセンスの数量を増やす予定はありますか? 図1 EB Tresos のエラー 敬具、 ふみ EB TRESOS ライセンス 優先度: 重要 Re: Urgent : Error of EB Tresos License こんにちは@mstricek 一部のお客様は、2025 年に有効期限が切れるアクティベーション コードを使用しており、 EB Client License Administrator の[アップグレード]ボタンを押して有効期限を延長しました。 しかし、一部のお客様には次のエラーが発生しています: よろしくお願いいたします ロビン Re: Urgent : Error of EB Tresos License こんにちは@mstricek この新しいコードを使用しても、私とお客様の両方が次のメッセージを受け取りました。 指定された数量は、許可される最大数量 (0) を超えています。 よろしくお願いいたします ロビン Re: Urgent : Error of EB Tresos License こんにちは@mstricek 、 どうもありがとうございます! お客様(SWS)はすでに開発中です。 MY26 Nissan FACE PIU (SWEET500)_S32K3 | 商談 | Salesforce メールで直接お問い合わせさせていただきます。 大丈夫ですか? 敬具、 ふみ Re: Urgent : Error of EB Tresos License 評価フェーズに合格し、実稼働環境に移行したお客様には、永続的なアクティベーション コードを割り当てる場合があります。ただし、そのようなコードは一般に公開されるべきではありません。 Re: Urgent : Error of EB Tresos License こんにちは@mstricek 、 サポートありがとうございます。 Q1. お客様にライセンスを一時的または永続的に付与することは可能ですか(難しいとは思いますが…)? Q2. ライセンスの数量を増やす予定はありますか? 私の知る限り、NXP はユーザーに 5000 のライセンスを配布しています。 ライセンスの数量が 5000 に達した場合、残りのユーザーは、他のユーザーがアクティブ化されたライセンスを返却するか、3 か月が経過するまで、EB Tresos を使用できません。 間違っていたら訂正して下さい。 よろしくお願いします、 ふみ Re: Urgent : Error of EB Tresos License はい、これはTresos Studioのダウンロードエリアで公開しているコードと同じです。 Re: Urgent : Error of EB Tresos License このコードは世界中のお客様が使用できますか? Re: Urgent : Error of EB Tresos License 新しいコードB25C-AEBB-4319-BAB1をご利用ください Re: Urgent : Error of EB Tresos License こんにちは、ジリさん 私のお客様も同じ問題を抱えています。 別のライセンスコードを送信していただけますか? よろしくお願いいたします。 ジェームズ Re: Urgent : Error of EB Tresos License こんにちは@jiri_kral 、 S32DSも含めてサポートありがとうございます! 急ぎの仕事が沢山あり、S32DSが確認できません… お客様の NXP ID がわかりません... しかし、私たち(私とDFAE)もお客様と同じ状況になりました(図1)。 ライセンスの数量超過... 図1 ライセンスのマネジメントの方法に問題があるのではないかと思います... DFAEと私は次のパターンを試しました(図2)。 結果として、誰かが自分のコンピュータでライセンスをアクティブ化すると、ライセンスの数がカウントされると思います。 ライセンス数がすでにいっぱいになっている場合、アクティベートしたライセンスが返却されるまで、他のユーザーはアクティベートできません。 さらに、他のユーザーは、NXP から新しいライセンス番号がリリースされるまで (少なくとも 3 か月ほど) 待つ必要があります... これは単なる私の推測です。 図2 敬具、 ふみ Re: Urgent : Error of EB Tresos License こんにちは、フミさん お客様のNXP IDをお持ちですか?
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KW45B41Z RTC 在断电期间未运行(备用电源由超级电容提供) 当电源由硬币电池提供备用电源时,RTC 在 KW45B41Z-EVK 中保持了其价值,但是在我的项目中,我在关机期间使用超级电容(25F/3.8V)为 RTC 供电。KW45B41Z在这里,RTC 没有保值。那么,我需要通过 SPC 启用任何电源模式还是需要进行任何特殊配置? 我还验证了超级电容两端的电压足以在关机期间为 RTC 供电。RTC 有任何电源模式配置吗? 问候 Kaif Re: KW45B41Z RTC not running during power off (Power backup given by super capacitor) 根据 EVK 原理图,当连接 JP5 引脚 2 和 3 时,VDD_DCDC 引脚为 RTC 供电。通过这种配置,RTC 可以在 EVK 上正常运行。我们观察到,在这种设置下,RTC 的电流约为 1 mA。 当我们使用超级电容器在定制板上复制这种排列时,超级电容器的放电速度非常快。 我们之所以特别选择超级电容器,是因为我们需要一种可充电的电源,能够维持 RTC 运行至少 1-2 个月,这在 RTC 应用中很常见。但是,由于纽扣电池不能充电,因此不适合使用。 Re: KW45B41Z RTC not running during power off (Power backup given by super capacitor) Hello 你从电容两端的电压中得到什么值?就好像进入非常低的电压(从电容放电开始)或数据表中接近最低值一样,它可能会导致功能异常,例如丢失 RTC 功能:最直接的后果是 RTC 可能会停止可靠运行。计时精度将受到影响,而且存储在 RTC 后备寄存器中的任何数据都可能丢失。 钮扣电池在其大部分寿命期间都能提供稳定且几乎恒定的电压,从而确保 RTC 始终获得高于其最低工作阈值的电压。 顺祝商祺! 路易斯 Re: KW45B41Z RTC not running during power off (Power backup given by super capacitor) 我使用的是 kw45b41zevk_rtc 演示(不是 AN14122 中的 rtc_func 或电源模式开关)。 我使用超级电容来实现 RTC 备用电源,而不是 Coin Cell(如 KW45B41Z EVK 中)。 在开机期间,RTC 将由 VDD_SWITCH 供电,但在关机期间,超级电容将为 RTC 供电。 在断电期间,超级电容正在放电(已测试),但RTC未保留其寄存值。 我附上了正在使用的 RTC 电源配置示意图。 为什么在 KW45B41Z EVK 中为 RTC 提供备用纽扣电池,为什么没有像超级电容或电池这样的可充电电源? Re: KW45B41Z RTC not running during power off (Power backup given by super capacitor) 你好,凯夫 如 KW45B41Z-EVK 所示,钮扣电池或锂电池将是首选方法,这样可以实现较长的电池寿命和电压稳定性。 关于 RTC 不能保留数值的问题,能否请您描述一下您在配置和测试时使用的程序?您使用的是"rtc_func" 演示,还是 AN14122 中的 power_mode_switch 演示? 另外,请考虑 AN14122 中提及的建议,从低电源模式启动 RTC。 顺祝商祺! 路易斯 Re: KW45B41Z RTC not running during power off (Power backup given by super capacitor) 我在定制板中使用 KW45B41Z,备用电源使用超级电容。 我们可以在断电期间使用超级电容为 RTC 供电吗?还是锂电池是唯一的出路? 如果您能在这方面给予支持,我将不胜感激。 致敬 凯夫 Re: KW45B41Z RTC not running during power off (Power backup given by super capacitor) 你好 你能帮我们确认一下你在 KW45B41Z 还是 KW45-EVK 上使用定制板吗? 应用笔记 14122 描述了如何使用 KW45 将 RTC 功能内置到低功耗应用中,并解释了实现该功能所需的文件修改。 AN14122:如何在 KW45-EVK 上使用 RTC | 恩智浦半导体 顺祝商祺! 路易斯 Re: KW45B41Z RTC not running during power off (Power backup given by super capacitor) 我们已经附上了连接到 VDD_SWITCH 线路的超级电容的示意图,我们需要在 rtc 或功率部分通过软件启用任何特定位吗? 致以最崇高的敬意 凯夫
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Which hypervisors are officially supported by NSP for Ls1043A Dear NXP Team, I would like to know, which Hypervisors are officially supported for Ls1043A . QNX/COQOS/Jailhouse/Xen/anyother? How about their ASIL ? Could you please let me know? Thanks and Regards, Karunakar Re: Which hypervisors are officially supported by NSP for Ls1043A 1. Please refer to  https://www.nxp.com.cn/docs/en/application-note/AN13138.pdf 2. You could contact the marketing team for the performance data. 3. Yes, you can. Re: Which hypervisors are officially supported by NSP for Ls1043A Hi yipingwang, Thank you for your answer. I have few more questions here. 1.) May I know, if NXP supports XEN on Ls1043A platform ?  2.)How about the performance with Jailhouse ?  3.)In case of Linux SDK, if we use KVM, can we go for production with KVM ? We are looking for a Hypervisor, with which we can go for production. Thanks and Regards, Karunakar  Re: Which hypervisors are officially supported by NSP for Ls1043A In Real-time Edge Software, Jailhouse is supported. In Linux LSDK, KVM is supported.
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Graphic shaking phenomenon during i.MX RT 700 operation Dear Support team,  Device : i.MX RT700 I have observed a graphic phenomenon related to the LCD. As the clock hand moves, the BACKGROUND image and the remaining images move together. You can see video clip.      This phenomenon can be seen in the basic example provided by GUI GUIDER. However, this issue does not appear on the i.MX RT 500. In my opinion, this phenomenon requires optimization.   The test environment is as follows. EVKIT : MIMXRT700-EVK SCH-89280 REV A3 700-89280 REVA1 EVKIT : ZC143AC72MIPI 700-94475 REV A SCH-94475 REV A  GUI-GUIDER  : GUI Guider-1.9.1-GA LVGL version : v9 SDK version  : MCUX SDK 25.03.00 toolchain version : MCUX IDE 24.12 | ARMGC 13.2.1  Re: Graphic shaking phenomenon during i.MX RT 700 operation It appears to be an issue related to the LCD driver or SmartWatch optimization.   After reviewing the code, I confirmed that the GPU is not the cause since LV_VGLITE (PXP) is not being used. To investigate whether the slowdown was due to the MIPI-DSI fetching the buffer, I tested by moving the buffer to SRAM, but the same issue persisted. Additionally, I configured the buffer with double buffering in partial refresh mode, but the issue remained.   However, when switching to full refresh mode, normal operation was observed. In conclusion, it seems the issue arises from the MIPI DSI driver and optimization used in the Smart Watch demo not being fully refined yet.   You can resolve the issue by modifying the following code:   File: <source/lvgl_support.c> Line 51: #define DEMO_DISPLAY_USE_PARTIAL_REFRESH 0     Set this to use LV_DISPLAY_RENDER_MODE_FULL mode for proper functionality. Re: Graphic shaking phenomenon during i.MX RT 700 operation Please refer to this post: https://community.nxp.com/t5/GUI-Guider/AClock-Widget-broken-Symptoms-in-i-MX-RT700/m-p/2133591/highlight/false#M1551
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LIN-LIN ゲートウェイを使用して、診断フレームまたはスリープ状態に移行するフレームを転送するにはどうすればよいですか? 私は S32K144 (IDEs は Arm 2.2 用の S32DS) を使用して LIN-LIN ゲートウェイを設計しました。LIN1 はスレーブとして動作し、LIN2 はマスターとして動作します。LIN1 で受信したフレームの一部は LIN2 経由でスレーブに転送されるはずですが、Go-To-Sleep フレームを受信しても LIN2 がそれをスレーブに送信できないことがわかりました。何か提案はありますか? Re: Using a LIN-LIN gateway, How to forward diagnostic frame or go-to-sleep frame? こんにちは、 LIN1 がスリープ状態への移行フレームを受信すると、ゲートウェイ ファームウェアはこのフレームを (ID とコンテンツによって) 検出する必要があります。次に、マスター スケジュールまたは API 呼び出し (LIN_DRV_GoToSleepMode() など) を使用して、LIN2 を手動でトリガーし、スリープ状態への移行フレームを送信します。 LIN2 がスケジュール テーブルを使用する場合は、フラグが設定されているときにスリープ状態に移行するフレームを送信する条件エントリを追加します。LIN1 がスリープ フレームを受信するときに、ゲートウェイ ロジックでこのフラグを設定します。 LIN スタックでは、バスがアイドル状態または特定の状態でない限り、Go-To-Sleep フレームの動的な送信が許可されない場合があります。確認する - LIN2 はビジー状態でもエラー状態でもない。 - 進行中のスケジュール中にフレームを送信しようとしていません。 BR、ペトル
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QorIQ T2080 处理器 IBIS 模型 您好, 我在设计中使用了T2080NXE8TTB 处理器。我想对这个设计进行 SI 分析。 请与我们分享T2080NXE8TTB的 IBIS 模型。 谢谢& Harika B N V L Re: QorIQ T2080 Processor IBIS Model 请与我们分享 T2080NXN8TTB 的 IBIS 模型。 T2080NXN8TTB 的 IBIS 模型。 Re: QorIQ T2080 Processor IBIS Model 我需要 T2080NXE8MQB 的 ibis 型号 Re: QorIQ T2080 Processor IBIS Model 恩智浦技术支持- 我在 2023 年 3 月 23 日申请 T2080 IBIS 型号,但没有收到。 请重新发送。 我检查了我的垃圾邮件文件夹,里面也没有。 Lou P Re: QorIQ T2080 Processor IBIS Model 我没有通过电子邮件收到任何文件 Re: QorIQ T2080 Processor IBIS Model 请检查您的电子邮件系统,我通过电子邮件向您发送了附件。 请检查您的电子邮件系统是否阻止了该附件。 Re: QorIQ T2080 Processor IBIS Model 嗨,yipingwang、 回复中没有附件。 请再次发送 Re: QorIQ T2080 Processor IBIS Model 我已将所需文件发送给您。
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RTC PCF85363ATLおよびPCF85263ATL内部保護 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> RTC PCF85363ATL/AX および PCF85263ATL には、内部バッテリ切り替え回路が存在します。また、両方の部品は UL 認定部品です。 -->ここでの私の質問は、バッテリー保護のために直列抵抗器またはダイオード、あるいはその両方を追加する必要があるかどうかです。バッテリー ピンには内部電流制限保護機能がありますか。また、内部に保護ダイオードはありますか。 よろしくお願いいたします。 サティッシュ RTC PCF85363ATL and PCF85263ATL Junction Temprature これらの部品の最大接合部温度と動作接合部温度を教えてください。 Re: RTC PCF85363ATL and PCF85263ATL Internal protection <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> ありがとう、トーマス あなたが言及した第13章で、次の一節が私を心配させます。 このマニュアルのすべての RTC には専用のスイッチ回路も充電器も組み込まれていないため、外部コンポーネントを使用してこれを実現する必要があります。これを実現するには、いくつかの回路例に示すように、いくつかの部品だけが必要です。 図表。 これは PCF85363ATL にも当てはまりますか? BR マルクス Re: RTC PCF85363ATL and PCF85263ATL Internal protection <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> こんにちは、マーティン、マーカス、 UM10301の第13章を参照してください。 https://www.nxp.com/docs/en/ユーザーガイド/UM10301.pdf よろしくお願いいたします。 トーマス Re: RTC PCF85363ATL and PCF85263ATL Internal protection <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> こんにちは、 TomasVaverkaさん 私も同じです。このトピックに関する追加のドキュメントはありますか?UL 番号はセーフティの適合性を証明する根拠としては不十分かもしれません。 BR マルクス Re: RTC PCF85363ATL and PCF85263ATL Internal protection <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> ハイ このトピックに関する公式ドキュメント/アプリケーションノートはありますか?CASE、試験機関または認定機関と協議する必要がある場合はどうなりますか? よろしくお願いします。 マーティン Re: RTC PCF85363ATL and PCF85263ATL Internal protection <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> ありがとう、トーマス。 よろしくお願いいたします。 サティッシュ Re: RTC PCF85363ATL and PCF85263ATL Internal protection <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> こんにちは、サティッシュさん。 ダイオード保護のみがあり、外部に直列抵抗を追加する必要があります。 よろしくお願いいたします。 トーマス
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S32K358 RTD SPI configuration question Hello Team, question from ART: ------------------------------------------------------------------------------------ We are using two SPI channels for intercommunication between S32K358 and a uP. For one the S32K3 is Master and used only for Transmission and the  for the other is slave used only for receiving.. Actually we have configurated a spiSquence contening a single job containing a single channel. See below: To receive  from this SPI (slave) we are using: Spi_SetupEB, - with channel and lenght of data to receive as parameters 2. Spi_AsyncTransmit, with Sequence as parameter. We are using a callback per la SpiSeqEndNotification called when the numbers of data is received. NO call if the number of data is less or data lost if more. We would like to have all the data read and receive ENDNotification when CS is releazed. Any suggestion? ------------------------------------------------------------------------------------ BR Stefano RTD
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I have a S32K344 with a S32KX4EVB-T172 I have followed all instructions from Getting Started with the S32K3X4EVB-T172 Evaluation Board for Automotive General Purpose | NXP Semiconductors  and I am now in the Build, Run phase. Compilation of the code with the Port Example for S32K344 was successful but for some reason, when going into debug, I am facing these errors: UsageFault: A coprocessor access error has occurred. The coprocessor is disabled or not present. UsageFault: An instruction executed with an invalid EPSR.T or EPSR.IT field. BusFault: A bus fault has occurred during lazy floating-point state preservation. Possible BusFault location: 0xF87AF003. BusFault: A bus fault has occurred on exception entry. MemManage: The processor attempted a load or store at a location that does not permit the operation. MemManage: The processor attempted an instruction fetch from a location that does not permit execution. HardFault: A fault has been escalated to a hard fault. HardFault: A BusFault has occurred on a vector table read during exception processing. Note: I have the FreeMaster Serial Communication Driver installed. The debugger initially would show: However, upon clicking either Resume/ Step Over, these errors would then occur. Any advice will be very much appreciated.   Re: I have a S32K344 with a S32KX4EVB-T172 Hi Daniel, I changed J31 to pins 3-2 and I can now flash my microcontroller. Thank you for that. The initial setup says to use pins 1-2 for J31. Re: I have a S32K344 with a S32KX4EVB-T172 Hi @marvincabuenas, The configuration of the Last mile regulator in PMC must match the HW configuration on board. V15_MCU can be generated by Q4 controlled by VRC_CTRL_MCU, or it can use VCORE from the SBC, check J31 on your board. Regards, Daniel    Re: I have a S32K344 with a S32KX4EVB-T172 Hi Daniel, It stops at the line if (PMC_CONFIG_LM_BASE_CONTROL_ENABLE == (ConfigPtr->ConfigRegister & PMC_CONFIG_LMBCTLEN_MASK)) inside Power_Ip_PMC.c Once I enter that line and click step into, it goes into assembly code and crashes. Re: I have a S32K344 with a S32KX4EVB-T172 Hello @marvincabuenas, I'm not able to reproduce it on my side with that example. Can you step through the code and find the exact instruction (or the lowest level function) that causes the failure? Thank you Re: I have a S32K344 with a S32KX4EVB-T172 Hi Daniel, I have this RTD version installed. I will check out the documents you sent. Re: I have a S32K344 with a S32KX4EVB-T172 Hi @marvincabuenas, The project should call either the PRECOMPILE or the POSTCOMPILE variants of the APIs. Which RTD version do you use? Any fault exception can further debugged, refer to this documents: https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-HARDFAULT-Handling-Interrupt-DS3-5-RTD300/ta-p/1806259 https://community.nxp.com/t5/S32K-Knowledge-Base/How-To-Debug-A-Fault-Exception-On-ARM-Cortex-M-V7M-MCU-S32K3XX/ta-p/1595570 https://community.nxp.com/t5/S32K-Knowledge-Base/Fault-handling-on-S32K14x/ta-p/1114447   Regards, Daniel  
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When LS1028 ENETC0 is a slave clock, enabling Qbv causes many packet losses. Hi ,community @yipingwang @khushbur  I connected the LS1028A to a TSN switch, with the ENETC0 port of the LS1028A configured as a slave clock. At the application layer, I wrote a program that uses SO_TXTIME to timestamp each transmitted packet, sending one packet every 1 ms. Using tsntool, I configured the gate control list (GCL) to fully open all gates (i.e., 0xff mode). However, I observed that some packets have abnormal timestamps. These packets are eventually dropped — although Linux does not report any packet drops, I confirmed the loss through packet capture with Wireshark. You can see that packet number 1667335 has a hardware timestamp of 1697.332212, which is earlier than both the preceding and following packets. This is clearly incorrect — the timestamps should be monotonically increasing, as only one packet is sent every millisecond. Upon further inspection, I found that this packet was never actually transmitted, and was silently dropped. As long as I don’t enable Qbv, this issue does not occur. Have you observed this phenomenon before? How can it be resolved? Is it a driver issue or a hardware problem? My kernel version is: Linux ls1028ardb 6.1.22-rt8 #1 SMP PREEMPT_RT Fri Mar 21 10:37:06 CST 2025 aarch64 GNU/Linux LS1028ARDB   Re: When LS1028 ENETC0 is a slave clock, enabling Qbv causes many packet losses. The fix patch for switch will be merged in Realtime-edge-v3.2, it will be released in early August. Customer can wait for it. Thanks Re: When LS1028 ENETC0 is a slave clock, enabling Qbv causes many packet losses. Hi @yipingwang  May I ask if the SWP port might have the same issue? Is there a similar patch available? So far, I have only tested the ENETC port, but I will also need to use the SWP port in the future. Thank you  Re: When LS1028 ENETC0 is a slave clock, enabling Qbv causes many packet losses. Customer can refer to the attached patch, it has been merged in Real-time edge v2.7. Re: When LS1028 ENETC0 is a slave clock, enabling Qbv causes many packet losses. Hi @yipingwang  I'm using ENETC0, and real-time-edge version is v2.6. Re: When LS1028 ENETC0 is a slave clock, enabling Qbv causes many packet losses. which port is customer using? enetc or switch? which version of real-time edge? I will check the patch for specified version. Re: When LS1028 ENETC0 is a slave clock, enabling Qbv causes many packet losses. I’m currently using the QBV (Time-Aware Shaper) mode on the network interface card. I’ve noticed that the issue only occurs when the device becomes a slave clock during time synchronization. Here’s the sequence of events: 1. I first start the application to send data — everything works fine at this stage. 2. Then I enable the QBV configuration — still no problem. 3. After that, I start the time synchronization service — still no issue. 4. However, as soon as the time sync process determines that this device is a slave, and it adjusts its local time to align with the master clock, that’s when the problem starts: the send function fails due to a full send buffer. 5. The app returns sendmsg() to 239.255.2.61:17226 failed (Err: Resource temporarily unavailable) 6. Then I reconfigure the qbv, everything works fine.  I want to know if there is an order dependency when acting as a slave clock and working with an application. For example, do I have to wait until time synchronization is completed before enabling QBV? If I enable QBV first and then perform time synchronization, will the clock adjustment process cause QBV to be disabled? BTW the lsdk version I used is real-time-edge-v2.6 Re: When LS1028 ENETC0 is a slave clock, enabling Qbv causes many packet losses. Which version of LSDK is customer using? How to config GCL entries? you can post the tsntool commands here. Suggest customer to use tcpdump to capture packets, instead of wireshark. If enabling Qbv, should ensure the bandwidth/priority of PTP stream, if no bandwidth reserved for PTP, the frames will sometimes be dropped.
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IMX8DXL flashing issue Hello NXP team, Our custom board using the i.MX8DXL processor, one of our customers reported a flashing issue when flashing the device using a Windows system. The error appears to be USB-related; however, we have been unable to reproduce the issue on our end. Do you have any suggestions or potential causes that could be related to the customer's laptop? Below is the logs UUU Tool\iW-PRGOT-R3.0-REL1.0-TelematicsGateway_Linux6.1.22_UUU> .\uuu.exe .\iW-PRGOT-R3.0-REL1.0-B0-iMX8DXL_Linux_6.1.22_UUU.uuu uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.4.243-0-ged48c51 Success 0 Failure 1 2:7 1/ 0 [Failure open usb device ] U-Boot 2023.04-iwg27_6.1.22_2.0.0_1.1+gb6bf789da2 (Mar 20 2024 - 05:40:28 +0000) CPU: NXP i.MX8DXL RevB A35 at 1200 MHz at 34C Model: iW-RainboW-G46M-i.MX8DXL-OSM Board: iWave iMX8DXL IWG46M OSM Boot: USB DRAM: 2 GiB Core: 169 devices, 25 uclasses, devicetree: separate MMC: FSL_SDHC: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Board Info: BSP Version : iW-PRGOT-SC-R3.0-REL1.0-Linux6.1.22 SOM Version : iW-PRGWZ-AP-01-R3.80000000 CPU Unique ID : 0x301E880E8293EE1C Carrier Board Version : iW-PRGJJ-AP-01-RX.X(Custom) BuildInfo: - SCFW 6638c032, SECO-FW 80649c52, IMX-MKIMAGE 5cfd2180, ATF 8103e82 - U-Boot 2023.04-iwg27_6.1.22_2.0.0_1.1+gb6bf789da2 - V2X-FW 75e63de2 version 1.2.1 switch to partitions #0, OK mmc0(part 0) is current device Detect USB boot. Will enter fastboot mode! Net: Could not get PHY for FEC0: addr 4 Could not get PHY for FEC0: addr 4 Get shared mii bus on ethernet@5b050000 eth1: ethernet@5b050000 Fastboot: Normal Setting bus to 3 Valid chip addresses: 17 51 6A 6B 74 77 Boot from USB for mfgtools *** Warning - Use default environment for mfgtool s , using default environment Run bootcmd_mfg: run mfgtool_args;if iminfo ${initrd_addr}; then if test ${tee} = yes; then bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; else booti ${loadaddr} ${initrd_addr} ${fdt_addr}; fi; else echo "Run fastboot ..."; fastboot auto; fi ; Hit any key to stop autoboot: 0 ## Checking Image at 83100000 ... Unknown image format! Run fastboot ... auto usb 1 Re: IMX8DXL flashing issue Hi @Tanushree  Sorry, I talked with our internal team, For now,  there is no solution about uuu can not work on win10 but can work fine on win11 and Ubuntu OS. The best way is using Ubuntu or Win11 OS run the uuu tool. B.R Re: IMX8DXL flashing issue Hi @pengyong_zhang  Is it possible to flash one i.MX8DXL device using another i.MX8DXL device? Has anyone tried this approach before? We would appreciate any suggestions or guidance you may have.  The observations with UUU are the same as what you shared in the last reply. Re: IMX8DXL flashing issue Hi @Tanushree  Please try use below uuu version try the test on windows10 OS: https://github.com/nxp-imx/mfgtools/releases/download/uuu_1.5.201/uuu.exe B.R Re: IMX8DXL flashing issue Hello @pengyong_zhang  In Device Manager, the device is listed under "Other devices" as "USB Download Gadget." Please let us know the specific driver that needs to be installed so we can proceed with testing. Re: IMX8DXL flashing issue Please try uninstall the USB driver and re install it. It is very strange, i have never meet this problem before. Re: IMX8DXL flashing issue Yes, we tried that as well, but it still fails with the error: 'Failed to open USB device'. Re: IMX8DXL flashing issue please try use the uuu -b command flash the image to your board. Re: IMX8DXL flashing issue Hello, Please see below — it has detected Connected Known USB Devices         Path     Chip    Pro     Vid     Pid     BcdVersion         ==================================================         1:1      MX8DXL  SDPS:   0x1FC9 0x0147   0x0003 Re: IMX8DXL flashing issue Hi @Tanushree  Can you find your board device when you type thre uuu -lsusb command? B.R Re: IMX8DXL flashing issue Hello @pengyong_zhang  Please find the attached failed log of windows 10. Re: IMX8DXL flashing issue hi @Tanushree  the windows 10 should not the root cause, please share the fail log on your windows10 OS. B.R Re: IMX8DXL flashing issue I reviewed the release notes for the Linux 6.1.22 kernel version and noticed that it recommends using UUU version 1.5.21. Currently, I am using the following specific UUU version as shown below:  While flashing works correctly on Windows 11 and Ubuntu 20.04 or later, it fails on Windows 10. However, I did not find any mention of supported or unsupported Windows versions in the release notes—only Ubuntu 20.04 is mentioned. Re: IMX8DXL flashing issue hi @Tanushree  Please share your UUU fail log on Windows10 OS. And what is your uuu version? please use the latest uuu version. B.R Re: IMX8DXL flashing issue We are encountering an issue where Kernel 6.1.22 is not flashing on Windows 10, whereas it flashes successfully on Windows 11. Could this be due to a lack of support for Windows 10? Additionally, we recently migrated from Kernel version 5.15.52 to 6.1.22. The UUU tool was functioning correctly with version 5.15.52 on Windows 10. Re: IMX8DXL flashing issue Hi @Tanushree  There is no specially about Windows setting of UUU. B.R Re: IMX8DXL flashing issue Hello @pengyong_zhang  Thank you for the reply. There doesn't appear to be any issue with the UUU script, as the same procedure works on some laptops. We're using our own custom build. Are there any specific Windows settings that could affect UUU tool flashing or UMS detection? Regards, Tanushree Re: IMX8DXL flashing issue Hi @Tanushree  What is your result if you run the uuu -b emmc_all <.wic>  command? Do not choose the uuu script file flash. B.R
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56F8300 编程软件 你好,需要读出 56F8323 的固件。 我能否使用《56800E 闪存编程器用户指南》?   Re: 56F8300 programming software 我添加了一些克隆 MCU 的信息。你只需要读出 568323 中的 2 个文件: 1) flash 568323_flash.cfg 程序 Flash.s-rp0x 00000:0 x03fff-p0x378 2) flash 568323_flash.cfg 启动 flash.s-rp0x 20000:0 x20fff-p0x378 据我所知,数据闪存区域 (0x01000 0x01FFF) 不是那么需要它 Re: 56F8300 programming software 你好@Fduch,我很高兴听到这个消息。 如有任何新问题,欢迎创建新帖。 Re: 56F8300 programming software 终于解决了!需要安装 CodeWarrior for 56800E 数字信号控制器 v8.3.exe+ FLSHPROGRAMMER_V1.2_WIN32.exe,并移动到如下目录: C:\Program Files\ Freescale\ FlashProgrammer v1.2\ bin > fflash 568323_flash.cfg 1623 0_p.s-rp0x 0:0 xfff-s-p0x378 56800E Flash 程序员 v1.1 程序 运行 时间:2025 年 7 月 21 日星期一 14:45:06 连接到本地 CCS 服务器配置为在 LP T1 端口使用并行命令转换器使用配置文件:568323_flash.cfg 配置文件中定义的 3 个闪存单元。 芯片 ID:0x01f4001d 核心 ID:0x02211004, 1 - 普通模式 将设备置于调试模式,请稍候... 读取内存:****************,完成 将设备重置为用户模式... 初始化:2907 毫秒,读取内存:3297 毫秒,退出调试:921 毫秒,总计:7125 毫秒 Re: 56F8300 programming software 操作系统是 Win XP。我也没有在上面安装 CodeWarrior。只需在 56800E Flash Programmer.exe& FFLASH.exe 档案中下载 56800E Flash Programmer 用户指南。是否需要安装 CodeWarrior? Re: 56F8300 programming software 您的 56F8300 编程软件是什么版本,它是哪个版本的 CodeWarrior 插件?此外,您的 Windows 操作系统是什么? 我注意到日志中有" CCCSClient::Open:Connection refused" 。 可能与中央案例研究有关,请参考。 Windows 7/10:在适用于 DSC 的 CodeWarrior 上使用 USB TAP-恩智浦社区 Re: 56F8300 programming software 下面是正确的 CMD 和我与你的 *cfg: C:\JtagV2>fflash 568323_flash.cfg 16230_x.S -rx0x0:0xfff -p0x378 56800E 闪存编程器 v1.0 程序运行于Mon Jul 21 13:48:18 2025 CCCSClient::Open:拒绝连接 C:\JtagV2> Re: 56F8300 programming software 您好,我在 Codewarrior v8.3 中找到了另一个 56F8323 配置文件,能否请您再试一次? Re: 56F8300 programming software 嗯,有些行动: C:\JtagV2>flashJtagLoader 568323_flash.cfg 16230_x.S -rX0x0:0xfff -p0x378 DSP56F801x 闪存加载器。编译于 2006 年 11 月 3 日 18:00:59。 版本 Alpha 2.0 (c) Freescale, TIC, 2006 by William Jiang 部分版权 2000-2002,Zloba Alexander I/O 端口驱动程序启动 使用地址为 0x378 的打印机端口。 芯片 ID:0x01f4001d 在编程中重置部件后,JTAG 路径现在如下所示: JTAG IR 路径长度:8 JTAG DR 路径长度:1 (BYPASS) 核心 ID:0x02211004 核心状态:0x0d - 调试 在编程中选择该部件的核心 TAP 后,JTAG 路径现在更改了!!! JTAG IR 路径长度:4 JTAG DR 路径长度:1 (BYPASS) 调试请求状态:0xd - 调试 启用 OnCE 状态:0xd - 调试 启用 OnCE 成功,目标芯片进入调试模式 修剪松弛振荡器成功!,调整值 =0x026c 芯片不安全 闪存配置文件命令被忽略:target_code_sets_hfmclkd 1 闪存配置文件命令被忽略:set_hfm_config_base 0x003FF7 闪存配置文件命令被忽略:set_hfm_programmer_base 0x2F800 闪存配置文件命令被忽略:set_hfm_prog_buffer_base 0 闪存配置文件命令被忽略:set_hfm_prog_buffer_size 512 配置文件中定义的 3 个闪存单元。 下载代码失败,验证 PRAM 基地址 C:\JtagV2> 怎么了? Re: 56F8300 programming software 又见面了我又回来了......我看到我需要 flash.cfg 文件来进行操作。但 56800E Flash Programmer.exe 中没有任何 *cfg 文件,在哪里可以找到?如果要更精确一些 - flash8323.cfg Re: 56F8300 programming software 你好@Fduch、 由于这是一个 LPC 频道,如有任何其他与 DSC 相关的问题,请帮助在数字信号控制器 - 恩智浦社区上创建一个新帖子。 预先感谢您的理解。 BRs, 西莱斯特 Re: 56F8300 programming software 以后肯定会有问题。为此需要进行一些调查 Re: 56F8300 programming software 你好@Fduch、 感谢您的支持。 是的,您可以使用《56800E 闪存编程器用户指南》从 56F8323 读取存储器。 请下载 56F8XXXFP 软件: 适用于 mc56f832x 和 mc56f812x DSC 的 EVK | 恩智浦半导体 然后打开文件 56800EFPUG,并按照 "2.2.3 查看内存 "部分的步骤操作: 打开文件 56800EFPUG,并按照 "2.2.3 查看内存 "部分的步骤操作。 希望能帮到你。 BRs, 西莱斯特 ------------------------------------------------------------------------------------------------------------------- 注:如果本帖回答了您的问题,请点击"ACCEPT AS SOLUTION" 按钮。Thank you! -------------------------------------------------------------------------------------------------------------------
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When I create a Device Tree, I get "Missing #address-cels" in the imx7s.dtsi file Hello. The imx7s.dtsi file is included to create the Device Tree. A warning message appears saying "imx7s.dtsi: Missing #address-cels in interrupt provider". imx7d.dtsi gives the warning "usbphynop2: missing or empty reg/range property".   usbphynop2: usbphynop2 {       compatible = "usb-nop-xceiv";       clocks = <&clks IMX7D_USB_PHY2_CLK>;       clock-names = "main_clk";   }; Why are these warnings appearing if this was made for the SABRE board? Thank you. Re: When I create a Device Tree, I get "Missing #address-cels" in the imx7s.dtsi file You are welcome, any question contact us freely. Wish you have a nice day Re: When I create a Device Tree, I get "Missing #address-cels" in the imx7s.dtsi file Thank you. I understand that the warning can be ignored. I'm still debugging, so I haven't checked the warning part yet. Anything without warnings is working fine. If I have any problems debugging the warning part, I'll ask again. Best regards. Re: When I create a Device Tree, I get "Missing #address-cels" in the imx7s.dtsi file For the warnings you can ignore it, are you met the error in your side?
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文件 drivers/clk/imx/clk-imx8ulp.c 缺少手册中的某些寄存器 请查看drivers/clk/imx/clk-imx8ulp.c 中的imx8ulp _ clk _cgc1_init、具体到第 219至221 行,请参见此处。 clks[IMX8ULP_CLK_AUD_CLK1] = imx_clk_hw_mux2("aud_clk1", base + 0x900, 0, 3, aud_clk1_sels, ARRAY_SIZE(aud_clk1_sels)); clks[IMX8ULP_CLK_SAI4_SEL] = imx_clk_hw_mux2("sai4_sel", base + 0x904, 0, 2, sai45_sels, ARRAY_SIZE(sai45_sels)); clks[IMX8ULP_CLK_SAI5_SEL] = imx_clk_hw_mux2("sai5_sel", base + 0x904, 8, 2, sai45_sels, ARRAY_SIZE(sai45_sels)); 现在,看看 i.MX 8ULP 处理器参考手册,IMX8ULPRM (此处) , 第 7.6.1.1 节 AD_CGC 内存映射。从表中可以看到,还有两个寄存器位于0x908和0x90C,没有包含在驱动程序中。 不包括这些寄存器的后果是,无法通过设备树将 TPM 6 和TPM7 (我想还有 MQS1 )配置为使用 PCC 4时钟。 我在 imx8ulp.dtsi 中添加了 tpm6 和 tpm7 节点,并配置它们使用时钟 <& pcc4 IMX8ULP_CLK_TPM6 > 和 <& pcc4 IMX8ULP_CLK_TPM7 >: per_bridge4: bus@29800000 { tpm6: pwm@29820000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x29820000 0x1000>; interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_TPM6>; assigned-clocks = <&pcc4 IMX8ULP_CLK_TPM6>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; #pwm-cells = <3>; status = "disabled"; }; tpm7: pwm@29830000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x29830000 0x1000>; interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_TPM7>; assigned-clocks = <&pcc4 IMX8ULP_CLK_TPM7>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; #pwm-cells = <3>; status = "disabled"; }; }; 但是,由于 TPM6_7CLK ( CGC1 寄存器 0x908)的默认值为 0x 00000000 ,因此 TPM6CLK 和 TPM7CLK 都配置为使用 AUD_PLL_CLK1,即由音频 PLL (PLL3PFD1DIV1) 生成的音频时钟,而不是我通过设备树选择的 PCC 4 时钟。 我通过调用writel来明确设置寄存器0x908,从而解决了这个问题。 static int imx8ulp_clk_cgc1_init(struct platform_device *pdev) { ... /* There is a register called TPM6_7CLK at offset 0x908 that is not set by this driver. By default, it is equal to 0x00000000, which causes TPM6 and TPM7 to use as their clock source an "Audio clock generated from the Audio PLL in AD - PLL3PFD1DIV1", rather than the main reference clock. By setting this register to 0x00000303, the main reference clock is used for both TPM6 and TPM7. See IMX8ULPRM, the "i.MX 8ULP Processor Reference Manual", section "Clock Generation and Control (CGC1)" for more information on this register. */ writel(0x00000303, base + 0x908); imx_check_clk_hws(clks, clk_data->num); return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); } 虽然这现在可以解决我的问题,但如果有办法通过设备树正确设置这个时钟配置,那就太好了,但这需要 cl k-imx8ulp.c时钟驱动器来配置该寄存器。 感谢您花时间调查此事! i.MX8ULP Linux Re: File drivers/clk/imx/clk-imx8ulp.c is missing some registers from the manual 嗨 @Manuel_Salas 我明白这个还没有添加到本周一(2025-07-21)的最新 lf-6.6.52-2.2.1 内核版本中 —— 有计划在树和/或上游发布这个或类似的补丁吗? 谢谢 Re: File drivers/clk/imx/clk-imx8ulp.c is missing some registers from the manual 你好@gfrung 希望你一切都好。 请尝试使用所附的补丁。 顺祝商祺! 萨拉斯
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使用 Zephyr 为 i.MX RT1060 加载 MCUboot RAM 我目前正在尝试在 i.MX RT1060 的 Zephyr 中使用 McuBoot 来加载 RAM,但我无法让引导加载程序启动映像。以下是我目前所做的步骤: 在"samples/sysbuild/with_mcuboot/sysbuild.conf", 添加 SB_CONFIG_MCUBOOT_MODE_RAM_LOAD=y. 在 samples/sysbuild/with_mcuboot-sysbuild/mcuboot.conf 中设置 CONFIG_SRAM_SIZE=128。 在生成的 .config 中文件,可以看到 CONFIG_SRAM_BASE_ADDRESS=0x80000000 似乎是正确的。但 MCUboot 并没有启动应用程序,而是报告了错误信息"Unable to find bootable image" 。 我使用的是 Zephyr 版本 4.1.0。 我还需要做其他改动吗? 谢谢。 Ildikó Re: Using MCUboot RAM loading with Zephyr for i.MX RT1060 仅供参考@ildikoo_pocsai和@Omar_Anguiano、 本文 提供了在 RT1060 EVK 上启用 RAM 载入的步骤和 Git 补丁,请参见 https://community.nxp.com/t5/Zephyr-Project-Knowledge-Base/MCUboot-RAM-Loading-with-Zephyr/ta-p/2139539 。 顺祝商祺! Re: Using MCUboot RAM loading with Zephyr for i.MX RT1060 您可以使用诸如安全配置工具或McubootUtuTility之类的工具将DCD添加到映像中,可以从生成的二进制文件中添加DCD。如果还没有 dcd,可以在 ConfigTools 中生成。 致以最崇高的敬意, Omar Re: Using MCUboot RAM loading with Zephyr for i.MX RT1060 你好,奥马尔、 感谢您的答复。是的,我想使用外部同步动态随机存取存储器(SDRAM)。请告诉我如何在 Zephyr 中为图像添加 DCD。我正在使用 Zephyr 的 sysbuild 编译系统来版本 mcuBoot 和我的应用程序,它使用 mcuBoot imgtool 对映像进行签名。但我找不到 imgtool 添加 DCD 的任何选项。 谢谢。 Ildikó Re: Using MCUboot RAM loading with Zephyr for i.MX RT1060 你好,希望你一切都好。 地址 0x80000000 用于外部同步动态随机存取存储器(SDRAM),你想将图像加载到那个同步动态随机存取存储器(SDRAM)吗?如果是这种情况,则需要在映像中添加 DCD,以便在启动期间初始化同步动态随机存取存储器(SDRAM),这样,当代码移至同步动态随机存取存储器(SDRAM)时,它就可以开始执行了。 致以最崇高的敬意, Omar
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SPD and DMA modules are used at the same time, a hardfault will occur Hi team, I encountered some problems when testing SPD. As long as I use DMA and SPD modules at the same time, the program will enter hardfault. The strange thing is that I didn't even include these drivers, but I still encountered such errors. Attached is the test project, which is actually the routine in S32 DS (S32 DS V3.5 + RTD 5.0.0+SPD 1.0.5), adding SPD components and DMA. thanks for you help always. BR,jim. RTD S32_CONFIG_TOOL S32DS Safety_SW Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi @cuongnguyenphu  one more finding: RTD Port example enables MPU in the startup, when you disable MPU, the bus fault is not happening. This is instruction causing the issue: as you can see it resides in MPU Region 6 where I don't see any issue with that. If I do write into the address 0x2040938 via Lauterbach it's not a problem. Anyway disabling MPU helped, so not sure what's going on now. I'm leaving for vacation today so I can't support until 1st August. Kind Regards, Radoslav Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi@ @cuongnguyenphu  Thanks for your help, is there any way we can avoid this problem or how to explain it to customers? Or is this a bug? Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi @cuongnguyenphu , when adding the SAF drivers, I'd add correctly SAF mem sections into linker file (not relying on default placement) and maybe examine size of regions if there is enough reserve. I can now confirm just the fact that original SIUL2 example + SAF does work, but + DMA doesn't. Kind Regards, Radoslav Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi @RadoslavB , I see the hardfault happend when I add eMCEM and SafetyBase to our working project, even we doesn't call any APIs from it SPD APIs. When deeper investigate, I see it raised a Bus fault error when trying to access 0x20430938. I'm wonder did I missed any steps when include eMCEM and SafetyBase module? Below is my debugging screenshot and .map file 1. Add eMCeM and SafetyBase: 2. SBC->BFAR: 3. Program counter when Hardfault: 4. Map file: Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi @Senlent  Yes I can reporduce the issue at my side. it jumped to hardfault when trying to access exclusive area. It seems that when adding SPD/DMA, there're memory protection of the address exclusive area Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi@ cuongnguyenphu Thank you very much for your help, could you please let me know if you can reproduce the problem? Re: SPD and DMA modules are used at the same time, a hardfault will occur Hi @Senlent  Let me check this issue and feedback to you soon
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