S32K HSE Can not change life cycle I have ported the S32K344_CQC_DEMO secure debug project from the S32K3_HSE_DemoExamples_1_0_0 package to the S32K314. The project runs, but I'm facing an issue where the HSE_AdvanceLifecycle service always remains in a pending state, waiting for a response from the HSE. I’ve verified that the project uses the common HSE service sending function, and all other services seem to work correctly — only HSE_AdvanceLifecycle does not receive any response from the HSE.  ADKP at 0x1b000360 is  provisioned. Could you please help me check and troubleshoot this issue? Thanks in advance. Re: S32K HSE Can not change life cycle Hi, This issue is resolved when i set variable to non cache memory. Many thanks Re: S32K HSE Can not change life cycle As I know we don't have specific EVB for S32K314 device, is it S32K344 switched to S32K324 configuration and used as S32K314 as this way are devices compatible or do you have your own prototype board? From HSE point of view both device are equal and with S32K344 it works correctly.

Taplinx オフラインキーの有効期限 taplinxライブラリを使用するためのオフラインキーがある場合（AndroidとJava） このキーには時間制限や有効期限はありますか? ライセンス オフライン認証 オフライン版 Re: Taplinx Offline Key Expiration こんにちは@IslamElmasry あなたの調子が良いといいのですが。 オフライン キーの更新は必要ありません。オフライン登録の詳細については、 「TapLinx Android SDK を使用した開発の開始」のセクション 2.1 を参照してください。 よろしくお願いいたします。 エドゥアルド。

S32G: PFE FW error reported after after 4~5 consecutive A53 ungraceful reset Hi PFE experts Customer: LGE/Mobis Platform: S32G2 Module: PFE slave driver 1.6.0 Our customer is using BSP36, PFE slave driver 1.6.0 and PFE MCAL driver 1.3.0.  Customer is implementing A53 ungraceful reset. If A53 doesn't send heart beat, M7 will force reset A53.  After 4~5 consecutive reset tests, PFE FW outputs the error log below. They using the following sequence as below: /* 1. Disable Interrupt router for GIC500 */ disable_a53_interrupt_routing(); /* 2. Remove the PFE logical interface */ pfe_logif_disable(); /* 3. Flush the slave HIF internal Rx bd */ Eth_43_PFE_ChannelBdFlushRx(PFE_PHY_IF_ID_HIF1); /* 4. Clear PFE Port coherency register */ REG_WRITE32(0x4007CA00, 0x0); /* 5. Turn off A53 cores/partition */ Bl_DisableCore(0, 1); Bl_DisableCore(1, 1); Bl_DisableCore(2, 1); Bl_DisableCore(3, 1); Bl_DisablePartition(1); /* 6. Enable Interrupt router for GIC500 */ enable_a53_interrupt_routing(); /* 7. Turn on A53 cores/partition */ Bl_StartApplication(); I set up a similar environment and could not reproduce the issue, the logs from my test are normal. could you help to analysis that under what condition the error will occur?  Appreaciate for your support. Best Regards, Leo PFE Re: S32G: PFE FW error reported after after 4~5 consecutive A53 ungraceful reset This also makes us confused. Reading the code, I think this is for the use case when 1 EMAC is connected to multiple HIF channels of the same driver. But I think this is a use case not recommended anymore. And it should definitely not be used in slave mode. I can see that this command does not give an error, but I don't know if it would create this error or not: libfci_cli logif-update -i emac2 --egress hif Re: S32G: PFE FW error reported after after 4~5 consecutive A53 ungraceful reset Hi @Sebastian_Raizer  What makes me confused is that the tx_port =PFE_PHY_IF_ID_HIF. Under what condition the tx_port is equal to PFE_PHY_IF_ID_HIF? I will ask customer to share their PFE configuration. BR, Leo Re: S32G: PFE FW error reported after after 4~5 consecutive A53 ungraceful reset Hi @Sebastian_Raizer  Thanks for your answering, I will confirm with customer how they configure the PFE. BR, Leo Re: S32G: PFE FW error reported after after 4~5 consecutive A53 ungraceful reset Additional info from my PFE colleagues. Normally with PFE Linux slave, the function fp_replica_hif_rx_scaling() is executed but the condition if(PFE_PHY_IF_ID_HIF == tx_port) is false so this code is skipped and the function returns with new_port = tx_port;. For frames targeted at PFE Linux slave driver, the value of tx_port should be 7 in this case (HIF1). But somehow here the value is 3, which I think is a special value used in multi interface mode of PFE Linux standalone driver. This value should not be used for a Linux slave. This might be the hint of a mis-configuration of the bridge or the flexible parser. Re: S32G: PFE FW error reported after after 4~5 consecutive A53 ungraceful reset Hello, this error comes from the FW in function fp_replica_hif_rx_scaling(). It's the infinite loop protection for the while loop in this function. It tries to find the next active HIF to send the packet to but cannot find one (it just got disabled by the BD flush). To investigate further, try to look if there is a specific option to enable traffic spreading. Is the Linux driver really configured with only 1 HIF. I'm not sure if this FW code is always executed or only in some specific configuration. The FW should determine that the frame is aimed at a disabled interface and drop it. Other thing is that the Linux driver must not be active during the call of Eth_43_PFE_ChannelBdFlushRx(). If the kernel is in Panic, this is the case, but depending on how they trigger the hart beat loss, it might not be the case. To ensure this, maybe it is safer to turn off the Linux partition before calling the BD flush API. Or they can make sure that the kernel is in Panic or other mode where nothing is executed. I assume they use bridge mode and it looks like traffic is flowing during the recovery process. Did you setup this as well in your environment?

LPC8N04 I2C 不工作 我有 OM40002 开发板。 我发现的问题是，在将逻辑探针连接到 SDA 和 SCL 时，我只看到两条线都是高电平。(我使用的探头最大采样率为 48MHz）。 下面是我的代码： #include "LPC8N04.h" #define I2C_CLOCK (1u << 5) int main(void) { // Init pins IOCON->PIO[0][4] = 1u; // SCL IOCON->PIO[0][5] = 1u; // SDA // Init clocks SYSCON->SYSCLKCTRL &= ~0b1110u; // SYSCLKDIV = 0 => 8MHz SYSCON->SYSCLKUEN &= ~1u; // Update system clock source SYSCON->SYSCLKUEN |= 1u; SYSCON->WDTCLKDIV = 1; SYSCON->SYSAHBCLKCTRL |= I2C_CLOCK; SYSCON->PRESETCTRL |= 0b10; I2C0->CONCLR = 0b01101100; I2C0->SCLH = 80; // 8 MHz / 80 = 100 kHz I2C0->SCLL = 80; I2C0->CONSET = 0b01000000; // I2EN I2C0->CONSET = I2C0_CONSET_STA_MASK; // START while (!(I2C0->CONSET & I2C0_CONSET_SI_MASK)) // Wait ; I2C0->DAT = 0xAE; // Send slave addr while (!(I2C0->CONSET & I2C0_CONSET_SI_MASK)) // Wait ; I2C0->CONCLR |= (1 << 3); while (!(I2C0->CONSET & I2C0_CONSET_SI_MASK)) // Wait ; while (1) { } } 调试结果表明，程序在倒数第二个 while 循环（就在 CONCLR 之后）上永远旋转着 我将板一分为二，并将6个调试引脚连接在两半之间，因为我认为与LED阵列的连接可能会导致问题。 我通过上拉电阻将 P4-1（PIO0_4/SCL）和 P4-3（PIO0_5/SDA）连接到 P4-5（VCC）。 我试过从 1k 到 100k 的上拉电阻，结果都一样。 我尝试过在连接和不连接从属设备的情况下都运行。 我尝试过的任何方法都无法在 SDA 或 SCL 上产生任何输出。 我尝试了多种编译和闪烁代码的方法，包括在 mcuexpresso 中创建一个新项目，使用默认选项，然后将 main 方法更改为上述方法。 Re: LPC8N04 I2C not working 你好@橙色茶蛙 感谢您的提问。 我建议你先运行开发工具包中包含的 I2C 演示板。确认它能正常运行，这将有助于验证您的板没有问题。然后，根据您的具体要求对演示进行修改。 如果您还有其他问题，请告诉我。 谢谢！ BR 爱丽丝

ダイレクトメモリアクセスを備えたMCANが動作しない ide=s32 Design Studio for pa SDK=SDK_S32_PA_15 ボード=mpc5775b eDMAでMCAN1を使用してデータを受信しようとしましたが、機能しません。以下にコードを記載しましたので、必要な変更を提案してください。 MPC5775B-E MPC5777C Re: MCAN with direct memory access not working お返事ありがとうございます。 私は **MCAN1** のみを選択しましたが、私の設定でわかるように、EDMA コンポーネントでは MCAN1 を設定でき、チャネル番号の選択のみが可能です。チャネル0は使用していません。画像を追加しました。コードでも確認できます。 Re: MCAN with direct memory access not working DMA chnl 0 は使用できませんが、MCAN に割り当てられたチャネルは使用できます。

Good tutorial to get started on IMX-RT1160 series. I am looking at the dual core and would like to start a project with it. Current using IAR/JLINK toosl.  Any video/help to get me started? Is there a simple dual core hello world example I can follow through? Re: Good tutorial to get started on IMX-RT1160 series. Hello @n4speed, You can follow the Getting Started with the i.MX RT1160 Evaluation Kit guide, which explains how to build and run an SDK multicore demo on the MIMXRT1160-EVK, as shown in the image below: The SDK version 25.06 includes several examples that demonstrate dual-core implementation. To install the SDK for IAR, please refer to the second step in the Getting Started guide, titled "Get Software". BR Habib

ZephyrでS32K148 EVCのイーサネットをテスト/検証する方法 nxp s32k148_evbイーサネットのテスト/検証がどのように行われるかを知りたいのですが。ボード/nxp/s32k148_evbと ドライバ/ethernet/eth_nxp_*コードがプッシュされます。 同じ設定に従いたいのですが、どのアプリケーションが正確にテストされているのかを知る必要があります。 可能であればテストログを入手したいと思います。 S32K148EVB ADTJA1101-RMII Re: How to test/validation for ethernet for s32k148 evb in zephyr Zephyr に関する質問については、Zephyr プロジェクトでディスカッションを作成してください。 https://github.com/zephyrproject-rtos/zephyr/

How to test/validation for ethernet for s32k148 evb in zephyr I would like to know how the testing/validation is carried out for nxp s32k148_evb ethernet when the boards/nxp/s32k148_evb and drivers/ethernet/eth_nxp_* code is pushed. i would like to follow the same setup and which exact applications are tested i need to know. I would like to get the testing logs if possible. S32K148EVB ADTJA1101-RMII  Re: How to test/validation for ethernet for s32k148 evb in zephyr For Zephyr questions please create a discussion in Zephyr project: https://github.com/zephyrproject-rtos/zephyr/

How to disable GIC-500 242? Hi Sir, We want to turn off GIC-500 242 on Linux kernel to avoid competing with M-core for EIRQ. Could you guide us on how to achieve this, such as through DTS or other configurations? Best regards, Jeff Huang Re: How to disable GIC-500 242? hi,Jeff-CF-Huang Thank you for your reply. If you do not check the interrupt of SIUL1_ORED_IRQn, you are not enable the interrupt in M core. Hope it can help you. BR Joey Re: How to disable GIC-500 242? Hi Joey, Thank you for your reply. Could you guide us on how to keep this IRQ on the A53 cores without routing it to the M7 cores? Best regards, Jeff Huang Re: How to disable GIC-500 242? hi,Jeff-CF-Huang Thank you for your reply. Check the interrupts information, The 242 interrupt is used to gpio. You can try to modify the file of (ATF/fdts/s32g.dtsi), it has the define for gpio in this file. Hope it can help you. BR Joey Re: How to disable GIC-500 242? Hi Joey, We are currently using BSP 40 with kernel 5.15 (RDB3), but plan to migrate to BSP 44 with kernel 6.6.   Best regards, Jeff Huang Re: How to disable GIC-500 242? hi，Jeff-CF-Huang Thank you for contacting us. Could you share more information to us? Which version of BSP are you using? And are you using the RDB2 or RDB3? BR Joey

SDK クロックピンツールで「プロセッサ NCXN236 はサポートされていません」というエラーが表示される NCXN236 MCU 用に開発したい新しいプロジェクトがあります。開発ボード用の SDK といくつかのサンプル プロジェクトをロードしました。DEVELOP タブでは、通常どおり期待どおりにコードを確認できます。新しいプロジェクトも開始し、main() の「Hello World」コードを確認すると、コンパイルされます。 ただし、[クロック]、[ピン]、または [ペリフェラル] タブをクリックし、 でいずれかのプロジェクト (新しいプロジェクト、または SDK のサンプル プロジェクト) を選択すると、しばらく「プロセッサ NCXN236 をダウンロードしています」と表示され、その後、「プロセッサ NCXN236 はサポートされていないか、プロセッサのデータが利用できません」というエラー ボックスが表示されます。 オンライン ビルダーから SDK を作成してドロップしてみましたが、同じ問題が発生しました。新しいプロジェクトの基本設定を行うためにピン/クロックにアクセスできません。 MCUXpresso IDE v25.6 [Build 136] [2025-06-27]を使用しています クロック|タイマー Re: SDK Clock-Pins tools give "Processor NCXN236 is not supported" これを試してみましたが、うまくいかず、同じ問題が発生しました。IDEs を「管理者として」実行し、ツールをクリックすると、必要なファイルがダウンロードされ、タブが期待どおりに開きました。したがって、解決策は (私のCASE) 「IDEs を管理者として実行」であり、それが機能しました。ファイルがダウンロードされると、期待どおりに作業を続行するために管理者権限は必要なくなります。 Re: SDK Clock-Pins tools give "Processor NCXN236 is not supported" こんにちは@jmullen_condose ご返信ありがとうございます。 MCXpresso IDE v25.06をダウンロードしてインストールしたところ、クロック ツールが正常に動作しました。 IDE v25.06 を再度インストールし、NXP Web サイトから MCXN236 の SDK を再度ダウンロードしてください。 https://mcuxpresso.nxp.com/select 次に、SDK を IDE にインポートして再度テストします。   BR アリス   Re: SDK Clock-Pins tools give "Processor NCXN236 is not supported" 今日、これを再度テストし、MCXA156VLL MCU 用の SDK を追加しようとしましたが、SDK 自体は追加でき、サンプル プロジェクトをロードできるにもかかわらず、同じ失敗が発生しました。さまざまなツール タブを開くために必要な更新のみが失敗します。IDE v11.1 と最新の 25.6 の両方で同じ問題が発生しているため、PC / コネクティビティの問題のように見えますが、他のすべてのコネクティビティは SDKs をロードするために機能しています。Norton AntiVirus やファイアウォールなどを無効にしました。それでも失敗します。 Re: SDK Clock-Pins tools give "Processor NCXN236 is not supported" はい、PCはオンラインです。MCUxpresso v11.1 の同時実行バージョンに戻り、RT1050 用の SDK をインポートして新しいベア C プロジェクトを作成しましたが、期待どおりに動作しました。たとえば、CLOCKs タブを開くと、IDEs は指定された新しいデータを読み込み、タブが開いて期待どおりに動作します。しかし、MCNX236 SDKをインポートすると、SDKがインポートされ、SDKリストに追加されますが、CLOCKSタブを開くと、V11.1でもエラーが発生します。 SDK をインポートすると、システムが正しく「SDK の更新」を実行します。SO、オンラインは機能しています。 現在の v25.6 MCUx で RT1050 と RT1107 を試しましたが、CLOCKS やその他のツール タブを開こうとすると、同じエラーが発生します。 Re: SDK Clock-Pins tools give "Processor NCXN236 is not supported" こんにちは@jmullen_condose あなたのPCはインターネットにコネクテッドですか?Config ツールを初めて使用するときは、関連データをダウンロードする必要があるため、インターネット接続が必要です。次回はインターネットは必要ありません。     PCがオフラインの場合はお知らせください。   よろしくお願いします。   BR アリス

NXP MPC5775 EVBをBLDCモーターコントローラとして使用することに関するお問い合わせ NXPサポートチーム様 最近、NXP MPC5775 評価ボードを購入し、BLDC モーター コントローラとして使用したいと考えています。MPC5775 EVB がこのアプリケーションと互換性があるかどうか確認していただけますか? 互換性がある場合は、このボードを使用して BLDC モータ制御を実装するのに役立つガイドライン、ドキュメント、またはサンプル プロジェクトなど、サポートしていただければ幸いです。 ご協力に感謝し、ご指導を賜りますようお願い申し上げます。 よろしくお願いします、 ブーシャン・パティル Re: Inquiry Regarding Using NXP MPC5775 EVB as a BLDC Motor Controller このデバイスには、MPC5775E 3相PMSM開発キットのみがあります。 https://www.nxp.com/design/design-center/development-boards-and-designs/MCSPTR2A5775E MPC5774E では、BLDC 6 ステップ整流制御はサポートされていません。それは計画さえありません。 ただし、BLDC は FOC 制御構造を使用して PMSM として制御できる可能性があり、つまり MPC5774E によって制御できることになります。しかし、先ほど言ったように、例はありません。

ADC averaging and sampling time Hi  I am using s32k311 series microcontroller and I am working on ADC peripheral. I want to know the use of  Conversion Timing For Precision Inputs (CTR0) register. Is it related to configuration of sampling time ? If yes  how to configure sapling time of 1 msec. Also want to know how averaging is done internally?    Please give some explanation on this.  Re: ADC averaging and sampling time Thank you for your interest in our products and for contributing to our community. Following training material describe in more detail ADC conversion time: S32K3_RTD_Training_ADC_BCTU_TRGMUX https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/S32K/46171/1/S32K3_RTD_Training_ADC_BCTU_TRGMUX.pdf I hope this information is helpful.

S32R47 的最新 RTD 版本 我们 —— 雷达系统软件团队 — 正在使用 SW32R47_RTD_R21-11_0.8.0_CD01_D2505 版本中的 RTD 驱动程序和配置，它们运行良好。我们现在正尝试切换到 S32R47 的最新 RTD 版本，即 " SW32R47 实时驱动程序 AUTOSAR R23-11 0.8.0 " 但这对我们不起作用。我们注意到的行为是，在使用新 RTD 并尝试执行 Spi_AsyncTransmit 时，缺少来自 DMA 的预期中断。 我根据新 RTD 驱动程序生成新的 rtd 配置时遵循的步骤是 1-卸载了旧的 RTD 驱动程序 2-安装了新的 RTD 驱动程序 SW32R47 实时驱动程序 AUTOSAR R23-11 0.8.0 3-从我们已经拥有的 tresos 项目中导入了工作配置并且在旧版本中运行正常 4-生成了配置并将其复制到我们的工作空间如果能支持我们获取，那 就太好了最新版本也适用于我们。预先致谢 RTD Re: Latest RTD release for S32R47 我的工作空间中的 ccache 中存在一个错误，导致了这个版本错误。在我清理它之后，可以成功版本该示例。感谢您的支持 Re: Latest RTD release for S32R47 您好@MMosbah, 能否请您确认一下我提供的示例是否对您有帮助？如果是这样，您能接受这个解决方案吗？ 谢谢。 Re: Latest RTD release for S32R47 您好@MMosbah, 请参阅所附示例，我已将其修改为使用 SPI 异步传输和 DMA。 在这个示例中，转账执行正常。 Re: Latest RTD release for S32R47 你好，马略， ，感谢您的回答。我查看了这个 RTD " SW32R47 实时驱动 AUTOSAR R23-11 0.8.0 补丁 01 " 但我还没有找到使用 SPI 和 DMA 的参考示例。您知道是否存在这种情况吗？ Re: Latest RTD release for S32R47 你好 Mohamed，你验证 过 " SW32R47 实时驱动程序 AUTOSAR R23-11 0.8.0 " 中的示例是如何完成的吗？ 我已经测试了 MCL DMA 传输示例，它运行正常。DMA 没有问题。 请将你的配置也与这个进行比较，如果没有，如果你附上它，我也可以看看你的项目。 同样在 " SW32R47 实时驱动程序 AUTOSAR R23-11 0.8.0 " 中，也有同时使用 Design Studio 和 Tressos 的示例。 ——马吕斯

How to create a Dynamic Entry for CB_SG_IR in S32G-VNP-RDB int WriteCB_SG_IR(uint32_t index) {   int cs = 0; uint32_t CBSGIR_OFFSET     = 142; uint32_t CBSGIR_CTRL_OFFSET = 147; const uint32_t SWREG_BASE    = 0;   uint32_t CB_SG_IR_ADDRESS      = SWREG_BASE + CBSGIR_OFFSET; uint32_t CB_SG_IR_ADDRESS_CTL  = SWREG_BASE + CBSGIR_CTRL_OFFSET;   if (index >= 64) {         return -1;     }       uint32_t RTAGOFFSET_0 = 0;     uint32_t RTAGOFFSET_1 = 0;     uint32_t RTAGOFFSET_2 = 0;     uint32_t RTAGOFFSET_3 = 0;     uint32_t RTAGOFFSET_4 = 0;     uint32_t RTAGOFFSET_5 = 0;     uint32_t RTAGOFFSET_6 = 0;     uint32_t RTAGOFFSET_7 = 0;     uint32_t RTAGOFFSET_8 = 0;     uint32_t RTAGOFFSET_9 = 0;     uint32_t RTAGOFFSET_10 = 0;       uint32_t REPLACE_PORTS = 0;     uint32_t TAG_PORTS = 0x7FF;     uint32_t SEQ_REC_PORTS = 0;     uint32_t IND_REC_PORTS = 0;     uint32_t IND_REC_TIMEOUT = 0;     uint32_t SEQRECOFFSET = 0;     uint32_t GENSEQNUM = 0x1;     uint32_t SEQGENRST = 0;       uint32_t VALID = 1U;     uint32_t RDWRSET = 1U;     uint32_t TARGETEDTBL = 0;       uint32_t CB_SG_IR_Entry[CB_SGIR_ADDR_RANGE] = {0};         CB_SG_IR_Entry[0] =     ((GENSEQNUM & 0x1) << 28) |     ((SEQRECOFFSET & 0x1F) << 29) |     ((IND_REC_TIMEOUT & 0xFFFF) << 34);       CB_SG_IR_Entry[1] =     ((SEQ_REC_PORTS & 0x7FF) << 0) |         ((IND_REC_PORTS & 0x7FF) << 11);       CB_SG_IR_Entry[2] =         ((TAG_PORTS & 0x7FF) << 0) |         ((REPLACE_PORTS & 0x7FF) << 11);       CB_SG_IR_Entry[3] =         ((RTAGOFFSET_0 & 0x3F) << 0)  |         ((RTAGOFFSET_1 & 0x3F) << 6) |         ((RTAGOFFSET_2 & 0x3F) << 12) |         ((RTAGOFFSET_3 & 0x3F) << 18) |         ((RTAGOFFSET_4 & 0x3F) << 24);       CB_SG_IR_Entry[4] =         ((RTAGOFFSET_5 & 0x3F) << 0) |         ((RTAGOFFSET_6 & 0x3F) << 6) |         ((RTAGOFFSET_7 & 0x3F) << 12) |         ((RTAGOFFSET_8 & 0x3F) << 18) |         ((RTAGOFFSET_9 & 0x3F) << 24) |         ((RTAGOFFSET_10 & 0x3F) << 30);       uint32_t status = 0;       status = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, cs);     uint8_t counter = 0;     while ((status & (1 << 31)) != 0){        counter++;        status = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, cs);     }       for (int i = 0; i < CB_SGIR_ADDR_RANGE; i++) {     Std_ReturnType ret = spi_write_DynamicEntry(CB_SG_IR_ADDRESS + i, CB_SG_IR_Entry[i]);     if (ret != E_OK) {     return -2;     }       uint32_t readBack = 0;     ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS + i, &readBack);     if (ret != E_OK || readBack != CB_SG_IR_Entry[i]) {     return -3;     }     }       uint32_t CTRL_VALUE = (VALID << 31) |                           (RDWRSET << 30) |                           (SEQGENRST << 9) |                           (TARGETEDTBL << 6) |                           (index & 0x3F);       Std_ReturnType ret = spi_write_DynamicEntry(CB_SG_IR_ADDRESS_CTL, CTRL_VALUE);         if (ret != E_OK) {             return -4;         }           do {             ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, &status);             if (ret != E_OK) {                 return -5;             }         } while ((status >> 31) & 1U);         return 0;  // Success } I am trying to create a Dynamic Entry for CB Sequence Generation and Recovery Table in which followed up the example from SJA1110 EVM Host tools CB_SG_IR.py. where i am facing some issue with the bit settings Add on to that, see when we are configuring this  ((GENSEQNUM & 0x1) << 28) | ((SEQRECOFFSET & 0x1F) << 29) | ((IND_REC_TIMEOUT & 0xFFFF) << 34); IND_REC_TIMEOUT value is written after 32 bit register value which is we are exceeding the 32 bits where the values will be written into the wrong register ryt?? can you double check whether it will be written within 32bit register  One more thing when i debug, i could see the CB_SG_IR_Entry[0] is written with some values what we are expecting to write but in the case of other CB_SG_IR_Entr[1],[2],[3] there is no value written  I am thinking the root cause of the issue is due to bit change ?? As you mentioned the spi_read and spi_write is as same as L2 Lookup table which i used to configure dynamically which is working fine in L2 Lookup table.  Is there any other thing we are missing out ?? Re: How to create a Dynamic Entry for CB_SG_IR in S32G-VNP-RDB Hello @Atkinson , I adapted example_vlan_lookup_table.py to work with the CB SG IR table. Please find the Python script attached. I’ve also included two .hex files for the SJA1110-EVM, which contain the switchcore configuration for my minimal IEEE 802.1CB example. Just remove the .txt extension from the filenames. Save all files to the folder where host tools were unzipped, e.g. sja1110evm_hosttools_v1.2\SJA1110EVM To load the configuration onto the board, follow the DIP switch settings as described in UM575112-AH1901 SJA1110 - EVM User Manual (v1.2), section 3.3 “Quick Start using the Python Host Tools Package”, and run: python setup_sja1110evm.py --hex1 switchcore_0_Config_CB.hex --hex2 switchcore_1_Config_CB.hex Then, run the dynamic change example: python __example_cb_sgir_table.py You should see output similar to: CB SG/IR Lookup Table SW0: +-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+ | IDX | REPLACE_PORTS | TAG_PORTS | IND_REC_PORTS | SEQ_REC_PORTS | IND_REC_TIMEOUT | SEQRECOFFSET | GENSEQNUM | +-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+ |  0  |       0       |    1056   |       0       |       0       |        0        |      0       |     1     | |  1  |       0       |     0     |       2       |       2       |        0        |      0       |     0     | |  2  |       0       |     0     |       2       |       2       |        0        |      0       |     0     | |  3  |       0       |     0     |       0       |       0       |        0        |      0       |     0     | ... |  15 |       0       |     0     |       0       |       0       |        0        |      0       |     0     | +-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+ CB SG/IR Lookup Table SW1: +-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+ | IDX | REPLACE_PORTS | TAG_PORTS | IND_REC_PORTS | SEQ_REC_PORTS | IND_REC_TIMEOUT | SEQRECOFFSET | GENSEQNUM | +-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+ |  0  |       0       |     0     |       4       |       4       |        0        |      0       |     0     | |  1  |       0       |     0     |       4       |       4       |        0        |      0       |     0     | |  2  |       0       |    1056   |       0       |       0       |        0        |      0       |     1     | |  3  |       0       |     0     |       0       |       0       |        0        |      0       |     0     | ... |  15 |       0       |     0     |       0       |       0       |        0        |      0       |     0     | +-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+ Change entry #1. [0, 2097152, 1, 0, 0, 0] Reading again... CB SG/IR Lookup Table SW0: +-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+ | IDX | REPLACE_PORTS | TAG_PORTS | IND_REC_PORTS | SEQ_REC_PORTS | IND_REC_TIMEOUT | SEQRECOFFSET | GENSEQNUM | +-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+ |  0  |       0       |    1056   |       0       |       0       |        0        |      0       |     1     | |  1  |       0       |     0     |       8       |       8       |        0        |      0       |     0     | |  2  |       0       |     0     |       2       |       2       |        0        |      0       |     0     | |  3  |       0       |     0     |       0       |       0       |        0        |      0       |     0     | ... |  15 |       0       |     0     |       0       |       0       |        0        |      0       |     0     | +-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+ CB SG/IR Lookup Table SW1: +-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+ | IDX | REPLACE_PORTS | TAG_PORTS | IND_REC_PORTS | SEQ_REC_PORTS | IND_REC_TIMEOUT | SEQRECOFFSET | GENSEQNUM | +-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+ |  0  |       0       |     0     |       4       |       4       |        0        |      0       |     0     | |  1  |       0       |     0     |       4       |       4       |        0        |      0       |     0     | |  2  |       0       |    1056   |       0       |       0       |        0        |      0       |     1     | |  3  |       0       |     0     |       0       |       0       |        0        |      0       |     0     | ... |  15 |       0       |     0     |       0       |       0       |        0        |      0       |     0     | +-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+ Best regards, Pavel Re: How to create a Dynamic Entry for CB_SG_IR in S32G-VNP-RDB Hello @Atkinson , Finally, I understand your issue clearly. It turns out the root cause is related to bit alignment across 32-bit words — something quite fundamental when working with hardware register programming.  Below is the corrected code. I hope I’ve implemented it without errors, but please let me know if anything still looks off. // Entry[0] – bits 0–31 CB_SG_IR_Entry[0] = ((GENSEQNUM & 0x1) << 28) | // Bit 28 ((SEQRECOFFSET & 0x7) << 29); // Bits 29–31 // Entry[1] – bits 32–63 CB_SG_IR_Entry[1] = ((SEQRECOFFSET >> 3) & 0x3) << 0 | // Bits 32–33 ((IND_REC_TIMEOUT & 0xFFFF) << 2) | // Bits 34–49 ((SEQ_REC_PORTS & 0x7FF) << 18) | // Bits 50–60 ((IND_REC_PORTS & 0x7FF) << 29); // Bits 61–71 // Entry[2] – bits 64–95 CB_SG_IR_Entry[2] = ((TAG_PORTS & 0x7FF) << 0) | // Bits 72–82 ((REPLACE_PORTS & 0x7FF) << 11) | // Bits 83–93 ((RTAGOFFSET_0 & 0x3) << 30); // Bits 94–95 (lower 2 bits) // Entry[3] – bits 96–127 CB_SG_IR_Entry[3] = ((RTAGOFFSET_0 >> 2) & 0xF) << 0 | // Bits 96–99 (upper 4 bits) ((RTAGOFFSET_1 & 0x3F) << 4) | // Bits 100–105 ((RTAGOFFSET_2 & 0x3F) << 10) | // Bits 106–111 ((RTAGOFFSET_3 & 0x3F) << 16) | // Bits 112–117 ((RTAGOFFSET_4 & 0x3F) << 22) | // Bits 118–123 ((RTAGOFFSET_5 & 0xF) << 28); // Bits 124–127 (lower 4 bits) // Entry[4] – bits 128–159 CB_SG_IR_Entry[4] = ((RTAGOFFSET_5 >> 4) & 0x3) << 0 | // Bits 128–129 (upper 2 bits) ((RTAGOFFSET_6 & 0x3F) << 2) | // Bits 130–135 ((RTAGOFFSET_7 & 0x3F) << 😎 | // Bits 136–141 ((RTAGOFFSET_8 & 0x3F) << 14) | // Bits 142–147 ((RTAGOFFSET_9 & 0x3F) << 20) | // Bits 148–153 ((RTAGOFFSET_10 & 0x3F) << 26); // Bits 154–159 Best regards, Pavel

Usage of AES keys inside edgelock secure enclave for Platform SCP I'm checking the usage of Platform SCP inside Plug and trust middleware. About the SCP keys in MCU/MPU side, as far as I checked the document, my understanding is we have following 3 options. - hard-coded in the source code - placed in linux file system - Secured using PUF(LPC55S)  And I wonder if we also have any example using edgelock secure enclave in MCXN/RW/i.MX9 etc. Do we have such plan? Re: Usage of AES keys inside edgelock secure enclave for Platform SCP @michaelsalfer Thank you for your comment, I understand current situation. >Is there a specific customer project requesting this? No specific customer for now, I will contact you if any customer really require it. Re: Usage of AES keys inside edgelock secure enclave for Platform SCP Hello Shinji, these options you wrote are correct. There is currently not yet a plan to explicitly implement a secure enclave interface for PlatformSCP keys, although the wish exists. In general the PlatformSCP crypto is abstracted by Plug & Trust using the host cryptography implementation which can make use of Mbed TLS or OpenSSL. So if secure enclave provides e.g. a OpenSSL provider with offloading to secure enclave via a mechanism like reference keys this could be directly used by Plug & Trust. Similar for Mbed TLS. For neither option a full analysis was made so far what exactly needs to be configured.  Still I expect mid term we can get such examples, may be for the release of MW in the coming year. Is there a specific customer project requesting this? Thank You, Michael

MKW3xAデータシートの消費電力 データシートの最初のページに記載されている消費電力は トランシーバ電流（DC-DC降圧モード、3.6 V電源） • 標準受信電流: 6.3 mA • 標準送信電流: 5.7 mA (0 dBm出力) 44ページと45ページによると、消費電力は上記よりも高いようです。 降圧コンバータを使用したSTOPモードでも、RXは8.5mA、0dBmでのTxは7.8mAです。 ページ2とページ44、45の電力消費データに違いはありますか?ありがとう。 Re: The power consumption in MKW3xA Datasheet こんにちは、 あなたの調子が良いといいのですが。 値の違いは測定範囲によるものです。 データシートの冒頭に記載されている低い値（Rx = 6.3mA、Tx = 5.7mA) は RF のみの電力消費仕様であり、2.4 GHz 無線のみの消費を指します。 KW39/38/37 SoC 全体の電力消費量 (セクション 6.2.7) は、2.4 GHz 無線や DC-DC コンバータなど、MCU プラットフォームとそのペリフェラルで可能なさまざまな構成によって決まります。表 17 は、特定の動作モードで測定された SoC 構成の一部を示しています。 よろしくお願いいたします。 アナ・ソフィア。

evkbmimxrt1170_sai_edma sai1 multi channel application  Hi experts  I'm using demo evkbmimxrt1170_sai_edma_record_playback_cm7, and I'm using this API status_t SAI_TransferReceiveLoopEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer, uint32_t loopTransferCount) I want to change SAI1 it to 4 rx like this : How could I use SAI_TransferReceiveLoopEDMA to receive 4  rx? Thanks Re: evkbmimxrt1170_sai_edma sai1 multi channel application Hi @starwarrior , Seems you didn't enable the fifo combined mode for SAI multi channels, so the result was not as expected, and we provide such demo within the RT1170EVKB SDK package, but it requires CS42448 Audio board as well. Please kindly refer to that demo for details. Hope that helps, Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: evkbmimxrt1170_sai_edma sai1 multi channel application Hi Kan Here is the project I changed "evkmimxrt1170_sai_edma_record_playback_cm7" running on  MIMXRT1170-EVK.  It can only receive rx0,.  rx1、2  will pull the signal down to about 0.5V. rx4 didn't pull it down ,but neither can it receive the right data , only receive zero Could you please help to test it ?  Thanks Re: evkbmimxrt1170_sai_edma sai1 multi channel application Hi Kan Still the example evkmimxrt1170evm_sai_edma_record_playback_cm7, which use API  SAI_TransferReceiveEDMA(DEMO_SAI, &rxHandle, &xfer)).After changing it to multichannel like this： SAI_GetClassicI2SConfig(&saiConfig, DEMO_AUDIO_BIT_WIDTH, kSAI_Stereo, (1U << DEMO_SAI_CHANNEL)|(1U << DEMO_SAI_CHANNEL1)); saiConfig.syncMode = DEMO_SAI_RX_SYNC_MODE; saiConfig.bitClock.bclkPolarity = DEMO_SAI_TX_BIT_CLOCK_POLARITY; saiConfig.masterSlave = DEMO_SAI_MASTER_SLAVE; saiConfig.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnRead; SAI_TransferRxSetConfigEDMA(DEMO_SAI, &rxHandle, &saiConfig); It will not able to enter into the rx_callback. Can you possibly try to test it? Thanks Re: evkbmimxrt1170_sai_edma sai1 multi channel application Hi @starwarrior , Please use the following API instead.  Hope that helps, Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. ------------------------------------------------------------------------------- Re: evkbmimxrt1170_sai_edma sai1 multi channel application Hi Kan  Thanks for the quick reply. I have already used this API like this SAI_GetClassicI2SConfig(&saiConfig, DEMO_AUDIO_BIT_WIDTH, kSAI_Stereo, (1U << DEMO_SAI_CHANNEL)|(1U << DEMO_SAI_CHANNEL1)); saiConfig.syncMode = DEMO_SAI_TX_SYNC_MODE; saiConfig.bitClock.bclkPolarity = DEMO_SAI_TX_BIT_CLOCK_POLARITY; saiConfig.masterSlave = DEMO_SAI_MASTER_SLAVE; saiConfig.syncMode = DEMO_SAI_RX_SYNC_MODE; saiConfig.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnRead; SAI_TransferRxSetConfigEDMA(DEMO_SAI, &rxHandle, &saiConfig); And now I need to use SAI_TransferReceiveLoopEDMA to receive both audio. It looks like this API do not support multichannel ,anything I need to change? Best Regards Nick Re: evkbmimxrt1170_sai_edma sai1 multi channel application Hi @starwarrior , We provide docs on how to configure the SAI DMA driver to support multiple SAI channels, please kindly refer to https://mcuxpresso.nxp.com/mcuxsdk/25.06.00/html/drivers/RT/RT1170/MIMXRT1176/index.html#sai-edma-driver for details. Have a great day, Kan ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "Mark Correct" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

Unable to Flash on MPC5775B in S32DSPA – [Stops ar block memory range] via Multilink JTAG Description of Issue: We are unable to flash our custom VCU board (With MPC5775B micro controller) via the Multi-Link debugger. The flashing process halts during the verification stage, blocking across the full address range 0x00800000–0x008FFFFF (see attached screenshot). Root Cause Identified: A power interruption occurred during MCU flashing via JTAG Multi-Link debugger, specifically during the erase process. This appears to have entire portions of the flash memory in a corrupted state. Analysis & Attempts so far: Approach 1: In cases where the application layer memory is partially corrupted, we have previously recovered by disabling the Preserve Memory Segment option and flashing over the uncorrupted area—thus erasing the entire application memory. In this case, we removed all preserved memory range options in S32 Design Studio for Power Architecture (S32DSPA) and attempted to reflash via Multi-Link JTAG debugger. Despite this, the flashing process still stalls—currently blocking verification across the entire range 0x00800000–0x008FFFFF. Approach 2: S32DSPA does not provide a direct option to manually clear flash memory. We tested the PE Micro PROG-HL-PPCNEXUS tool. The demo version allows memory read but disables erase functionality. Observations: Core 0: Fully corrupted (undefined state XX). Core 1: Empty state Erase operation for Core 0 is not possible with the demo version. Setup Details: MCU: MPC5775B Connection: JTAG only with multilink universal debugger Board: Custom VCU board  Request for Support: Given that Core 0 flash appears fully corrupted and is blocking the flashing process across the full range 0x00800000–0x008FFFFF even with all preserve memory ranges removed, could you please advise if there is any alternative method to completely clear/erase the corrupted Core 0 memory via JTAG (Universal multilink debugger)? Re: Unable to Flash on MPC5775B in S32DSPA – [Stops ar block memory range] via Multilink JTAG Thanks David, I was able to recover the board by following exact steps. Re: Unable to Flash on MPC5775B in S32DSPA – [Stops ar block memory range] via Multilink JTAG You may try this: https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/HOWTO-MPC5777C-Low-Mid-Flash-block-erase-via-PE-Micro/ta-p/1123596 Note that MPC5775B is compatible device with MPC5777C so it could work as it is.

FRDM-MCXA156 – mcuboot_opensource SDK Example Not Working in MCUXpresso Hi, I am currently working with the FRDM-MCXA156 board for evaluation of one of our projects and using the SDK examples in MCUXpresso IDE. I have tested basic examples such as: frdmmcxa156_blink_led frdmmcxa156_lpuart_interrupt_transfer  These examples worked as expected. However, while testing the frdmmcxa156_mcuboot_opensource example from the same SDK, I encountered the following log message on the terminal: I have followed the tutorial from the official documentation here: link Could you please suggest what might be causing this issue? Core and Memory FRDM-Training Re: FRDM-MCXA156 – mcuboot_opensource SDK Example Not Working in MCUXpresso Hi @CEPL_Dev , you can also use Secure Provisioning Tool, see step-by-step procedure described in the user guide: Generic workflows — MCUXpresso Secure Provisioning Tool 25.06 Re: FRDM-MCXA156 – mcuboot_opensource SDK Example Not Working in MCUXpresso Hello @CEPL_Dev  Thanks for your question. Please use the two projects together: "mcuboot_opensource" and "ota_mcubot_basic".   For detailed steps, please refer to readme.md. If still have issue, please show all your steps, I help you check. Thank you. BR Alice

SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi NXP Support Team, I would like to report a new issue we encountered during our ongoing testing of the SD8997 Wi-Fi module in 5GHz STA mode. Issue Description Under repeated connection failure scenarios, particularly when multiple EAPOL timeouts occur (e.g., 5 consecutive failures), the driver triggers an in-band reset. However, we have observed that the firmware sometimes fails to reload afterward via the SDIO interface, leaving the Wi-Fi interface non-functional until the system is manually rebooted. This behavior seems to occur only under reconnection stress conditions and may be related to how the SDIO interface or firmware handles recovery following a reset. Platform Details SoC: NXP i.MX6ULL (ARMv7) Kernel: Linux 5.4.24-imx6ull Wi-Fi Module: NXP SD8997 (SDIO interface) Driver Stack: moal/mlan Driver Source: https://github.com/nxp-imx/mwifiex.git -b lf-6.12.20-2.0.0 (lf-6.12.20-2.0.0) Firmware Source: https://github.com/NXP/imx-firmware.git -b lf-6.12.20-2.0.0 (lf-6.12.20-2.0.0) Firmware File: nxp/sdiouart8997_combo_v4.bin Power Table: tx_power_test.bin Driver Parameters cfg80211_wext=0xf max_vir_bss=1 cal_data_cfg=none ps_mode=2 auto_ds=2 host_mlme=1 fw_name=nxp/sdiouart8997_combo_v4.bin drv_mode=3 sta_name=wlan max_uap_bss=2 txpwrlimit_cfg=nxp/tx_power_test.bin Test Setup Topology: SD8997 (STA) ←→ Access Point Test Scenario: STA reconnection stress test Failure Point: Firmware fails to reload after in-band reset, triggered by EAPOL timeouts Relevant dmesg Logs: [87697.429777] WiFi Reset due to EAPOL timeout cnt 5 [87697.499968] ========START IN-BAND RESET=========== [87704.130302] wlan_sdio_poll_card_status failed, tries = 10000, cs = 0xc [87704.259872] wlan_dnld_fw fail ret=0xffffffff [87705.481337] woal_request_fw failed [87705.484769] Firmware Init Failed Request We would greatly appreciate your help in confirming the following: Is this a known issue with SDIO firmware reload after in-band reset? Are there any suggested workarounds or firmware/driver updates available? Would this require escalation to the SAE team for deeper investigation? Please let us know if you need additional logs, debug configurations, or if any specific testing is required from our side. We’re happy to support further troubleshooting. Thank you very much for your continued assistance. Best regards, Yaoguang Attachment: dmesg.txt – captured during failure event for reference. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi, @yangyaoguang  Thanks for your confirmation. Sure, then I will close this case for now. Please feel free to create new case to us if you meet any other issue. Have a nice day! Best regards, Christine. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi Christine, After our internal discussion, we also believe that this issue can be closed. Best regards, Yangyaoguang 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi, @yangyaoguang  Thanks for your feedback. Then would you please help to accept my answer as a solution so that we can close this current case? For the SDIO frequency, let's continue to discuss in another thread, OK? https://community.nxp.com/t5/Other-NXP-Products/URGENT-SD8997-WiFi-Module-5GHz-STA-Throughput-Frequently-Drops/td-p/2142614 Best regards, Christine. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi Christine, It seems that the issue has been resolved. Based on the latest internal testing, the automation has been running for 4 days without encountering any issues. Previously, we could reproduce the problem within 1-3 hours, but with the changes we made (SDIO frequency set to 50MHz and the latest WIFI driver update), the issue no longer occurs. Thank you for your support ! Best regards, Yangyaoguang 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi, @yangyaoguang  Can you please help get below logs and details? dmesg logs (drvdbg=0xa0037) Valid FW dumps when issue is observed. The issue scenario and steps for better understanding and issue re-creation. Best regards, Christine. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi, @yangyaoguang  Thanks for your feedback. If it still exist, would you please help to provide us dmesg logs for further tracking? Hope we can resolve it ASAP. Best regards, Christine. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi Christine, This issue is still reproducible on our side. We may need some additional time to investigate it further, and we will provide feedback once we have any new findings. Best regards, Yangyaoguang 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi, @yangyaoguang  Do you have any updates on this case? Whether the original issue(Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout) is still exist? Best regards, Christine. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi, @yangyaoguang  Thanks for your quick reply. Sounds great! Then please help to check the original issue(Wi-Fi fails to recover after in-band reset triggered by EAPOL Timeout) whether still exist. Best regards, Christine. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi Christine, We followed your instruction and copied the firmware file: cp /lib/firmware/nxp/sdiouart8997_combo_v4.bin /lib/firmware/nxp/sduart8997_combo_v4.bin After that, the Wi-Fi driver loaded successfully, and the firmware initialized as expected. Here is part of the log: [ 31.293027] wlan: Register to Bus Driver... [ 31.298597] vendor=0x02DF device=0x9141 class=0 function=1 [ 31.304248] Attach moal handle ops, card interface type: 0x104 [ 31.310149] rps set to 0 from module param [ 31.316040] SD8997: init module param from usr cfg [ 31.320942] card_type: SD8997, config block: 0 [ 31.325442] cfg80211_wext=0xf [ 31.328413] max_vir_bss=1 [ 31.332138] cal_data_cfg=none [ 31.335330] ps_mode = 2 [ 31.338024] auto_ds = 2 [ 31.340495] host_mlme=enable [ 31.343678] drv_mode = 3 [ 31.346425] sta_name=wlan [ 31.349052] max_uap_bss = 2 [ 31.352108] txpwrlimit_cfg=nxp/tx_power_test.bin [ 31.357979] Mode PSD file name: nxp/tx_power_test.bin [ 31.358168] SDIO: sdio_blk_size=256 max_blk_count=65535 max_segs=128 max_seg_size=65535 [ 31.371521] rx_work=1 cpu_num=4 [ 31.375600] Enable moal_recv_amsdu_packet [ 31.379863] Attach mlan adapter operations.card_type is 0x104. [ 31.386878] wlan: Enable TX SG mode [ 31.390609] wlan: mpa_tx.buf_size=65280 [ 31.394633] wlan: Enable RX SG mode [ 31.421308] Request firmware: nxp/sduart8997_combo_v4.bin [ 32.226230] Wlan: FW download over, firmwarelen=635964 downloaded 626844 [ 32.839565] imx-dwmac 30bf0000.ethernet eth1: Link is Up - 100Mbps/Full - flow control rx/tx [ 32.945532] WLAN FW is active [ 32.948508] on_time is 32943367625 [ 32.951962] Download txpwrlimit_cfg=nxp/tx_power_test.bin [ 33.015199] VDLL image: len=9120 [ 33.098103] fw_cap_info=0x587c6fa3, dev_cap_mask=0xffffffff [ 33.103931] max_p2p_conn = 8, max_sta_conn = 8 [ 33.111331] FW country code WW does not match with US [ 33.142173] Register NXP 802.11 Adapter wlan0 [ 33.147973] wlan: uap%d set max_mtu 2000 [ 33.160450] Register NXP 802.11 Adapter uap0 [ 33.167250] wlan: uap%d set max_mtu 2000 [ 33.189411] Register NXP 802.11 Adapter uap1 [ 33.195525] wlan: version = SD8997----16.92.21.p149.2-MM6X16537.p9-GPL-(FP92) [ 33.209366] usbcore: registered new interface driver usbxxx [ 33.217078] wlan: Register to Bus Driver Done [ 33.221474] wlan: Driver loaded successfully [ 33.691546] wlan: wlan0 START SCAN Best regards, Yaoguang 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi, @yangyaoguang  Thank you for the driver load logs. From logs we can see below: [ 31.541283] Request firmware: nxp/sduart8997_combo_v4.bin   Please copy the available combo FW as follows: cd /lib/firmware/nxp/ cp sdiouart8997_combo_v4.bin sduart8997_combo_v4.bin   Please let us know if you still observe driver load failure after above steps.   Thanks, Christine. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi， @yangyaoguang  Thanks for your quick response. Sure, Let me check internally and reply you soon. Best regards, Christine. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi Christine, Thanks for your instructions. We removed the fw_name=nxp/sdiouart8997_combo_v4.bin parameter from /lib/firmware/nxp/wifi_mod_para.conf as requested. However, after doing so, the Wi-Fi driver failed to initialize successfully. [ 31.329658] wlan: Loading MWLAN driver [ 31.349418] wlan: Register to Bus Driver... [ 31.353928] vendor=0x02DF device=0x9141 class=0 function=1 [ 31.365740] Attach moal handle ops, card interface type: 0x104 [ 31.371789] rps set to 0 from module param [ 31.384957] SD8997: init module param from usr cfg [ 31.393341] card_type: SD8997, config block: 0 [ 31.398090] cfg80211_wext=0xf [ 31.401682] max_vir_bss=1 [ 31.404360] cal_data_cfg=none [ 31.407714] ps_mode = 2 [ 31.410394] auto_ds = 2 [ 31.416131] host_mlme=enable [ 31.420715] drv_mode = 3 [ 31.423957] sta_name=wlan [ 31.427305] max_uap_bss = 2 [ 31.430680] txpwrlimit_cfg=nxp/tx_power_test.bin [ 31.435583] Mode PSD file name: nxp/tx_power_test.bin [ 31.435772] SDIO: sdio_blk_size=256 max_blk_count=65535 max_segs=128 max_seg_size=65535 [ 31.449893] rx_work=1 cpu_num=4 [ 31.453130] Enable moal_recv_amsdu_packet [ 31.457238] Attach mlan adapter operations.card_type is 0x104. [ 31.467379] wlan: Enable TX SG mode [ 31.470961] wlan: mpa_tx.buf_size=65280 [ 31.474870] wlan: Enable RX SG mode [ 31.541283] Request firmware: nxp/sduart8997_combo_v4.bin [ 31.547021] wlan_sdio mmc1:0001:1: Direct firmware load for nxp/sduart8997_combo_v4.bin failed with error -2 [ 31.557949] wlan_sdio mmc1:0001:1: Falling back to sysfs fallback for: nxp/sduart8997_combo_v4.bin [ 31.572463] WLAN: request_firmware() failed, error code = -11 [ 31.578407] woal_request_fw failed [ 31.582174] Firmware Init Failed [ 31.589377] Free module params [ 31.592582] woal_add_card failed [ 31.596264] wlan_sdio: probe of mmc1:0001:1 failed with error -1 [ 31.604477] usbcore: registered new interface driver usbxxx [ 31.610456] wlan: Register to Bus Driver Done [ 31.615067] wlan: Driver loaded successfully  As a result, no interface appears under iw dev. Regarding the long-term STA issue: we will continue testing using the new firmware/driver version. If the issue can be reproduced again, we’ll proceed to open a separate case. Best regards, Yaoguang 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi, @yangyaoguang  Thanks for your updating. 1. Yes, I know you are using following command with a config file: modprobe moal mod_para=nxp/wifi_mod_para.conf  I mean please modify this config file: /lib/firmware/nxp/wifi_mod_para.conf, remove below parameter. fw_name=nxp/sdiouart8997_combo_v4.bin  Yes, from your given directory contents, I see both combo and Wi-Fi only FW are put there. Please remove this parameter in /lib/firmware/nxp/wifi_mod_para.conf, then let me know your test results. For point 2, please create a new case to us, so that we can track one issue with one case.  In this way, we will not be confused and also won't miss any issue. Best regards, Christine. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Regarding the second point, this issue was observed during long-term testing with an older Wi-Fi firmware, and we are now updating to the latest version to rerun the same test. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi Christine, Just to update you on two points: 1. Driver Load Parameter We are not directly passing fw_name=nxp/sdiouart8997_combo_v4.bin in the driver load command. Instead, we use the following command with a config file: modprobe moal mod_para=nxp/wifi_mod_para.conf Both the combo and WLAN-only firmware files have already been placed under /lib/firmware/nxp/. Directory contents: README_MLAN ed_mac_ctrl_V3_8997.conf mlanutl sd8997_bt_v4.bin sd8997_wlan_v4.bin sdiouart8997_combo_v4.bin sdsd8997_combo_v4.bin tx_power_test.bin txpwrlimit_cfg_8997.conf wifi_mod_para.conf 2. STA Link Failure After Long Uptime A new issue was recently reported by our internal testing team. In a long-term stability test (non-reconnection scenario), the STA interface failed to reconnect after 24 days of continuous operation and required a full reboot to recover. During this time, the device was only sending a single ping to an external host approximately every 60 seconds. Key log: Block woal_cfg80211_del_key in abnormal driver stateThe related log is attached for your reference. Best regards, Yaoguang 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi, @yangyaoguang  Can you please help to remove this driver load parameter: fw_name=nxp/sdiouart8997_combo_v4.bin Also please  copy both (WLAN only and combo FW) in /lib/firmware/nxp path and provide observation. Thanks, Christine. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi Christine, Noted, thank you! Best regards, Yaoguang 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi， @yangyaoguang  Just for your information, I have created an internal case to escalate this case. Once have any updates, I will let you know. Best regards, Christine. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Hi, @yangyaoguang  Thanks for creating new case to us. I will check and reply to you ASAP. For your information, this issue is related to FW reset, it might need our internal SAE team's help for tracking root cause. In other words, it will take longer time for global communications. Please pay more patient about this. Thanks for your understandings! Best regards, Christine. 回复： SD8997 Wi-Fi Fails to Recover After In-Band Reset Triggered by EAPOL Timeout Attachment: dmesg.txt – captured during failure event for reference.