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Guaranteed manufacturing lifetime When we first chose to use the mc9s12xep100 many years ago, part of that choice was based on a guaranteed availablility of supply of at least 15 years. 15 years has now passed, and I'm trying to check on if that has been updated - how much longer can I rely on the mc9s12xep100 being available for purchase as a current part? Re: Guaranteed manufacturing lifetime Dear Grant Kassell, Product Longevity | NXP Semiconductors   ... A Life status after defined period will still depends on the market. The last stage when ctm should be careful is Not Recommended for New Design (now it is good to contact Distributor if you still want to use them in future). followed by Last Order Date and finally End of Life.    Best regards, Ladislav  
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[S32Z] VKMS for HSE-H/M firmware Hi NXP Team! I noticed that S32K has support for VKMS (vehicle key management system). See this post and the application note "an744410 - K3_SecurityWorkshop_VKMS__29Mar2022.pdf (1.0).pdf". Is VKMS (core) also available for the HSE-H/M firmware used for S32Z? Best regards, Philipp Sommer Re: [S32Z] VKMS for HSE-H/M firmware Hi, We understand that all S32Z/E related information is under control of distribution, for which we can recommend contacting your local NXP FAE/DFAE/representative. We do apologize for the inconvenience. Please, let us know. Re: [S32Z] VKMS for HSE-H/M firmware I think we can move this to S32Z2 - NXP Community
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【S32Z】HSE-H/Mファームウェア用VKMS こんにちはNXPチーム! S32KがVKMS(Vehicle Key Management System)をサポートしていることに気づきました。この 投稿とアプリケーションノート「an744410 - K3_SecurityWorkshop_VKMS__29Mar2022.pdf (1.0).pdf」を参照してください。 S32ZのHSE-H/MファームウェアにVKMS(コア)は搭載されていますか? よろしくお願いいたします フィリップ・ソマー 日時:[S32Z] HSE-H/Mファームウェア用VKMS これをS32Z2に移行できると思います - NXP Community
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I2Cコードに関するヘルプが必要(Peripheral Config Toolを使用) I2C1 周辺機器を使用する必要があります。サンプルプログラムを確認しました。しかし、それは実際にはサンプルコードではないと言わざるを得ません。サンプルコードでは、なぜとどのように説明するための良いコメントを期待しているからです。しかし、コメントはゼロです!プログラマーとして、私はそのようなコードを書くことは決してありませんし、ましてやサンプルコードも書きません。 しかし、最悪なことに、この例では、ペリフェラルツールとクロックコンフィグツールを使用しませんが、それが好ましい作業方法と言われています。 だから、自分ですべてを理解しなければなりません。しかし、良い例がなければ、それは難しいことです。とても難しいです。 たとえば、ポーリング、割り込み、転送、eDMA、RTOSのいずれかのモードを選択できます。それらが正確に何を意味するのか、どこかに説明はありますか? プログラマーですが、ポーリング、割り込み、eDMAのアイデアがあると思います。しかし、転送とは何ですか?それらはすべてデータを転送します。そして、なぜRTOSは別のモードなのか。RTOSはeDMAや割り込みもしないの? これらのモードのいずれかを選択した場合、どの機能を使用することになっていますか?これらは、Peripheral Config Tools に基づいていない例と同じですか。 あなたの道を見つけるための期待される方法は何ですか? (そして、どうか、どうか、Config Toolsを使用したサンプルコードを教えてください! Re:I2Cコードに関するヘルプが必要(Peripheral Config Toolを使用) いいえ、mex ファイルはコピーしていませんが、I2C IO ピンを適切に構成し、Clock Config ツールで正しいクロックを確認しました。
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S32K3 MCAL CANFD mask setting bug Hi, All The EDF bit the standard CANFD should be bit 14.but now it is 30. Is it a bug ? and it still exists in rtd5.0.0. In the MCAL code, if you want to send a CANFD frame, you need to have the FDF byte of the CANFD message ID of the incoming parameter to be 1, that is, the Bit14 of the CANFD standard frame is 1. There is a Bug. According to the CANFD frame format CAN_43_FLEXCAN_FD_FRAME_U32 should mask bit 14. Now it is set to bit 30. BRs, xianlong Re: S32K3 MCAL CANFD mask setting bug Hi@wuxianlong Please refer to this post. https://community.nxp.com/t5/S32K/Use-S32K358-flexcan-to-sent-extended-ID/td-p/1993198https://nxp.lightning.force.com/lightning/r/Case/500KA0000039pXzYAI/view Re: S32K3 MCAL CANFD mask setting bug Hi, Sorry, I took a closer look. This is not a BUG, it is a software design. The CANFD_ID transmission parameter requires the user to fill in the maximum two bits of 32U. /** * @{ * @brief Can_IdType * @details Represents the Identifier of an L-PDU. The two most significant bits specify theframe type: * -00 CAN message with Standard CAN ID * -01 CAN FD frame with Standard CAN ID * -10 CAN message with Extended CAN ID * -11 CAN FD frame with Extended CAN ID * @implements Can_IdType_type */ /* Can_CreatePduInfo(id | CAN Can_IdType_type, swPduHandle,length, sdu) */ Can_PduInfo = Can_CreatePduInfo(0U | CAN_43_FLEXCAN_FD_FRAME_U32, 0U, 16U, Can_au8Sdu8bytes); Re: S32K3 MCAL CANFD mask setting bug DataInfo.fd_enable = ((PduInfo->id & CAN_43_FLEXCAN_FD_FRAME_U32) != 0U) ? TRUE : FALSE;
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16位总线和IVT数据的并行NOR-Flash 你好。 在 i.MX7D 参考手册第 1241 页上,IVT 头格式图表明要设置的值为 0xD1-0x0020-0x40 到 .word0xD1002040,但在20132年“i.MX6 IVT结构”中Anson Huang回答说应该是.word0x402000D1。 我认为手册上说的是 0x400 = 0xD100 0x402 = 0x2040 但这是错误的吗? 谢谢! 回复:16位总线和IVT数据的并行NOR闪存 谢谢 Harvey021。 那么安森用小端方式解释了吗? 我很困惑,因为参考手册说它是大端的。
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S32K3のI2Cマスターの強制リセット ねえ S32K324をI2Cマスターとして使用して、I2Cスレーブと通信しています。そこで、I2Cマスターがタイムアウト割り込みをスローすることが発生する場合があることに気づきました。割り込み後、SDAラインとSCLラインの両方がローにプルダウンされますが、これはおそらくタイムアウトが発生したときのマスターの状態です。このタイムアウトにより、I2C バスで完全なデッドロックが発生します。 ここで、I2Cマスターユニットを強制的に別の状態にし、SDAおよびSCLラインを解放してI2Cスレーブをリセットする方法はありますか?ソフトリセットのようなものですか? よろしくお願いいたします フェリクス
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How to connect an IO pin via XBAR to ADC_ENV to trigger ADC conversions? I'm using a iMXRT1011 MCU and I need so synchronize ADC conversions to an external source.  I want to connect a sample clock to some IO pin and make the ADC start conversions on that sample clock. I did read somewhere that one would need to connect the IO via the XBAR to the ADC_ETC module. But I see no XBAR inputs that connect to IO pins. So is it possible? i.MXRT 101x Re: How to connect an IO pin via XBAR to ADC_ENV to trigger ADC conversions? Hi @simmania, I presume you read about this on an RT1050 or RT1060 related post, since these devices do have IOMUX_XBAR_INxx signals. The RT1010, on the other hand, does not have an IOMUX_XBAR_IN signal, so it is not possible for the RT1010. BR, Edwin. 
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[Security] Get UID when load keys Dear NXPs: IC:S32K146 sample:csec_keyconfig_s32k146 in SDK S32DS Phenomenon: /* Extracts the UID. */ bool getUID(uint8_t *uid) When I use this function, I step into the inside of the function and when calling When stat = CSEC_DRV_GetID(challenge, uid, &sreg, mac);, the returned mac values are all 0, but the uid is correct. Since the mac values are all 0, execute the statement stat = CSEC_DRV_VerifyMAC(CSEC_RAM_KEY, verif, 256U, mac , 128U, &verifStatus, 1U);, the verifStatus value is false. question: Although the return value of bool getUID(uint8_t *uid) is false, it does not affect subsequent load key processing, but I would like to know why the CSEC_DRV_GetID(challenge, uid, &sreg, mac) interface, mac is all 0? Re: [Security] Get UID when load keys Hi @Gideon  I guess that this is the problem: Regards, Lukas
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I2Cの IMXRT 1170では、CM7ポーリング方式のi2cサンプルコードを使用して、たとえば、J26ポートに特定のCfg SDL、SDAピンを使用してボードを直接フラッシュすることで検証を試みます。退勤信号を受信していません。 J 10 や J 09 などのピンを変更します。これらは、例の i2c コードでは cfg です。コンパイル後もクロック信号を取得できません。 今、IMXRT 1160で確認したところ、i2cサンプルコードからクロック信号SCLを取得しますが、データSDAから信号は取得しません
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如何标记要从内部 Ram 执行的功能? 你好, 出于性能原因,我需要一些功能(例如中断例程)从内部存储器执行。 当我编译时,似乎还没有使用 Ram 来编写代码。所以我想我必须以某种方式告诉链接器哪些功能需要从 Ram 执行。 我怎样才能做到这一点?我正在使用 MCUXpresso 和 MIMXRT1010-EVK。 我确实在论坛上搜索过这个。并且有关于它的主题,但我很难过滤出正确的信息。 我希望有人能帮助我。 回复:如何标记要从内部 Ram 执行的功能? 非常感谢,这很有效。 我想读那篇文章。但该链接指向一个中国论坛。不幸的是我看不懂中文。
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I2C In the IMXRT 1170, we attempt to verify using i2c example code for the CM7 polling method by flashing the board directly, for instance, but with specific Cfg SDL, SDA pins on the J26 port. not receiving the clock-out signal. I alter the pins, such as J 10 and J 09, which are cfg in the example i2c code. We are still unable to obtain a clock signal after compilation. Now , I checked with IMXRT 1160, we get Clock Signal SCL from i2c Example code, but not get signal from data SDA Re: I2C Hi @sabesh , Thanks for your interest in NXP MMXRT series! If your question is solved, please tell me to close this case, and Accept as Solution. thanks. Wish you a nice day! BR mayliu Re: I2C Hi @sabesh , Thank you so much for your interest in our products and for using our community. If you use MIMXRT1170-EVKB board, you can use LPI2C1_SCL J26-12 and LPI2C1_SDA J26-10. Please pay attention that  In the hardware circuit, SCL and SDA must be connected to pull-up resistors, Software SCL and SDA need set as open drain mode and Software Input On Enabled . Please refer to the next Fig. In I2C communication, there are one master and multiple slaves. The master I2C device generates the clock signal. So I suggest you import a SDK demo about I2C master, For example "evkbmimxrt1170_lpi2c_edma_b2b_transfer_master_cm7". If you want I2C communication run okay, Please connect a I2C slave board. So I suggest you use two board, one is as I2C master, one is as I2C slave. Wish it helps you. If you still have question about it, please kindly let me know. Best Regards mayliu
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The image generated by the provisioning tool does not match, I did not see "FCFB ########################################################################################################## 生成构建脚本: build_image_lnx.sh 生成构建脚本: build_image_win.bat 生成构建脚本: build_image_mac.sh 正在执行脚本C:\Users\Administrator\secure_provisioning00\build_image_win.bat ###脚本: 构建镜像: C:\Users\Administrator\secure_provisioning00\build_image_win.bat Build HAB image nxpimage hab export -c "C:\Users\Administrator\secure_provisioning00\bd_files\imx_application_gen_win.bd"  -o "D:\RT1052_Example Code\Example\1.led_test\hello_world_boot.bin"  "C:\Users\Administrator\secure_provisioning00\source_images\hello_world.srec" Success. (HAB container: D:\RT1052_Example Code\Example\1.led_test\hello_world_boot.bin created.) nxpimage succeeded ### Build flashloader as unsigned bootable image ### nxpimage hab export -c "C:\Users\Administrator\secure_provisioning00\bd_files\unsigned_MIMXRT1050_flashloader_win.bd"  -o "C:\Users\Administrator\secure_provisioning00\bootable_images\unsigned_MIMXRT1050_flashloader.bin"  "C:\nxp\MCUX_Provi_v10\bin\_internal\data\targets\MIMXRT1050\flashloader.srec" Success. (HAB container: C:\Users\Administrator\secure_provisioning00\bootable_images\unsigned_MIMXRT1050_flashloader.bin created.) nxpimage succeeded ###脚本“构建镜像”的结果: 成功(返回代码= [0]成功) 操作的状态: 成功: 构建镜像 Re: The image generated by the provisioning tool does not match, I did not see "FCFB Indeed, this issue has been resolved. thank you. Re: The image generated by the provisioning tool does not match, I did not see "FCFB Hi, in your screenshot I can see the file name has "SDRAM" in it, but also in the screenshot the DCD is not configured, it might be the root cause why the application does not run. Regards, Libor Re: The image generated by the provisioning tool does not match, I did not see "FCFB Hi, may be the training video can help you. There should be all steps captured: Secure Boot on the i.MX RT10xx Crossover MCUs | NXP Semiconductors If you cannot find any information in the user guide, please let us know what information is missing. It is not possible to provide help without information: - what you want to do - what the problem is. Re: The image generated by the provisioning tool does not match, I did not see "FCFB Can't I run the LED program even after writing it in PROVISION TOOL? The image construction is incorrect. I can run it using KEIL's original image. Is it not possible to follow the official manual step by step? The documentation for this tool is not detailed enough. I can't use it. Re: The image generated by the provisioning tool does not match, I did not see "FCFB Hi, MCUXpresso Secure Provisioning tool does not generate the image with FCB, the FCB is written to flash as extra step. The FCB can be specified either as simplified or full configuration. Kindly review generated write script for details.
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MPC5748G FCCU fault details Hello team, Can you please explain the details(especially error condition) of MPC5748G FCCU faults below? 1. NCF[18] / MEMU_0 / System RAM error overflow (all or'ed) 2. NCF[20] / MEMU_0 / Peripheral RAM uncorrectable ECC error (what's the Peripheral RAM?) 3. NCF[25] / PRAM_0 / System PRAM Controller_0 ahb alarm 4. NCF[41] / DMC PRAM1 / DMC PRAM1 FCCU ALARM 5. NCF[43] : PRAM_0 / System PRAM Controller_0 RAM alarm There are two DMC PRAMx FCCU alarm faults - PRAM1 and PRAM2. Why isn't the DMC PRAM0 FCCU alarm fault?  Best regards, James Re: MPC5748G FCCU fault details Hello Peter, Thank you for your answer and please close this. Best regards, James Re: MPC5748G FCCU fault details Hello, 1. NCF[18] / MEMU_0 / System RAM error overflow (all or'ed) 2. NCF[20] / MEMU_0 / Peripheral RAM uncorrectable ECC error (what's the Peripheral RAM?) For example CAN buffers. 3. NCF[25] / PRAM_0 / System PRAM Controller_0 ahb alarm It signals that there was and uncorrectable RAM error on masters AHB. 4. NCF[41] / DMC PRAM1 / DMC PRAM1 FCCU ALARM Alarm signal from DSMC to FCCU 5. NCF[43] : PRAM_0 / System PRAM Controller_0 RAM alarm There are two DMC PRAMx FCCU alarm faults - PRAM1 and PRAM2. Why isn't the DMC PRAM0 FCCU alarm fault? Hmm, hard to answer. I expect it corresponds to 0 and 1. But this would be question for documentation/ application team. You can rise a ticket at NXP.com or get in touch with application engineer. Best regards, Peter
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找到Pflash的Demo工程 你好,我想用S32K311开发Bootloader,涉及到PFlash的擦除、写入、以及bank切换。有了S32DS配置工具,有相关的Demo工程吗?你能和我分享吗?谢谢。
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Find the Demo project of Pflash Hello, I want to use S32K311 to develop Bootloader, which involves PFlash erasing, writing, and bank switching. With the S32DS configuration tool, do you have related Demo projects? Can you share them with me?Thanks. Re: Find the Demo project of Pflash hello @CcW18, There are C40_IP and FLS MCAL RTD examples in S32DS IDE. Unfortunately, there are no examples specifically for S32K311. But still, you can refer to the examples and configure the drivers in your project accordingly. Regards, Daniel
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Does i.MX RT1180 support IEEE802.1QCR? Does i.MX RT1180 support IEEE802.1QCR? I did not find any 802.1QCR for TSN on i.MX RT1180. So I want to double check. Thanks. Re: Does i.MX RT1180 support IEEE802.1QCR? Hi @Sally_Jay  i.MX RT1180 does not support IEEE802.1QCR. Hope this will help you. BR Hang
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Register MC EDAC with Linux EDAC subsystem I have an S32G-VNP-EVB3 board running Linux using the NXP provided BSP 40. I have enabled the EDAC system in the Linux kernel to montior sbes and dbes however I do not see it in the filesystem. Makes me wonder if EDAC is actually enabled on this board? The amount of available memory seems to indicate that it is; though I could not find the memory node in the device tree to double check. Any way for me to be sure? Expect to see edac information here, /sys/devices/system/edac/mc # ls power subsystem uevent  System memory, /sys/devices/system/edac/mc # cat /proc/meminfo MemTotal: 3500312 kB MemFree: 3442776 kB MemAvailable: 3442020 kB Buffers: 1724 kB Cached: 9168 kB SwapCached: 0 kB Active: 7532 kB Inactive: 3924 kB Active(anon): 64 kB Inactive(anon): 640 kB Active(file): 7468 kB Inactive(file): 3284 kB Unevictable: 0 kB Mlocked: 0 kB SwapTotal: 0 kB SwapFree: 0 kB Dirty: 24 kB Writeback: 0 kB AnonPages: 724 kB Mapped: 2116 kB Shmem: 60 kB KReclaimable: 25168 kB Slab: 33908 kB SReclaimable: 25168 kB SUnreclaim: 8740 kB KernelStack: 1376 kB PageTables: 192 kB NFS_Unstable: 0 kB Bounce: 0 kB WritebackTmp: 0 kB CommitLimit: 1750156 kB Committed_AS: 2520 kB VmallocTotal: 259653632 kB VmallocUsed: 1872 kB VmallocChunk: 0 kB Percpu: 656 kB CmaTotal: 262144 kB CmaFree: 260576 kB HugePages_Total: 0 HugePages_Free: 0 HugePages_Rsvd: 0 HugePages_Surp: 0 Hugepagesize: 2048 kB Hugetlb: 0 kB Re: Register MC EDAC with Linux EDAC subsystem Hello, @minersrevolt From BSP perspective, it does not support EDAC at DDR level. Sorry for your inconvenience.   Best Regards Chenyin   Re: Register MC EDAC with Linux EDAC subsystem Is it because this board used inline dram which means the scrubber is obfuscating the results from the MC so the ARMs just dont have access to this information?
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Why does the linker try including a noneexistend crt0 object? Here the part of the log file which shows that the linker tries incoroprating a nonexistent crt0.o object: Building target: DiagnosticsTest_CM7.elf Invoking: Standard S32DS C Linker arm-none-eabi-gcc -o "DiagnosticsTest_CM7.elf" "@DiagnosticsTest_CM7.args" c:/nxp/s32ds.3.5/s32ds/build_tools/gcc_v9.2/gcc-9.2-arm32-eabi/bin/../lib/gcc/arm-none-eabi/9.2.0/../../../../arm-none-eabi/bin/real-ld.exe: cannot find crt0.o: No such file or directory c:/nxp/s32ds.3.5/s32ds/build_tools/gcc_v9.2/gcc-9.2-arm32-eabi/bin/../lib/gcc/arm-none-eabi/9.2.0/../../../../arm-none-eabi/bin/real-ld.exe: cannot find -lc collect2.exe: error: ld returned 1 exit status make: *** [makefile:76: DiagnosticsTest_CM7.elf] Error 1 "make -j12 TOOLCHAIN=linaro" terminated with exit code 2. Build might be incomplete. Please guide me to the S32DS tool option which obviously needs to be adjusted. BTW I also do not see where the option -lc gets set in the tool Re: Why does the linker try including a noneexistend crt0 object? Hi @markusregner, I haven't really tested the project, but I've just imported and built it. Is this the "S32Gx based S32G-VNP-EVBx diagnostics package version 0.8.7" package? By "It was already not compiling any longer", do you mean in the newer versions of S32DS? Is this a new error or has this been known by the SW team since Nov?  The release notes for this package say it is supported by S32DS3.4:  --Complete suite builds out of box with S32Design Studio v3.4 After importing this project, and right clicking for "Properties", go into "C/C++ Build > Tool Chain Editor". The current toolchain for the project should show up.  Just to confirm, after downloading and importing the project, when going into properties, is the NXP GCC 9.2 toolchain selected?  Best regards, Julián Re: Why does the linker try including a noneexistend crt0 object? BTW, Around November 2023 I discussed with members of the NXP SW team the future of this Diagnostic code. At that time it was already not compiling any longer. And the NXP team knew. So I wonder how you got it compiling now. Anyway... I think the question is how can I chose now the right compiler in my S32DS to make it compile again? Re: Why does the linker try including a noneexistend crt0 object? Hi Julian, Yes, this is a migration of an older project which I used for demonstrating certain functionalities to colleagues and customers. Hence, yes likely it was built with a different GCC at that time. I tried the workaround described in the link which you sent. It made things even worse. It lead to 135 errors.  Well to my best knowledge I imported the project just as normal. So how can I fix it? BTW, I also wonder why a different GCC compiler lead to a failure message about crt0.o?  Existence and Absence of such file should matter of the project and not matter of the compiler version.  Best regards, -Markus Re: Why does the linker try including a noneexistend crt0 object? Hi @markusregner, Could you share some information from your project?  Are you building the diagnostic tests for S32G-VNP-EVBx Diagnostics? Also, I see on the path that gcc 9.2 is being used, but when importing the EVBx Diagnostics project on my side, I can build them correctly using the default gcc (6.3): Finished building: ../src/s32g_test_all.c Building target: DiagnosticsTest_CM7.elf Invoking: Standard S32DS C Linker arm-none-eabi-gcc -o "DiagnosticsTest_CM7.elf" "@DiagnosticsTest_CM7.args" Finished building target: DiagnosticsTest_CM7.elf Invoking: Standard S32DS Create Flash Image arm-none-eabi-objcopy -O binary DiagnosticsTest_CM7.elf "DiagnosticsTest_CM7.bin" Invoking: Standard S32DS Print Size arm-none-eabi-size --format=berkeley DiagnosticsTest_CM7.elf text data bss dec hex filename 158264 481664 247728 887656 d8b68 DiagnosticsTest_CM7.elf Finished building: DiagnosticsTest_CM7.siz Finished building: DiagnosticsTest_CM7.bin 13:12:32 Build Finished. 0 errors, 151 warnings. (took 22s.434ms) Did you port the example? Are you using another package? This issue may be caused by different GCC versions. Also, take a look at this community post with a similar issue, it was resolved by copying some configuration from the GCC path: Facing Issue with Make file S32K144 [crt0.o : No such Directory] - NXP Community Best regards, Julián
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GD3162 gate driver SC fault Hi NXP, What could be the reason that INTB is going to 2.5V from 5V in the case of a short circuit fault ? Can there be any causes in SW? Any possibility ? Re: GD3162 gate driver SC fault Hello Could you please let me know the result? Additionally, would you be able to test the INTB connected directly to the microcontroller? Re: GD3162 gate driver SC fault And also, INTB before connecting to micro is externally given a pull-up to 5V through a 10K resistor Re: GD3162 gate driver SC fault Hi, FYI, in our project, all the INTB pins are connected to one pin of the micro so that if any one of the gate drivers (6 gate (RH, YH, BH and RL, YL, BL) for 3 phase motor) encounters a fault, the PWM is cut off for all. In the attached image you can see that ISENSE pin of the R-L gate driver is supposed to detect phase over current cut off through SC fault and ISEN of Y-L gate driver is supposed to detect DC over current cut off through SC fault. In our case whenever ISEN of YL detects DC bus over current cut off, in that case INTB is going to 2.5V and when phase over current cut off occurs, then INTB is further transitioning from 2.5 to 0. I've noted your point to disconnect INTB from micro and check the signal again. Re: GD3162 gate driver SC fault Hello, Is the INTB pin directly connected to the microcontroller? Please note that the INTB pin has an internal passive pull-up to VDD, and INTB reports faults with an active low signal (logic 0 indicates a fault). According to the datasheet, the INTB pin should indeed be connected directly to the microcontroller. Could you confirm whether, when disconnecting the microcontroller from the INTB pin, the voltage remains at 2.5V in the event of a fault?
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