fs23 が LPOFF の入力に失敗する FS23がLPOFFモードに入るように制御するために、S32K312を使用してSPI経由でFS23と通信しています。次のように、SPI を介して LPOFF コマンドを送信しました。 まず、SBC_FS23_M_SYS_CFG_ADDRレジスタの値を読み取ります。 Sbc_fs23_ReadRegister(1, SBC_FS23_M_SYS_CFG_ADDR, &M_Sys_Cfg_RxData); 次に、SBC_FS23_M_SYS_CFG_ADDRレジスタの読み取り値を書き込み、LPOFFスリープモードのSBC_FS23_M_GO2LPOFF_MASKを0x0040(1<<6)に設定しました。 Sbc_fs23_WriteRegister(1, SBC_FS23_M_SYS_CFG_ADDR, M_Sys_Cfg_RxData |SBC_FS23_M_GO2LPOFF_MASK、&pu16RxData_LDT); しかし、FS23はLPOFFモードに入らず、再度レジスタ値を読み込んでも変化していませんでした。SPI通信が正常に機能していることを確認できます。外部ウェイクアップ ソースが接続されていません コンフィギュレーションに問題があるのか、それともコンフィギュレーションが必要な他のレジスタがあるのか、教えてください。 日時:fs23がLPOFFに入るのに失敗する SPIがレジスタへの書き込みに失敗したため、この状況につながったためであるべきだとわかりました。ただし、fs23 は実際には通常モードであり、ウォッチドッグ タイマーも無効になっています。しかし、SPIを介してデータを読み取るのに問題はなく、データの書き込みも正常に返されます。 日時:fs23がLPOFFに入るのに失敗する M_IOWU_FLGレジスタ 日時:fs23がLPOFFに入るのに失敗する どのレジスタに入っているか教えていただけますか? 日時:fs23がLPOFFに入るのに失敗する 1.M_SYS_CFGレジスタの値は21507(0101010000000011)です。 2.表記値は21571(0101010001000011)です。 書き込みが成功したかどうかを確認する 3.To、再読み取りする値も21507(0101010000000011)です。 この問題は何日も私を悩ませてきました。何か指導をお願いします。 日時:fs23がLPOFFに入るのに失敗する きっとノーマルモードになっていると思いますので、レジスタSBC_FS23_M_SYS_CFG_ADDR(0x05)に書き込んでLPOFFモードに入りたいです。私の手順は次のとおりです。 ステップ1:SPIを介してレジスタSBC_FS23_M_SYS_CFG_ADDR(0x05)の値を読み取ります。 ステップ2:この値とSBC_FS23_M_GO2LPOFF_LPOFF(0x0001U << SBC_FS23_M_GO2LPOFF_SHIFT)の間でビットごとのOR演算を実行し、結果をSBC_FS23_M_SYS_CFG_ADDR(0x05)に書き戻してfs23をスリープモードにします。 日時:fs23がLPOFFに入るのに失敗する M_STATESレジスタ値12295(バイナリ表現:0011000000000111)について、bit13は1でノーマルモードを示します。 M_SYS_CFGレジスタの値は 21507 (0101010000000011) ですが、正常に変更されていません。 Re: fs23 fail to enter LPOFF 本当に通常モードですか？LPOFFモードに入るためにどのようなコマンドを送信しましたか？ Re: fs23 fail to enter LPOFF M_SYS_CFGレジスタを「xxxx x000 0100 0011」と書きます。試してみてください。「x」は任意の値を表します。 日時:fs23がLPOFFに入るのに失敗する ステップ1:SPIを介してレジスタSBC_FS23_M_SYS_CFG_ADDR(0x05)の値を読み取ります。 [gw]读出来的值是多少这个寄存器？ ステップ2:この値とSBC_FS23_M_GO2LPOFF_LPOFF(0x0001U << SBC_FS23_M_GO2LPOFF_SHIFT)の間でビットごとのOR演算を実行し、結果をSBC_FS23_M_SYS_CFG_ADDR(0x05)に書き戻してfs23をスリープモードにします。 [gw]写进去 M_SYS_CFG register 的值是多少？写过以后有没有再读一下验证写成功有否？

IMXRT1052 XIP 暗号化の問題 専門家に聞いてもいいですか:RT1052 + XIP暗号化方式?ヒューズを燃やさずにチップのUIDをキーとして使用する場合、イメージを暗号化して生成するにはどのソリューションを選択すればよいですか?ヒューズを燃やした後、チップが再利用できなくなるのが心配だからです。暗号化のための良い方法があるかどうか尋ねてもいいですか。また、工場にとっても大量生産を促進することは有益です。 Re:IMXRT1052 XIP暗号化の問題 こんにちは： MFGTOOLはUSBのみをサポートし、UARTをサポートする製品ソフトウェアを持っていますか?

Unable to debug i.MXRT1189 on cm33 core Hello, Can anyone help me out on this issue. I am trying to debug baremetal firmware in i.MXRT1189 evk and each time i am getting the error as per the image attached with this. i am able to debug successfully on cm7 core but not on cm33 core.  #i.MXRT1189  Re: Unable to debug i.MXRT1189 on cm33 core Hello @kerryzhou Yes i got the same solution from nxp technical team and the boot switch position was 0001 initially which was a serial downloader. Thank you very much for your support. but i think some configuration is still need to be done because i am getting the same error when i create a new c/c++ project for both cm7 and cm33 cores. Re: Unable to debug i.MXRT1189 on cm33 core Hi @vilas_shetty ,   Please check my test result: You can see the cm33 project can be entered. SW5: 0100 And the debugger is using the on board CMSIS DAP debugger, J53. Please try it again, thanks. If you still have issues, you even can refer to my document: https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/How-to-create-RT-AVB-switch-amp-endpoint-platform/ta-p/1898344 chapter 2.3.2 RT1180 AVB switch, Use the mcubootutility to download the cm33 code. The code can try the mcubootutility attached cm33 code: Wish it helps you! If you still have question about it, please kindly let me know. if your question is solved, please tell me to close this case, and help me to fill the feedback as resolved, thanks. Any new issues, welcome to create the new case. Best Regards, Kerry Re: Unable to debug i.MXRT1189 on cm33 core Hello kerryzhou, Thank you and will be waiting for your response. Re: Unable to debug i.MXRT1189 on cm33 core Hi @vilas_shetty ,    Thanks for your updated information.   Please give me more time, I will help you to check it tomorrow, as I don't have the board on my hand right now, I will find board and test it on my side tomorrow, then give you updated information. Thanks a lot for your understanding. Best Regards, Kerry Re: Unable to debug i.MXRT1189 on cm33 core Hello @kerryzhou, I am still facing the same error even after i tried with helloworld cm33 demo project. Board details: mimxrt1180-evk reversion number - SCH-50577 REV C3, 700-50577 REV C SDK version - 2.16.000 Re: Unable to debug i.MXRT1189 on cm33 core Hi @vilas_shetty ，   Thank you for your interest in the NXP MIMXRT product, I would like to provide service for you.   Do you try the SDK demo code, eg, the helloworld cm33 project, whether that code downloading works or not?  BTW, please tell me your side information: 1. mimxrt1180-evk reversion number 2. Your used SDK version, please also try the helloworld or the led_blinky project, cm33,  If you still have issue about it, please kindly let me know. Best Regards, Kerry

How to Configure Clock for 24 bit 48 Khz I2s transfer in lpc55s69-evk As per the calculation the BCLK frequency  required is 2304000Hz. I seem to be getting the FXCOMCLK7 clkin(23.04Mhz) as a multiple of BCLK required. But MCLK also has to be multiple of BCLK. But MCLK seem to be not using the fractional clock divider output. Please share some inputs to configure the clock correctly Re: How to Configure Clock for 24 bit 48 Khz I2s transfer in lpc55s69-evk The noise sound issue is resolved after updating the Dma input buffer to the I2S. I was using same address as DMA source address. Updated it to a ring buffer as in SDK example to resolve the issue. Thanks Re: How to Configure Clock for 24 bit 48 Khz I2s transfer in lpc55s69-evk 2 channels. I think I am able to generate the clocks properly. MCLK is 46.08 Mhz, Bclk is 2.304 Mhz(Verified with DSO). Audio is playing with small noise in the output sound. Could you share some inputs to debug. Do we need to update any setting for the codec when we update the the sampling rate to 48 khz in 24 bit mode. I have used sdk example lpcxpresso55s69_dev_audio_speaker_freertos as reference Re: How to Configure Clock for 24 bit 48 Khz I2s transfer in lpc55s69-evk Hello @dawnpaul100  Please tell me how many channels does your I2S have? BR Alice

Questions about the internal SRAM of S32G Hi， I recently tested the bootloader to boot multi-core programs and found that the bootloader will move the complete bin file of each M7 core from QSPI to internal SRAM and then execute it. However, I noticed that the internal SRAM of S32G2 is only 8M, and the space allocated to each M7 core in LD is about 1M. Question: If my M7 core program is very large, such as 10M, how should I operate it? thanks， Re: Questions about the internal SRAM of S32G Hi chenyi,     As we know, if multi-core is enabled, it takes a long time for A-core to boot Linux. During the startup of Core A, if Core M collects 100MB of data that requires saving, how should this be handled?      I'm having this problem right now.S32G QSPI issue - NXP Community Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your reply. In common,  the 8M of SRAM should be bigger enough to run a M7 application, I suggest checking the code to reduce the size. Regarding to XIP, yes, it is theoretically supported,  but there are no example or some documentations about XIP on S32G. It's not easy and not common to implement XIP from NOR flash on S32G,  the S32G didn't have internal nor flash, so the cpu can not directly access the nor flash. you could use a bootloader to initialize the QSPI controller and DDR controller at first and then let cpu to execute the application stored in Qflash or DDR on running time. I hope it will help.  BR Chenyin Re: Questions about the internal SRAM of S32G hi, 已解决: S32G2xx M7 execute code from external flash ? - NXP Community I saw this document introducing an XIP(eXecute-In-Place) mechanism that can execute code from external flash. Do you have any relevant materials or demos? thanks Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for you reply. As per my understanding, there is not formal sample/document regarding to this topic, you may reference the ddr init code from A53 side if willing to initialize the DDR for M7 side. Sorry for your inconvenience. BR Chenyin Re: Questions about the internal SRAM of S32G hi， Do you have any relevant demos or materials within NXP? thanks Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your reply. Yes, I think both method may work for your situation, but as far as I know , most customers do not use DDR from M core side, it is  one option to solve your specific case. BR Chenyin Re: Questions about the internal SRAM of S32G Hi， What do you mean, if the M core wants to execute a large image, there are two options: 1. M7 first transfers a portion of the code to the internal SRAM for initializing DDR. After initializing DDR, the complete code is transferred to DDR for execution; 2. The M7 core waits first, and after the A core initializes the DDR, it moves the M7 core image to the DDR and executes it; Is that so? Re: Questions about the internal SRAM of S32G Hello, @youke  Thank for the reply. If the large size image is indeed caused by code(for example, large libs linked) and cannot be resized via linker file, then it cannot be directly loaded to the SRAM to run.  if so, I think you may have to initialize the DDR for running the code. But, unlike A53 side, the DDR is not by default enabled from sample code/bootloader from M7 side. BR Chenyin Re: Questions about the internal SRAM of S32G hi, Thank you for your reply Because I have written too much code, the compiled file is very large. Based on your answer, S32G2 does not support M7 core images exceeding 8MB because they cannot be copied to internal SRAM for execution. Is that correct? Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your reply. I am not sure why your images are so large, since they have been far larger than the 8M ram size(24 M in total). One possible method is to check the linker file, for example,  edit it to make it to 1-2M size each. Then re-build 3 images, note that do not overlap the address of each other. If the big size of image is because multi-libs linked(large sized libs), then edit the linker file may not work for the case from my understanding. BR Chenyin Re: Questions about the internal SRAM of S32G Hi， We will use three M7 cores to run separate programs here, with each core having an image size of approximately 8M, totaling 24M, Because the internal SRAM of S32G2 is only 8MB, how should I plan the LD file thanks, Re: Questions about the internal SRAM of S32G Hello, @youke  Thanks for your post. In common, the actual size of the M7 image would not be that so big, if so, I suggest modify the linker file to change the address range of each part, thus resize the image.  BR Chenyin

MCU-Link compatibility with the iMX93's M33 processor Hello Community, We need to flash, debug and read logs from the iMX93's M33 processor, using the MCUXpresso VSCode extension. Would any of the following options allow us to use SWD/SWO with the iMX93: MCU-LInk MCU-Link Pro with default firmware MCU-Link Pro with J-Link LITE firmware The Getting Started doc for the iMX93 mentions only the Segger J-Link Plus. Enrique Re: MCU-Link compatibility with the iMX93's M33 processor Thank you Re: MCU-Link compatibility with the iMX93's M33 processor Hi @enrique001! At the moment we only validate the Segger J-Link Plus. According to the documentation of Segger the MCU-Link Pro with J-Link LITE firmware should support iMX processors too, but that are not validated by us. You can contact to Segger to confirm if MCU-Link Pro with J-Link LITE firmware supports iMX93. Best Regards! Chavira

Basics of Bus Fault in S32DS Program Hi team, I was trying to run a simple complementary program on a S32K358 microcontroller using the S32DS IDE. But i'm facing an error called as bus fault in the program. I have attached the highlighted screenshot of the error message below. I ran the same program in an S32K344 evaluation board and there I didn't face such an error. Please explain me this fault and also the solution to this as I'm new to this IDE's programming. It would be really helpful. S32DS-S32PLATFORM #S32K358 #BusFault  Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  I sent you a private message Re: Basics of Bus Fault in S32DS Program Hi @VaneB  This is the Lpspi_Ip_UpdateTransferMode() function in my code Lpspi_Ip_StatusType Lpspi_Ip_UpdateTransferMode(uint8 Instance, Lpspi_Ip_ModeType Mode) { Lpspi_Ip_StateStructureType* State; Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS; #if (LPSPI_IP_DMA_USED == STD_ON) Dma_Ip_LogicChannelTransferListType DmaTcdList[1u]; #endif #if (LPSPI_IP_DEV_ERROR_DETECT == STD_ON) DevAssert(Instance < LPSPI_INSTANCE_COUNT); #endif State = Lpspi_Ip_apxStateStructureArray[Instance]; #if (LPSPI_IP_DEV_ERROR_DETECT == STD_ON) DevAssert(NULL_PTR != State); #endif /* Transfer mode can be changed when no transfers are in progress. */ if (State->Status != LPSPI_IP_BUSY) { State->TransferMode = Mode; #if (LPSPI_IP_DMA_USED == STD_ON) if (TRUE == State->PhyUnitConfig->DmaUsed) { /* Activate TX DMA and RX DMA interrupt in interrupt mode or disable then in polling mode. */ DmaTcdList[0u].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT; switch (State->TransferMode) { case LPSPI_IP_POLLING: /* Disable DMA major interrupt. */ DmaTcdList[0u].Value = 0u; break; case LPSPI_IP_INTERRUPT: /* Enable DMA major interrupt. */ DmaTcdList[0u].Value = 1u; break; default: /* Nothing to do */ break; } (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 1u); (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, DmaTcdList, 1u); } #endif } else { Status = LPSPI_IP_STATUS_FAIL; } return Status; } The below mentioned are the SPI configurations, SpiDriver   SpiGeneral Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  It seems that your code fails in the Lpspi_Ip_UpdateTransferMode() function. How do you call this function? Also, could you share the SPI configurations? Re: Basics of Bus Fault in S32DS Program Dear @VaneB, Here is the screenshot of the right side of debug window you requested. What could be the problem? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  Could you share a picture of the Debug tab displayed on the left side of the S32DS during debugging? This tab shows where the code failed. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  In a new custom project file, I'm now experiencing this type of bus and hard fault with the message highlighted as shown, , I haven't connected any peripherals or devices to the custom microcontroller. Do you think that the fault is due to the SPI data not being transmitted/received to the controller? Or is it something else? Re: Basics of Bus Fault in S32DS Program Hi @VaneB  You were right about the failure in the Clock_Ip_init() function. The problem was not with the hardware. The problem was in specifying the right clock frequency in the FXOSC section in the clock configuration tool (which makes the Clock_Ip_init() function). My custom hardware was using 40 MHz oscillator and I was running the code in 16 MHz FXOSC in the clock configuration tool of my program. Once I changed that to 40 MHz and uploaded the code again, the busfault error was gone and the code was running.  Thanks for all the help you have given me sir. I deeply appreciate it. Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  From the shared images I deduce that it is a clock problem because the failure occurs in the Clock_Ip_init() function. To verify if this is the case, test the Clock_Ip_Example_S32K358 making the necessary changes to match your HW. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  As per the Hardware Design Guidelines for S32K3xx Microcontrollers the crystal oscillator design of our hardware seems to be correct. What could be other possible hardware/software reason(s) for the BusFault and HardFault errors? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  It seems to be a hardware problem. Since the Hard fault occurs during clock initialization, a possible root cause could be the connections of the EXTAL and XTAL pins, for this you can use as a reference the Hardware Design Guidelines for S32K3xx Microcontrollers. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  I ran the Emios_PWM_Ip example code, that comes with the SDK, on my custom board with the S32K358 controller. I'm still getting the same HardFault error mentioned before. What could be the problem then? Re: Basics of Bus Fault in S32DS Program Hi @VaneB  Yes, you are right. I'm using a custom made board which uses the S32K358. What may the problem then? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  I have flashed your code on my S32K3X8EVB-Q289 and I did not get a bus Fault. Are you using a custom board? Is it necessary to use both Cortex-M7_0_0 (Boot) and Cortex-M7_0_2 files for programming S32K358? No, depends if you want to work with multicore.  Why does the design studio create two files for this processor and only one file for S32K344? Because S32K358 devices have 1 LS core and 1 single core and S32K344 devices have only 1 LS core. So one project is created for each device core. Re: Basics of Bus Fault in S32DS Program Hi @VaneB  I have attached the .zip file of the project that the code is in. I'm using version 4.0.0 of PlatformSDK kit from NXP.  P.S.: Is it necessary to use both Cortex-M7_0_0 (Boot) and Cortex-M7_0_2 files for programming S32K358? Why does the design studio make two files for this processor and only one file for S32K344?? Re: Basics of Bus Fault in S32DS Program Hi @abdul_rahman  BusFault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit). HardFault: is the default exception and can be triggered because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. If there is no handler for a specific fault, it is escalated to HardFault. As the code works with a S32K344, there could be a configuration problem. If it is possible could you share your project or configurations? Also, which RTD version are you using?  BR, VaneB

optee with rpmb error 0xffff0007 TEE_ERROR_BAD_DATA I am Working on Optee in imx8mm device and xtests and other applications were working fine. However, then I enabled the following flags in Optee-os ``` EXTRA_OEMAKE:append = " \ CFG_RPMB_FS=y \ CFG_RPMB_WRITE_KEY=y \ CFG_RPMB_FS_DEV_ID=0 \ CFG_RPMB_TESTKEY=y \ CFG_REE_FS=y \ " ``` and added the` RPMB_EMU=0` in tee-supplicant/Makefile in optee-client but after doing these changes, all my tests are failing ``` * regression_1004 Test User Crypt TA /usr/src/debug/optee-test/3.19.0.imx-r0/git/host/xtest/regression_1000.c:459: xtest_teec_open_session( &session, &crypt_user_ta_uuid, ((void *)0), &ret_orig) has an unexpected value: 0xffff0007 = TEEC_ERROR_BAD_STATE, expected 0x0 = TEEC_SUCCESS regression_1004 FAILED * regression_1005 Many sessions /usr/src/debug/optee-test/3.19.0.imx-r0/git/host/xtest/regression_1000.c:551: xtest_teec_open_session(&sessions[i], &concurrent_ta_uuid, ((void *)0), &ret_orig) has an unexpected value: 0xffff0007 = TEEC_ERROR_BAD_STATE, expected 0x0 = TEEC_SUCCESS regression_1005 FAILED * regression_1006 Test Basic OS features /usr/src/debug/optee-test/3.19.0.imx-r0/git/host/xtest/regression_1000.c:570: xtest_teec_open_session(&session, &os_test_ta_uuid, ((void *)0), &ret_orig) has an unexpected value: 0xffff0007 = TEEC_ERROR_BAD_STATE, expected 0x0 = TEEC_SUCCESS regression_1006 FAILED * regression_1007 Test Panic /usr/src/debug/optee-test/3.19.0.imx-r0/git/host/xtest/regression_1000.c:594: xtest_teec_open_session(&session, &os_test_ta_uuid, ((void *)0), &ret_orig) has an unexpected value: 0xffff0007 = TEEC_ERROR_BAD_STATE, expected 0x0 = TEEC_SUCCESS regression_1007 FAILED * regression_1008 TEE internal client API o regression_1008.1 Invoke command /usr/src/debug/optee-test/3.19.0.imx-r0/git/host/xtest/regression_1000.c:738: xtest_teec_open_session(&session, &os_test_ta_uuid, ((void *)0), &ret_orig) has an unexpected value: 0xffff0007 = TEEC_ERROR_BAD_STATE, expected 0x0 = TEEC_SUCCESS regression_1008.1 FAILED o regression_1008.2 Invoke command with timeout /usr/src/debug/optee-test/3.19.0.imx-r0/git/host/xtest/regression_1000.c:759: xtest_teec_open_session(&session, &os_test_ta_uuid, ((void *)0), &ret_orig) has an unexpected value: 0xffff0007 = TEEC_ERROR_BAD_STATE, expected 0x0 = TEEC_SUCCESS regression_1008.2 FAILED o regression_1008.3 Create session fail n = 0 ``` Note: I am using optee_os_3.19 version right now. I have not touched the emmc rpmb before. I even removed the `CFG_REE_FS=y` flag but it still gave the same results i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Re: optee with rpmb error 0xffff0007 TEE_ERROR_BAD_DATA Sorry this function is called for IMX I guess, the other one is called for plat-zynqmp Re: optee with rpmb error 0xffff0007 TEE_ERROR_BAD_DATA Hi! I am already running as sudo user. Here I have gone to more details and found some reason for error. I dry run the optee code (I can't see optee logs due to some reason ) and I found out the error was coming from here. I just wanna ask that I just want to fuse the testkey, what it has to do with HW Unique key and which flags I need further to write the test key on rpmb. Should I need to Fuse OTP necessarily?        For security reasons, we don't allow writing the RPMB key using the  development HUK even though it is unique.       Re: optee with rpmb error 0xffff0007 TEE_ERROR_BAD_DATA Hello, Please make sure to run tee-supplicant with sudo before running the test. https://github.com/OP-TEE/optee_os/issues/865#issuecomment-228551328 Best regards/Saludos, Aldo.

how do i know if a clock is enabled already? If I need to init ADC and QDC,  and they both use XBARA, and `CLOCK_EnableClock(kCLOCK_Xbar1);` is invoked twice. Would it be a problem that kCLOCK_Xbar1 enable twice? Is there a function I can use to know if the module already has been enabled before I try to enable the module? Re: how do i know if a clock is enabled already? Hello @5angxr, It is not a problem to use "CLOCK_EnableClock(kCLOCK_Xbar1);" twice, this because the clock will be enabled. Also, to know if the clock is enabled you can see the bits 22 and 23 in the register called "CCM Clock Gating Register 2" where is in the chapter 14.7.23 in the RM. As shows the next image: Also, if you experience any issue, do not hesitate to let me know. BR Habib Re: how do i know if a clock is enabled already? RT1042 Re: how do i know if a clock is enabled already?   Hello @5angxr, Sorry for taking a while to get back to you. In order to support you better, can you provide me which RTxxxx you are currently using? BR Habib

Industrial i.MX8QM clock frequencies Hi everyone, We are currently doing tests on the MIMX8QM5CVUFFAB and found some strange behaviour regarding clocks. The first thing we noted is that even though the clock is limited to 1.3 GHz for the Cortex A72 and 1.104 GHz for the Cortex A53, the cpufreq driver allows us to set the higher frequency of 1.6 GHz and 1.2 GHz. The SCFW seems to correctly ignore the higher frequencies but this leads to a missmatch between cpufreq and the actual clock rate: root@apalis-imx8-15556460:~# cat /sys/bus/cpu/devices/cpu4/cpufreq/scaling_cur_freq 1596000 root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep a72 a72_clk 0 0 0 1296000000 0 0 50000 Y cpu4 no_connection_id root@apalis-imx8-15556460:~# cat /sys/bus/cpu/devices/cpu0/cpufreq/scaling_cur_freq 1200000 root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep a53 a53_clk 0 0 0 1104000000 0 0 50000 Y cpu0 We would expect that this is either solved by a special cpufreq driver or then by a fdt fixup in U-Boot. However, I can't find any of this solutions in the BSP. Can you confirm that this is currently not implemented? A second clocking issue affects the GPU, even though according to the datasheet the GPU should only run at 625 MHz it runs at 800MHz: root@apalis-imx8-15556460:~# cat /sys/kernel/debug/gc/clk gpu0 mc clock: 797983833 HZ. gpu0 sh clock: 996002801 HZ. gpu1 mc clock: 798002539 HZ. gpu1 sh clock: 995989749 HZ. root@apalis-imx8-15556460:~# cat /sys/kernel/debug/clk/clk_summary |grep gpu gpu_shader1_clk 0 0 0 996000000 0 0 50000 Y 54100000.gpu shader gpu_core1_clk 0 0 0 798000000 0 0 50000 Y 54100000.gpu core gpu_shader0_clk 0 0 0 996000000 0 0 50000 Y 53100000.gpu shader gpu_core0_clk 0 0 0 798000000 0 0 50000 Y 53100000.gpu Here the SCFW does not limit the clock, which seems to be a violation of what is written in the datasheet. My expectation would also be here that there is a fdt fixup in U-Boot to address this but I could not find it. Can you confirm that this is currently not implemented? The version of the SCFW, ATF and U-Boot should be recent enough to properly support the i.MX8QM with the 1.3 GHz limitation: U-Boot 2024.04-34984-g64f00b21ff8 (Dec 04 2024 - 14:42:45 +0100) CPU: NXP i.MX8QM RevB A53 at 1104 MHz at 33C DRAM: 4 GiB Core: 203 devices, 24 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: Toradex 0091 Apalis iMX8QM 4GB WB IT V1.1A Serial#: 15556460 Boot: MMC0 Reset cause: POR BuildInfo: - SCFW 83624b99, SECO-FW c9de51c0, IMX-MKIMAGE ca5d6b2d, ATF 616a458 - U-Boot 2024.04-34984-g64f00b21ff8 Best regards, Stefan i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Re: Industrial i.MX8QM clock frequencies current bsp is based on nxp mek board, don't find specific bsp for industrial, you can change the bsp by yourself Re: Industrial i.MX8QM clock frequencies Hi @joanxie  Thanks for the update. Can you point me to the right BSP for the industrial version of the i.MX8? Thanks and best regards Stefan Re: Industrial i.MX8QM clock frequencies the bsp you used isn't for industrial, so the A72 core define 1596000000 as max, you can remove this from a72_opp_table: opp-table-1 linux-imx/arch/arm64/boot/dts/freescale/imx8qm.dtsi at lf-6.6.y · nxp-imx/linux-imx · GitHub you also can refer to this workaround, for the 1.3G imx8qm  [OUTDATED] Workaround for de-rating i.MX 8QM/QP parts before SCFW 1.16.0 releases - NXP Community Re: Industrial i.MX8QM clock frequencies Hi @joanxie  The following versions are used: SCFW: 1.17.0 (83624b99) U-Boot: lf_v2022.04 https://github.com/nxp-imx/uboot-imx/tree/lf_v2024.04 Linux: lf-6.6.y https://github.com/nxp-imx/linux-imx/tree/lf-6.6.y Regards, Stefan Re: Industrial i.MX8QM clock frequencies what bsp version and SCFW version do you test? let me double check it

SBC FS26 state Flow Hello, its a bit difficult to understand the Simplified functional state diagram given in the datasheet of FS26 as somethings are not mentioned Detailly, is there any Documented or Video kind of thing where this is Explained detailly, if not Can someone Explain it in the Post. Re: SBC FS26 state Flow Hello @JozefKozon , I have the Eval-Board RDK358BMU, and facing some issue with FS26 w.r.t Standby mode and wakeup.  could you please send me the same document ? would also appriciate if you send me an example, considering Eval-Board RDK358BMU. B.T.W , my company has already a valid NDA. thanks in advance BR Abdullah Re: SBC FS26 state Flow @JozefKozon Please send me this file. It has already been established that there is a valid NDA agreement. Thank you. Re: SBC FS26 state Flow @JozefKozon Could you do me a favor and send me an email with the requested FS26 diagram. I would appreciate it very much. Re: SBC FS26 state Flow Hi Djuric, thank you for creating the case. I see it already in our inbox. We will support you via the case. For your company name, yes I have entered incorrect name. I have read your company name from your email address, but this is not correct one. In the case you created I see your company name in the description and for this, yes there is a valid NDA in our database. With Best Regards, Jozef Re: SBC FS26 state Flow I opened a new ticket. The only problem I can think of is that you entered the wrong name of the company I work for. If you contact me by private message, I will send you the exact name of the company as well as the tag from the NDA contract. This whole process is very slow and unnecessarily complex... Re: SBC FS26 state Flow Dear Djuric, I apologize for a late reply. I have checked our NDA database and unfortunately I couldn't find your company listed there. If the NDA was signed only recently, it is possible that it wasn't entered into our system yet. Please create a new case here and we will support you via the case. I apologize for inconvenience and thank you for your understanding.  With Best Regards, Jozef Re: SBC FS26 state Flow @JozefKozon I would appreciate it if you could send me the same FS26 diagram you mentioned in the previous comment. The company I work for has a signed NDA agreement with NXP, which I also uploaded via the NXP website. Thank you. Re: SBC FS26 state Flow @JozefKozon Can you send me the same document? My company has a valid NDA agreement with NXP. Thank you. Re: SBC FS26 state Flow Hello @JozefKozon  Can you please send me this file as well, please? Re: SBC FS26 state Flow Hi Jozef, Yeah, Just gone through the Application Note, things are somewhat clear in this. Thank you for the Document. Re: SBC FS26 state Flow I am using FS26 Safety system basis chip with low power for ASIL D/ASIL B (ds616040-FS26) Datasheet, isn't it the same ? Re: SBC FS26 state Flow Hi Naveen,  I have sent you an email. With Best Regards, Jozef

Configuring memory protection unit (MPU) in i.MX RT1040 Hello, I am trying to enable the MPU for RT1040 and configure a couple of sections of the RAM as non-executable. I am unable to find the relevant document / example code to be able to configure the MPU for this chip. From this link https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/TEE-for-ARM-Cortex-M7-based-MCU/td-p/1753242, I got information about the “tee_fault” example in “SDK_2_16_000_MIMXRT1160-EVK” and learned about the McuXpresso Config TEE tool. But this tool is not supported for RT1040. So, my questions are: How do I configure the MPU for RT1040 processor? Are there any example code / documentation which I can refer to? Thanks Re: Configuring memory protection unit (MPU) in i.MX RT1040 Thank you. I think I can proceed with these references. Re: Configuring memory protection unit (MPU) in i.MX RT1040 Hi @rd24  - Firstly, I would like to share the dedicated application note about the cache system that includes the L1 cache, memory types, attributes and MPU (Memory Protection Unit) https://www.nxp.com/docs/en/application-note/AN12042.pdf - There are no any dedictaed examples about MPU feature, but you can understand from below sample code in many examples. https://github.com/nxp-mcuxpresso/mcux-sdk-examples/blob/52b428258efda7d5bd8a2ace2195ca828356743a/evkmimxrt1040/demo_apps/hello_world_virtual_com/hello_world.c#L85  MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); /* Enable MPU */ ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); Re: Configuring memory protection unit (MPU) in i.MX RT1040 Hi @Sam_Gao, Thanks for your quick reply. I have checked the BOARD_ConfigMPU() function from the hello_world example and understood the MPU configurations. I understand that after configuring and enabling the MPU, if an access is made to a region without the right permissions a MemManage fault is raised. Is there a handler for the MemManage fault? Is there an example code which demonstrates this scenario? Thanks Re: Configuring memory protection unit (MPU) in i.MX RT1040 Hi @rd24  1. About SDK of I.MX RT1040, please download from https://mcuxpresso.nxp.com/en/builder?hw=MIMXRT1040-EVK which supports our nxp.com/i.mxrt EVK board for reference. 2. About MPU configuration, you can refer anyone of examples (e.g, helloworld) in source/xx.c reference code like below, `BOARD_ConfigMPU` function is for configration when doing init board hardware. int main(void) { char ch; /* Init board hardware. */ BOARD_ConfigMPU(); BOARD_InitBootPins(); BOARD_InitBootClocks(); BOARD_InitDebugConsole(); /* Just enable the trace clock, leave coresight initialization to IDE debugger */ SystemCoreClockUpdate(); CLOCK_EnableClock(kCLOCK_Trace); PRINTF("hello world\r\n");

ioctl_cmds.h The document iMX8MP_CAMERA_DISPLAY_GUIDE.pdf mentions: Interface header file: mediacontrol/include_api/ioctl_cmds.h This header file is referenced by a number of Vivante header files but doesn't get built into the Yocto SDK (I am currently using Scarthgap with the Toradex 7.0.0 BSP). Sometimes this file is built in the /build/tmp/work directory but not with Toradex BSPs. I have to go find this file in a build from a different BSP and add it directly to my Qt project when I update Yocto. Is it possible to force this file to be created and added to the SDK? Thanks i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Multimedia Yocto Project 回复：ioctl_cmds.h 谢谢你！这有效。 回复：ioctl_cmds.h 该文件内置于isp-imx SDK中，您可以构建独立的isp-imx包，步骤如下： $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/isp-imx-xxx.bin $ chmod +x isp-imx-xxx.bin $ ./isp-imx-xxx.bin $ cd isp-imx-xxx $ ./build-all-isp.sh 发布部分

imx93evk rebuild kernel image and replace ! This is the command i build for the imx93evk $ mkdir imx-yocto-bsp $ cd imx-yocto-bsp $ repo init -u https://github.com/nxp-imx/imx-manifest -b imx-linux-scarthgap -m imx-6.6.36-2.1.0.xml $ repo sync $ mkdir -p downloads $ cd downloads $ mkdir linux-imx; cd linux-imx $ git clone https://github.com/nxp-imx/linux-imx.git $ cd ../.. $ export BSPDIR=$(pwd) $ DISTRO=fsl-imx-wayland MACHINE=imx93-11x11-lpddr4x-evk source imx-setup-release.sh -b buildwayland $ bitbake imx-image-multimedia after building finish, the directory imx-yocto-bsp/buildwayland/tmp/sysroots-components/imx93_11x11_lpddr4x_evk/imx-boot/boot will contain imx-boot-imx93-11x11-lpddr4x-evk-sd.bin-flash_singleboot ! is using $ sudo ./uuu -b emmc_all imx-boot-imx93-11x11-lpddr4x-evk-sd.bin-flash_singleboot ! a correct way to update the image that reflect the kernel changes i made in the linux-imx? ! what is the recommended way to only build the linux kernel and replace the kernel only, is it $ cd linux-imx $ make imx93_11x11_evk_defconfig $ make ! and which image should i burn specifically for replacing the kernel? BR, Colin         Re: imx93evk rebuild kernel image and replace When you finish rebuild you can use the scp commend to copy the kernel images to your board Re: imx93evk rebuild kernel image and replace Yes, could you provide the steps that we can follow? Re: imx93evk rebuild kernel image and replace Here do you just need to rebuilt and update the kernel on the board?

IMX93EVK no uart log Bought imx93evk, power it up and connect the USB DBG to my pc and open up the tty to check the log with 115200, but failed to see any log, after flashing with sudo ./uuu LF_v6.6.52-2.2.0_images_IMX93EVK.zip, still can not see usrt log, what do i miss? Re: IMX93EVK no uart log i found out there are actually multiple port being open and i was only targeting the first, which ends up no output, thanks Re: IMX93EVK no uart log HI lykaios1203 The i.MX 93 Applications Processor has six independent UART ports (UART1 – UART6). On the MCIMX93-EVK board, UART1 is used for Cortex-A55 core, and UART2 is used for Cortex-M33 core. A single chip USB to dual UART, JTAG, and I2C is used for UART debug and remote debug. The part number is FT4232H. The developers can download the driver from FTDIwebsite. After the driver for FT4232H is installed, the PC will enumerate four COM ports when the USB cable is plugged into the J1401 connector, the third port is used for A55 and fourth for M33 system debugging.  Regards Daniel Re: IMX93EVK no uart log pin attached

[i.MX6] 我如何知道 CK 和 ADDR/CMD 之间的 i.MX6 输出时序？ 大家好， 我如何知道 CK 和 ADDR/CMD 之间的 i.MX6 输出时序？ 对于 DQ 或 DQS，我发现了有关读取校准或写入校准的信息，但我看不到有关 CK 和 ADDR/CMD 的信息。 我需要这些参数来进行 SI 模拟。 在此先感谢您的帮助！ 回复：[i.MX6] 我如何知道 CK 和 ADDR/CMD 之间的 i.MX6 输出时序？ 好的，我会检查一下。很抱歉错过了 回复：[i.MX6] 我如何知道 CK 和 ADDR/CMD 之间的 i.MX6 输出时序？ 如果使用 LPDDR2，CA-Bus 延迟显示在寄存器 WRCADL 中。 对于 DDR3，没有寄存器，因为 JEDEC 没有对其进行培训。 CK到CA的延迟由路由规则控制。您可以在 HDG 中找到它。 回复：[i.MX6] 我如何知道 CK 和 ADDR/CMD 之间的 i.MX6 输出时序？ 您需要做什么 SI 仿真，对于 DDR 部分，我们为其配置了脚本和压力测试工具。 回复：[i.MX6] 我如何知道 CK 和 ADDR/CMD 之间的 i.MX6 输出时序？ 由于此文件补充了我们的问题，请确认。

Calibration features Hello,  I wonder if FreeMaster is capable of being used as a calibration tool. For example, calibrate a thermistor with a NXP board.  Another question on top of this: is it possible to apply a function to a raw signal before it is displayed on a graph in FreeMaster? Thanks  Re: Calibration features Hi @Vast-Horizon, Yes, you can use FreeMASTER as calibration tool. Here's an example of how it could be used in such scenario: Implement the algorithm in the embedded application Store algorithm parameters in global volatile variables Use FreeMASTER to read algorithm parameters at runtime Use FreeMASTER to update parameter values to fine tune the algorithm You can also apply transformation functions on the variables before those are displayed. This option is available in the Variable menu (Project -> Variables -> Edit): Note: transformations are applicable only to REAL values (top right option) Hope it helps, Iulian

PP4/PW4 pin Hello newbie here, I'm looking at a mc9s12gc (52 pin) on HVAC board and noticed that a Thermostat(Basically a potentiometer) what I would think should be tied to an input pin is wired to the PP4/PW4 pin. Can the PW4 pin be configured as an input? Everything I've read says it is a Pulse width modulated waveform output. I know most thermostats are just open/closed contacts but this one is not. Thanks Re: PP4/PW4 pin Hi @P0zburn, This is not an ATD (ADC) pin, it can be a digital input only. Best regards, Daniel Re: PP4/PW4 pin Thanks for the response.  I have a follow up question. Once it is configured as an input, can it be used as a analog input? Re: PP4/PW4 pin Hello @P0zburn, The PP4/PW4 pin is a GPIO. The direction is configurable in the DDRP register.

MC9S12C64MFA IOC4 question Hi All, MC9S12C64, Code Warrior 5.9.0, coding in assembler. I've been wrestling with a problem I am having getting the input capture function to work for well over a week now with no success. It's time to swallow my pride and beg for help. I have all the other timer functions working well, but the IC has me stumped, both IOC4 and IOC5. I put together an absolute minimum test code (attached). If anyone can offer suggestions I'd really appreciate it. Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Daniel, Update. After trying just about every combination of everything I could think of I finally got the test program to work. I think the key issue was the way I was clearing the flags. As for the IRQ, I didn't notice that the pullups for Port E are set after reset. I used an external pullup in my other program so that kind of messed me up. I've attached my latest test program. Now I have to see if I can get them to work in my main program, but at least I have this working for an example.  Thanks so much for all your help. I doubt that I could have solved this without it. Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Daniel, Thanks for the clarification on IRQ and XIRQ. I think I understand it now. I have experimented with use of the pullup but I still can't get it, or IOC4 or IOC5 to trigger their respective ISRs. PARTIDH is $31, PARTIDL is $03. What does that tell you? Regards, Robert  Re: MC9S12C64MFA IOC4 question Hi Robert, I believe this is well explained here: https://www.nxp.com/docs/en/data-sheet/MC9S12C128V1.pdf Can you double-check the part ID in the PARTIDH and PARTIDL registers? Thank you Re: MC9S12C64MFA IOC4 question Hi Daniel, Thanks for that link. I studied it and think I have made the correct changes to my program (attached). Unfortunately I still can't get either IOC channel or IRQ to trigger their respective ISRs. I'm still not quite clear on the IRQ channels. It is my understanding that IRQ (PE1) is set to falling edge capture only if IRQCR, IRQE is set to 1. To enable PE1 does IRQCR, IRQEN have to be set to 1 as well? I tried that and still didn't get it to work. Is PE0 a separate IRQ channel and if so what triggers it, Falling edge, Rising edge or Hi or Lo level? The manual doesn't give me much information on this, or at least I can't find it if it does. Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Robert, There is one issue in the code I overlooked. It is the BSET instruction used to clear the flags. BSET does read-modify-write operation at the register, which clears every flag that is set in the register. It is explained here: https://www.nxp.com/docs/en/application-note/AN2554.pdf Can you test it? Thank you, Daniel Re: MC9S12C64MFA IOC4 question Hi Daniel, I tried running another larger program I am working on that uses IOC5. It gets a pulsed 5 volt signal to the main board where it is inverted. IOC5 has a pullup and the pulse pulls IOC5 low. I have confirmed this with a scope. With this signal I can also use jumpers to test IOC4 , PE0 (XIRQ) and PE1 (IRQ). I have confirmed continuity of the input pins on the board to the pins on the processor. Even though I have a good signal at the board I'm not able to read it in the ports on the debugger, stopped or running. PTT and PTIT read the same, %11100000. This makes sense because pins 7 and 6 are initialized high and not changed in the program. Pin 5 has a pullup.  A change in IOC4 or IOC5 is not indicated with a pulsed input. When I read PORT E, it is always %00001111. So PE0 and PE1 are always high, no matter what the signal to the board pin is. This indicates to me that there could be an internal problem in the processor, but it seems odd that it should affect these four pins. All the other timer functions work fine, as well as the ITR and ADC channels. Is there any other way I can confirm if these pins are damaged or not? Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Daniel, I'm not fluent in "C" but I believe the MC9S12C64 IRQ is on Port E1 and XIRQ is on Port E0, not Port B, as your attachment indicates. I didn't bring out PE0 on my board so I am just trying to get the IRQ pin working. I wrote a new test program to test the IRQ, IOC4 and IOC5 (attached). It is about as brief as I could make it. I have the ITR toggle PTM5 every 100mS. I use this as a trigger to test the input capture ISRs. I have checked the signal at the ISR inputs with a scope and it is a nice clean 5 volt square wave. When I read PTIT is just shows pins 7 and 6 high which is legitimate as they are commanded high in the timer set up. At no point do they indicate high for IOC4 or IOC5. When I put a break point in any of the ISRs the program doesn't get there which indicates to me that the ISRs have not been triggered. Can you offer any suggestions as to what I am doing wrong? Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Robert, I'm sorry, it is PTIT. IRQ/XIRQ example attached Re: MC9S12C64MFA IOC4 question Hi Daniel, I'm a bit confused about the PWM and TIM functions and which pins they are assigned to. Should I be checking the PTIP register, the PTIT register or both. At this point it looks like IOC4 is not generating an interrupt but it definitely has a 5 volt square wave signal to the IOC4 pin. I discovered this by placing a break point in the ISR with the debugger, but the program never got there. On another matter, I could use the IRQ, or XIRQ pin to monitor my external signal but I'm not clear on how to set it up. Could you advise me on this please? Regards, Robert Robert Re: MC9S12C64MFA IOC4 question Hi Daniel, The fact that my set up looks good is very encouraging. You've made some very good troubleshooting suggestions and I give them all a try. Thanks again. Regards, Robert Re: MC9S12C64MFA IOC4 question Hi @roberthiebert, I have gone through the project but I haven't spotted anything wrong in the configuration. Can you double check all the registers in the debugger's register view? And instead of just checking the PTM4, read the interrupt flag of the TIM_4 channel. Also, The PTIP register will give you the state of the pin in any mode. Re: MC9S12C64MFA IOC4 question That doesn't appear to be the problem. I tried applying a 5 volt 100mS square wave to PT4 and PTM4 is still not toggling. Have I got my set up correct? Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Daniel, Thanks so much for your prompt response. What you say makes sense to me. I'll modify my board and let you know the results. Regards, Robert Re: MC9S12C64MFA IOC4 question Hi Robert, Can you please first make sure there is an edge at the pin? Removing the 5V from the pin does not mean there is 0V. Regards, Daniel

SRAM and SDRAM can interface together with imxrt1062 in one design Hello  I'm designing a new product using the IMXRT1062 controller. I've already interfaced with SRAM and verified that it's working. I'm now planning to interface with SDRAM as well, so that I can access both SRAM and SDRAM as needed. Is it possible to interface with both SRAM and SDRAM using the IMXRT1062? i.MXRT 106x Re: SRAM and SDRAM can interface together with imxrt1062 in one design Hi @VishalAvg , Thanks for your interest in NXP MIMXRT series! Yes, this can be done with SEMC. The SEMC is a multi-standard memory controller optimized for both high-performance and low pin-count. It can support multiple external memories in the same application with shared address and data pins. The interfaces supported include SDRAM, NOR Flash, SRAM, NAND Flash, and 8080 display interface. Best regards, Gavin