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How to Configure Clock for 24 bit 48 Khz I2s transfer in lpc55s69-evk

As per the calculation the BCLK frequency  required is 2304000Hz. I seem to be getting the FXCOMCLK7 clkin(23.04Mhz) as a multiple of BCLK required. But MCLK also has to be multiple of BCLK. But MCLK seem to be not using the fractional clock divider output. Please share some inputs to configure the clock correctly

Re: How to Configure Clock for 24 bit 48 Khz I2s transfer in lpc55s69-evkThe noise sound issue is resolved after updating the Dma input buffer to the I2S. I was using same address as DMA source address. Updated it to a ring buffer as in SDK example to resolve the issue. ThanksRe: How to Configure Clock for 24 bit 48 Khz I2s transfer in lpc55s69-evk

2 channels. I think I am able to generate the clocks properly. MCLK is 46.08 Mhz, Bclk is 2.304 Mhz(Verified with DSO). Audio is playing with small noise in the output sound. Could you share some inputs to debug. Do we need to update any setting for the codec when we update the the sampling rate to 48 khz in 24 bit mode. I have used sdk example lpcxpresso55s69_dev_audio_speaker_freertos as reference

Re: How to Configure Clock for 24 bit 48 Khz I2s transfer in lpc55s69-evk

Hello @dawnpaul100 

Please tell me how many channels does your I2S have?

BR

Alice