S32K322 FLEXCAN THROUGH DMA ERFCR[ERFEN] this register is not precent in S32K322 controller. an one more thing and can anyone give me step by step example code for can through dma. Re: S32K322 FLEXCAN THROUGH DMA Hi@vignesh3 Create a new topic for your new question, this original topic is closed. Re: S32K322 FLEXCAN THROUGH DMA Hi @Senlent , So can I use message buffers for receiving and transmitting through DMA instead of using legacy RX FIFO. an Is the message buffer address is present in the SRAM area because I have studied that we can use non configured message buffers as SRAM in the application notes ? Re: S32K322 FLEXCAN THROUGH DMA If message buffer is received a CAN message will it request DMA channel or Is it only legacy fifo is requesting the DMA ? Re: S32K322 FLEXCAN THROUGH DMA How can I know that if peripherals are requesting to the DMA channel or not ? Re: S32K322 FLEXCAN THROUGH DMA Hi@vignesh3 The message buffers and mail boxes you mentioned should be the same concept. 1. When sending, you must use MB. 2. Receiving can be MB or FIFO. 3. Legacy FIFO and Enhanced FIFO cannot be enabled at the same time. The difference is that Enhanced FIFO can be used for CAN FD, while Legacy FIFO cannot support CAN FD. Re: S32K322 FLEXCAN THROUGH DMA I have one more doubt also, can you tell me when to use Message buffers , Mail boxes and RXFIO(legacy fifo and enhanced fifo)? Re: S32K322 FLEXCAN THROUGH DMA Hi@vignesh3 This part is described in detail in the data sheet. S32K3xx Reference Manual, Rev. 9, 07/2024: Senlent_0-1742346595631.png Re: S32K322 FLEXCAN THROUGH DMA we are receiving all the CAN messages in this Flexcan_Ip_StateType FlexCAN_BOARD_InitPeripherals_State0; global variable. the message buffers are implemented in this structure. can anyone tell me how RAM space is assigned as CAN message buffers. Re: S32K322 FLEXCAN THROUGH DMA Hi@vignesh3 As you can see that the FlexCAN 0 of S32K322 do supports Enhanced Fido S32K3xx Referernce Manual, Rev9.9/07/2024, the Table 488. Senlent_0-1742283835733.png For FlexCAN with DMA used , you may refer to this post by Petr, https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K344-FlexCAN-Ip-TX-RX-EnhanceRXFIFO-DMA-test-S32DS3-5/ta-p/2015832 Re: S32K322 FLEXCAN THROUGH DMA vigneshv1_0-1762166837382.png Hi @Senlent , According to above picture it looks like RxFIFO and mailbox are same is it correct?

S32K144 PORT Hi:     I want to configure the PORTB pins of S32K144 in EB project, but I find that some of the PCR values of the pins are wrong after configuration, such as PORTB0-14, is there anything special about these pins? My MCU package is LQFP_100, thank you for your help! Snipaste_2024-06-16_21-38-28.png 回复： S32K144 PORT Hi @Embedded_novice  Section 3.6 (Driver usage and configuration tips) of the User Manual for S32K1_S32M24X PORT Driver provides a formula to obtain the PortPinPcr value. For easy reference, I am adding it to my response, but you can find the document for example C:\NXP\SW32K1_S32M24x_RTD_4.4_R21-11_2.0.0\eclipse\plugins\Port_TS_T40D2M20I0R0\doc. The value of actual PortPin Pcr is identified by the formula: PortPinPcr = PinId + PortId∗32. Where PortId is the numeric identifier of the port. VaneB_0-1718645352478.png For example, the PortPinPcr value of PTC7 will be 7 + (2∗32) = 71. B.R. VaneB 回复： S32K144 PORT I see. It's my understanding. I think PORTA has 18 pins, so the PCR of PORTB_0 should be 19, but in fact, the PCR value is calculated according to the maximum 32 per PORT group, PORTA occupies 0-32, PORTB_0 should start from 33. However, when I checked the section on the number of PORT pins in the RM manual, there seemed to be no clear mark indicating that I should calculate according to the absence of 32 pins in the PORT group. Could you tell me where in the manual to get this information?

Where can I find MCX comparator SAMPLE/WINDOW input Hi NXP, I am currently trying to use the comparator module in the MCX series. However, I have noticed that the documentation does not provide detailed instructions on how to configure the SAMPLE/WINDOW signal. Although the manual (MCXN 44.3.1, MCXA 41.3.1) note mentions "See the chip configuration section for the source of SAMPLE/WINDOW input." I have not been able to find the relevant description. https://www.nxp.com/webapp/Download?colCode=MCXNX4XRM&location=null https://www.nxp.com/webapp/Download?colCode=MCXAP64M96FS3RM&location=null Could you please assist me in confirming how to proceed with the configuration? If possible, I would greatly appreciate it if you could provide me with some examples. Thank you very much! Analog(ADC|CMP|DAC|OpAmps) MCXA MCXN Re: Where can I find MCX comparator SAMPLE/WINDOW input Hi @Harry_Zhang: Thank you very much! Re: Where can I find MCX comparator SAMPLE/WINDOW input Hi @onejoeluo  About "See the chip configuration section for the source of SAMPLE/WINDOW input." Please check the MCX Nx4x Reference Manual 26  chapter Input Multiplexing (INPUTMUX). HangZhang_0-1718764139136.png Hope this will help you. BR Hang

imx8qm lpddr4 android bsp Hi! I'm trying to flash a board from phytec with imx8qm on board. I've downloaded Android 14 from the nxp page. I tried to run uuu_imx_android_flash.sh script but it keeps failing with error: [HID(W): LIBUSB_ERROR_TIMEOUT (-7) ] SDPS: boot -f imx-boot-imx8qmmek-sd.bin-flash The command was: sudo ./uuu_imx_android_flash.sh -f imx8qm As I understood the error is related to LPDDR4 and DDR4. The board has LPDDR4 and my question is the android build or uboot from the build don't support LPDDR4? Also, tried to flash linux and got the same error.    Re: imx8qm lpddr4 android bsp Hi, Thank you for your answer! Re: imx8qm lpddr4 android bsp Hi, Thank you for your interest in NXP Semiconductor products, The problem is the imx-boot image, there must be differences other than the LPDDR4 because 8QM-MEK has a LPDDR4 memory. The differences in RAM configuration, channels of PMIC, memories, etc. cause failures probing, then failure booting an image specially with this SoC since the resources are managed by SCFW. You have to use PHYTEC release of Android since it requires a lot of partitions and are checksum-ed, with Linux you could adapt working with our RootFS integrating PHYTEC imx-boot, device tree and probably Kernel image, the other option is to use PHYTEC Linux release too. Regards

I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 你好 我将 SDRAM（CS0）和 SRAM（CSX1）连接到 RT1170 的 SEMC。 我发现 CS0 有时为低脉冲而 CSX1 为低，这意味着当 SEMC 正在访问 SRAM 时，SEMC 对 SDRAM 进行了中断访问。 访问 SRAM 时是否可以阻止 SDRAM 访问？ 回复：I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 是的，如果需要执行刷新，自动刷新仍然会中断 burts 操作。它只是分割突发，以便可以在其间插入自动刷新。 此致， 奥马尔 回复：I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 是的，因为自动刷新是定期执行的。不幸的是，我们没有这个具体实现的例子。 此致， 奥马尔 回复：I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 SEMC 在发送 AUTO REFRESH 命令之前发送 PRECHARGE ALL 命令来关闭设备上任何打开的页面。因此，如果自动刷新被禁用，则这两个命令都不会被执行。这在 SDRAMCR3[REN] 字段上被禁用。 请注意，如果刷新没有按照 sdram 时序进行，则可能会导致 sdram 上的某些数据丢失。 此致， 奥马尔 回复：I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 SDRAM 的哪个特定命令会中断 SRAM 访问？ 将 BMCR 设置为 0x81 的目的是避免重新排序命令队列，以便命令按照“先进先出”策略执行。 建议 UT 和 RT 保持不变，将它们更改为内存可能的最高刷新周期可能会减少 SDRAM 的中断，因为我怀疑中断是自动刷新命令。 此致， 奥马尔 回复：I.MX R1170 SEMC SDRAM 在 SRAM 访问期间中断 我认为SDRAM的中断是由于自动刷新命令造成的，因此调整SDRAM刷新的时间对于防止这种情况至关重要。 另外，在 BMRC 寄存器上实施不同的设置可能会有所帮助，我建议设置 0x81 以防止重新排序命令。 此致， 奥马尔

Stresstest fails at 3 frequencypoints but passes with 1 frequencypoint, LPDDR4 Hello everyone, I had asked a similar question when i used the mScale DDR Test Tool and that error was resolved when switched to ConfigTool V15. I am currently working on a board bring-up with the following combination of SOC, RAM and Software for the RAM-Stresstest: - i.MX 8M Plus (1600 MHz) + Micron LPDDR4 4GB (MT53D1024M32D4DS) - iMX Config Tool v24.12 I have used the NXP RPA Excel sheet for generating the according ".ds"-file for the Stresstest program. Also using the standard parameters in the "DDR Configuration Sheet" results in the same error.  The question is as following: Why does the Stresstest run smoothly and without errors, even under temperature fluctuations, when chosing 2000 MHz as the single frequency for the test, but fails when i chose the same parameterset, but now with three frequency points enabled. In that case the default, additional 200 MHz and 50 MHz, are tested as well.  Any help is hugely appreciated Greetings Niko i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Re: Stresstest fails at 3 frequencypoints but passes with 1 frequencypoint, LPDDR4 Hello, If selecting a frequency range to test, ensure that the start frequency test is within ±50MHz of the frequency that the DDR initialization script is tuned for and make sure end frequency is no less than start frequency and within 100Mhz of the start frequency. Best regards. Re: Stresstest fails at 3 frequencypoints but passes with 1 frequencypoint, LPDDR4 I have already extensively tested the ODT, PDDS, Vref etc. For our highest target frequency i can get the stresstest running succesfully, without errors, when its the only tested frequency -> i assume our layout is good, because the most critical operating point works. Also in the first test run when 200 and 50 MHz are enabled. Only from the second run errors arrise in the highest frequency operating point as well -> i assume some the firmware or the Config Tool dont work as expected: So you´d test the 2000 MHz/200 MHz and 50 MHz seperately and then just enable the 3 frequencies in the RPA sheet?  Re: Stresstest fails at 3 frequencypoints but passes with 1 frequencypoint, LPDDR4 Hello, It is suggested to run the stress test at the target operating frequency for an extended period of time to verify the DDR performance on the target board. Running the stress test higher/lower than the target operating frequency is not meaningful. The signal waveform may change a lot as the frequency increases/decreases. Therefore, passing the stress test at a frequency higher/lower than the target operating frequency does not necessarily mean that there is more timing margin. To pass the stress test you may need to change: ODTImpedance Desired ODT impedance in Ohm. Valid values for DDR4=240,120,80,60,40. Valid values for LPDDR4=240,120,80,60,40 TxImpedance Write Driver Impedance for DQ/DQS in ohm (Valid values for all DDR type= 240, 120, 80, 60, 48, 40, 34) ATxImpedance Write Driver Impedance for Address/Command (AC) bus in ohm (Valid values for all DDR type = 120, 60, 40, 30, 24, 20) Best regards.

S32G3 Linux BSP 35 で ttyLF1 を有効にする方法 こんにちは、NXPチームの皆様、 S32G399ardb3を参照し、カスタムボードを設計し、Linux BSP 35を使用しました。 当社の S32G3 カスタマイズボードはPCから UARTデータを受信できません が、PCはS32G3からUARTデータを受信できます PINMUX FUNC Xがデバイスツリーでどのような機能を表しているかをどうやって知ることができますか? UART2を有効にした場合、 PINMUX FUNC Xはどのように設定すればよいですか? 以下はデバイスツリーです(BSP 43に従って変更します) uart1_pins: uart1_pins { uart1_pins_grp0 { pinmux = FUNC2)>; // PC_08 output-enable; slew-rate = ; }; uart1_pins_grp1 { pinmux = FUNC0)>; // PC_04 input-enable; slew-rate = ; }; uart1_pins_grp2 { pinmux = FUNC2)>; }; }; &uart1 { pinctrl-0 = <&uart1_pins>; pinctrl-names = "default"; status = "okay"; }; S32G3のコマンドを使用してデータを送信します echo "Test" > /dev/ttyLF1 私のPCは、受信したデータにコマンドを使用できます cat /dev/ttyUSB1 ありがとうございます 回复: S32G3 Linux BSP 35 で ttyLF1 を有効にする方法 こんにちは、NXPチームの皆様、 現在正常に動作しています。 しかし、stty コマンドを使用せずにボーレートを設定するにはどうすればよいですか? ノート: ttyLF1 はシリアルコンソールではなく内部 UART です 回复: S32G3 Linux BSP 35 で ttyLF1 を有効にする方法 こんにちは、NXPチームの皆様、 私は これらの問題をS32G3_IOMUX 2で見つけました。xlsx ファイル PC_04 PINMUX関数「LINデータ受信」SSSは0000_0100なので、FUNC4である必要があります uart1_pins_grp2 { pinmux = FUNC4)>; }; ありがとうございます

S32K3 RTD 5.0.0 - LPUART - 当指示“结束传输”时区分 TX 和 RX？ 我正在为 S32K344 处理器编写一些板支持软件，与 S32K3 RTD 5.0.0 配合使用，特别是使用 Lpuart_Uart_Ip 进行全双工异步（中断驱动）发送和接收操作。 问题：当接收到带有事件 LPUART_UART_IP_EVENT_END_TRANSFER 的回调时，似乎没有直接的方法来区分该回调是与未完成的 TX 还是未完成的 RX 操作相关联。（此事件由两者共同产生。） 检查 Lpuart_Uart_Ip.c 后实施时，我已确定了一种在我的用例中消除歧义的有点复杂的方法。具体来说： 我会跟踪我是否期待即将发生的 RX‘结束传输’事件。我预计在以下情况下 RX‘结束传输’事件即将发生： 1) 我收到了LPUART_UART_IP_EVENT_RX_FULL事件的回调，并且 2) 我没有在该回调中将接收缓冲区重置为非零大小，例如通过 Lpuart_Uart_Ip_SetRxBuffer()。 3) 我尚未收到指示“结束传输”事件的预期回调。 当我预期即将发生 RX“结束传输”事件时，我假设回调是针对未完成的 RX 操作。 当我在其他条件下收到“结束传输”回调时，我假设该回调是针对未完成的 TX 操作。 也许我遗漏了一些东西——有没有更好的方法来消除歧义？其他 RTD 实现有单独的 RX 和 TX 回调，但这里的情况并非如此。我的建议是为 RX 和 TX 设置单独的“结束传输”事件类型枚举值，但我意识到对 API 的这种更改不会向后兼容，并且可能无法在下一个主要 RTD 版本之前实施（例如6.0.0)

S32G3 Linux BSP 38.0 linuxptp パッケージの問題 こんにちは、コミュニティ。 S32G-VNP-RDB3 ボードを使用し、Linux BSP 38.0 を構築して PFE と PTP を開発しています。 ユーザーマニュアルによると、linuxptpツール(ethtool、ptp4lなど)がデフォルトでインストールされています。ただし、Linux BSPで ethtool または ptp4l コマンドを実行すると、コマンドが見つかりませんが出力されます。 ユーザーマニュアルに従ってYOCTOを使用してBSPを構築しましたが、linuxptpのために何か特別なことが必要ですか? Re:S32G3 Linux BSP 38.0 linuxptpパッケージの問題 ありがとう、それはとても役に立ちました。 Re:S32G3 Linux BSP 38.0 linuxptpパッケージの問題 ご回答ありがとうございます。 「base」ではなく「fsl-image-auto」で再ビルドすると、PTP機能が有効になっています。 ありがとうございます。 ああ、それからもう一つ、SDカードにビルド済みのtgzファイルを設定する方法と、このビルド済みのtgzファイルにSJA1110スイッチファームウェアが含まれているか教えていただけますか?

FreeMaster using PE micro debugger As mentioned FreeMASTER support real-time debug monitor and data visualization tool that enables runtime configuration and tuning of embedded software applications. I tried to connect NXP microcontroller and FreeMaster through PE micro multi universal debugger for monitoring the variable at run time. But i cant make it proper.  Is is possible  to use FreeMASTER using PE micro multi universal debugger for monitoring data?   Re: FreeMaster using PE micro debugger Hi @MichalH  Thanks you for you quick Response. My issues is solved. Regards, Stark_ Re: FreeMaster using PE micro debugger OK, so the connection problem is resolved. For general use of FreeMASTER, please refer to User Guide.  In short: you have used the ELF file to load symbols; now you need to create so called FreeMASTER Variables, where you select a symbol/address, size, reading period, format, etc. to be displayed in FreeMASTER. Once you have the FreeMASTER variables defined, you can observe them in a grid or in graphs. Please close this thread as the initial issue has been resolved.  If you have any questions on general FreeMASTER usage after reading the User Guide, please start a new thread on this forum. Regards, Michal Re: FreeMaster using PE micro debugger Hi @MichalH  Connection are done when i start the communication popup show for for load the executable file, I also load the .elf file which is created in my project. but how to import the variable that are used in my project? Regards, Stark_ Re: FreeMaster using PE micro debugger There are two important points: The S32 Design Studio (debugger) must be disconnected from the target when attaching FreeMASTER. The P&E probes cannot handle simultaneous connection from two client applications. The FreeMASTER plug-in shall know what MCU part number you are using.  Go to Project/Options, open the configuration dialog and select the MCU type like in the picture below: MichalH_1-1743674891142.png Regards, Michal Re: FreeMaster using PE micro debugger Hi @MichalH  once I flash my microcontroller after that i just connect with FreeMASTER. but it show an error MCU is used is S32K3 series P&E micro Multilink universal FX IDE used S32 Design studio Regards, Stark_ Re: FreeMaster using PE micro debugger The error you show now in the screenshot is reported by the P&E Micro debugging function already - it seems the P&E probe cannot connect to the target MCU. What is your target MCU?  What is the type of P&E probe? Can you use a CodeWarrior or other debugger with the P&E probe? Thanks, Michal Re: FreeMaster using PE micro debugger Hi @MichalH  Thanks for the quick response. As you said " Project/Options - the drop-down list of Plug-in modules will probably be empty in your case " was correct and followed the step you mention, after that can able to see the plugin in FreeMASTER. when i try to run with the mention setting (i.e, FreeMaster P&Emicro communication plugin (Cortex-M, power pc, HCS08/12, Cold fire) ). but again got an error message. Is is possible to use FreeMASTER with P&Emicro debugger? for that any lib should be added in project file ? Re: FreeMaster using PE micro debugger Hello, from your screenshot it seems like a problem in FreeMASTER installation. The communication plug-ins are probably not installed properly. You can confirm this by going to Project/Options - the drop-down list of Plug-in modules will probably be empty in your case: MichalH_0-1743668612039.png How to fix the installation: Close FreeMASTER Open file explorer in "c:\NXP\FreeMASTER 3.2\FreeMASTER" directory Locate the "register.bat" file Right-click the file and select "Run as administrator" Start FreeMASTER, the plug-ins shall now be visible in Project/Options dialog. Regards, Michal

PEマイクロデバッガを使用したFreeMaster 前述のように、FreeMASTERは、組み込みソフトウェアアプリケーションのランタイム構成とチューニングを可能にするリアルタイムデバッグモニターとデータ視覚化ツールをサポートしています。 実行時に変数を監視するために、NXPマイクロコントローラーとFreeMasterをPEマイクロマルチユニバーサルデバッガーを介して接続しようとしました。しかし、私はそれを適切にすることはできません。 PE micro multi universal debuggerを使用してFreeMASTERをデータ監視に利用することは可能ですか?   Re:PEマイクロデバッガを使用したFreeMaster OK、接続の問題が解決しました。 FreeMASTERの一般的な使用方法については、ユーザーガイドを参照してください。要するに、ELFファイルを使用してシンボルをロードしました。次に、FreeMASTERに表示するシンボル/アドレス、サイズ、読み取り期間、形式などを選択する、いわゆるFreeMASTER変数を作成する必要があります。FreeMASTER変数を定義したら、グリッドまたはグラフでそれらを観察できます。 最初の問題が解決されたため、このスレッドを閉じてください。ユーザーガイドを読んだ後、一般的なFreeMASTERの使用について質問がある場合は、このフォーラムで新しいスレッドを開始してください。 よろしく ミハル Re:PEマイクロデバッガを使用したFreeMaster スクリーンショットに示しているエラーは、P&E Microのデバッグ機能によってすでに報告されています - P&EプローブがターゲットMCUに接続できないようです。 ターゲットとするMCUは何ですか? P&Eプローブの種類は何ですか? CodeWarriorまたはその他のデバッガをP&Eプローブと一緒に使用できますか? 感謝 ミハル

S32G3 GMAC and PFE pin assignment Hello, I am using S32DS pin tools to configure GMAC0, PFE0/1/2 interfaces. However, I am encountering numerous pin conflicts between GMAC0 and PFE1, as well as between PFE0 and PFE2. According to the "S32G-VNP-RDB3 Ethernet Enablement Guide," it seems that all four interfaces are able to be configured simultaneously, and supports multiple combinations. The dts/dtsi patch files do not provide sufficient information regarding the pin assignments when attempting to use all four interfaces together. My questions are as follows: Can all four interfaces (GMAC0, PFE0, PFE1, and PFE2) be used together? If so, are there any restrictions? If it is possible to use all four interfaces simultaneously, can you provide an example of the correct pin assignment? I am struggling to find enough available pins for all of them using S32DS. Thank you for your assistance. XD  Re: S32G3 GMAC and PFE pin assignment Hello, @XD  Thanks for the update. Yes, the PFE0 and PFE2 could be used simultaneously. Because on RDB3 with the BSP, the PFE0 is working on SGMII mode by default, the pins you listed are not actually used by PFE0, but by PFE2, so that no pin conflicts existed from my understanding. Best Regards Chenyin Re: S32G3 GMAC and PFE pin assignment Hi Chenyin, I appreciate your support, and the files you provided are very helpful. According to the S32g.dtsi file, I noticed that PFE0 and PFE2 are using almost the same pin groups. Below are the PFE0/2 TX pin groups I found: pfe0_pins: pfe0 { pfe0_grp0 { pinmux = , , , , ; output-enable; slew-rate = ; }; pfe2_pins: pfe2 { pfe2_grp0 { pinmux = , , , , ; output-enable; slew-rate = ; }; Given this overlap, could you please clarify how we can use PFE0 and PFE2 simultaneously? Thank you for your assistance. XD Re: S32G3 GMAC and PFE pin assignment Hello, @XD  It is my pleasure to support. You may reference the dts file in TF-A’s source code, under fdts/, with the name s32xxx.dts/dtsi Hope it helps Best Regards Chenyin Re: S32G3 GMAC and PFE pin assignment Hi Chenyin, Thank you for your quick response. Regarding item 2, are the files in the kernel source code? Could you please point me to the DTS file name or the folder name of TF-A? Thanks, XD Re: S32G3 GMAC and PFE pin assignment Hello, @XD  Thanks for the questions. Yes, all four interfaces (GMAC0, PFE0, PFE1, and PFE2) could be used together; for combinations, you may reference the chapter 53 of S32G3RM for the details of serdes working modes.(Page2756-2757 of S32G3 Reference Manual, Rev 3.1) With the default settings of BSP, for example, BSP41, the four interfaces could be used simultaneously, you may reference the dts files in TF-A for the details. Best Regards Chenyin

S32K311 - Register Can not Access Hi all, I recently switched from the S32K312 to the S32K311 Unified Bootloader, but I am encountering an issue where some of the driver registers are no longer accessible. Specifically, I am using CAN communication, and certain registers (SFRs) seem to be unreachable. I’ve attached an image to illustrate the issue. Could anyone provide insights into potential causes or solutions for this problem? Any advice on configuration differences between the S32K312 and S32K311 that could be affecting register (SFRs) access would be greatly appreciated. Thank you in advance! Best regards. Re: S32K311 - Register Can not Access Hi The S32K3XXRM mentions: The peripherals working on the system clock should be clock-gated used the MC_ME.PRTNx_COFBy_CLKEN configurations. According to Table 260. MC_ME partition peripheral mapping and clock control, please check the value of FlexCAN 0: PRTN1_COFB2_CLKEN[REQ65] If this bit was 0, Please check whether the FlexCAN 0 clock gate is enabled in the S32 Configuration Tool. FlexCAN0 clock gate PRTN1_COFB2_CLKEN[REQ65].png Also, does your program call the Clock_Ip_Init function? Best Regards, Robin ------------------------------------------------------------------------------- Note: - If this post answers your question, please click the "ACCEPT AS SOLUTION" button. Thank you! - We are following threads for 7 weeks after the last post, later replies are ignored Please open a new thread and refer to the closed one, if you have a related question at a later point in time. -------------------------------------------------------------------------------

MPC5746R 用户模式机器检查访问 SIUL2 端口时的异常 下午好 我试图在用户模式下运行应用程序代码，但每次我尝试写入 SIUL2 端口寄存器时都会出现机器检查错误。 该操作系统相对简单，在设置应用程序运行的基本系统后，通过跳转块访问应用程序（我希望）。除了 AIPS 之外，没有任何内存保护块从其默认值更改，目前我已将 AIPS 设置为最大权限（所有内容都可以供所有人使用），但每次我尝试初始化 SIUL2 端口时仍然会收到机器检查异常。我对 DSPI 块或 TPU 块没有任何问题，所以我不认为这是一个一般外围设备问题。 我已附上我希望的操作系统和应用程序的相关部分，很抱歉内容太少，但我不得不努力才能发送这些内容。 附加的两个 OS 文件是相关的启动代码，OS 代码是应用程序初始化时运行的第一个文件。 任何建议或更好的绝对答案都将不胜感激。

BL31 中立即发生运行时异常 我有一块围绕 S32G3 构建的定制板。我正在尝试进入 U-Boot。我可以成功加载到 BL2 并完成整个代码库的执行。一旦进入BL31 ，我就会收到运行时异常@0xff6000424。 在 bl31_main.c 的开头添加断点应用程序将立即崩溃并转到此处。 知道为什么会出现这种情况吗？ 回复：BL31 中立即发生运行时异常 我正在使用 arm-trusted 固件的 bsp40.0-2.5 版本。此外，BL2 在 0xff600000 处加载 BL31，但在 AT-F 代码库中找不到调用该代码的位置。这只是一块我没有在任何地方使用的板的单一定义。

license expiring hi, i can no longer open IDE S32DS 2.2 and in attachment i report the licensed component image. i also report image with license site nxp is it possible to extend the license and restore IDE usage? thanks for your availability Re: license expiring Hi,  your S32DS License has been extended.  license expiring Hi, My S32 Design Studio for ARM v2.2 License has already expired,could you help to extend it?Thanks! Activation Code: 07E0-0E26-5682-F10C Re: license expiring @jiri_kral I found problem same as above, Could you please extend license for me ? Re: license expiring Hi,  license has been extended. Please activate S32DS again with your old code.  Re: license expiring Hi, My S32 Design Studio for ARM v2.2 License has already expired,could you help to extend it?Thanks! Activation Code: 49D6-F07D-1169-98A0 Re: license expiring Hi, My S32 Design Studio for ARM v2.2 License has already expired,could you help to extend it?Thanks! Activation Code: 49D6-F07D-1169-98A0 Re: license expiring Hi, My S32 Design Studio for ARM v2.2 License has already expired,could you help to extend it?Thanks! Activation Code: 49D6-F07D-1169-98A0 Re: license expiring Hello,  could you please gives me a hand to update the following license: S32 Design Studio for S32 Platform 3.5, softwaare activation code: 3928-F883-4215-D1EF Thank you!

マーカーあたりのimxrt ADCサンプリングレート 皆さん、こんにちは i.MX RT1010 プロセッサ リファレンス マニュアルには、ADC には次のものがあると記載されています。 • 最大1MS/sのサンプリングレート • 最大 16 個のシングルエンド外部アナログ入力 チャネルごとに 1MSps と記載されているか (したがって 16 × 1Msps のサンプリングが可能)、それとも ADC 全体で使用できますか (したがって、16 の入力すべてを一度にサンプリングすると ~62 ksps) になりますか。 図 53-2.1924ページのADCブロック図には、複数の入力が接続されたアナログコンパレータが1つだけ示されていますが、後者は正しいと思いますか?

S32DS for Arm 2.2 Terminal Window Hello, We've been working with S32DS for Arm 2.0 on Windows 10 for a few years and are now looking to move to Windows 11 and S32DS for Arm 2.2 In the 2.0 version, there's a rather useful serial terminal feature accessible through Window > Show View > Other > Terminal, but it seems to be absent in the 2.2 version Searching for "terminal" in the menus reveals preference settings for the terminal window, but still no way to enable it Has the terminal window been deprecated? If not, where would one find the new enable option? Thank you for your time! Eclipse IDE Usage and Settings Re: S32DS for Arm 2.2 Terminal Window Hi, Thank you so much for your interest in our products and for using our community. Good observation! S32DS for Arm 2.2 do not have terminal. However you could use third party terminal, there are several free ones on the web. On the other hand, taking advantage of your IDE migration and supposing that you are working with an S32K1, please consider migrating to a newest development environment like S32DS for S32 Platform, which do have terminal, please refer to the following community post: https://community.nxp.com/t5/S32-Design-Studio/S32K1xx-SDK-in-S32DS/td-p/2032492 Hope it helps you. Have a nice day!

Yocto 构建失败（vulkan-validation-layers） 运行 bitbake imx-image-multimedia，全部通过，但 vulkan-validation-layers 一直失败。不确定如何继续。 尝试使用 bitbake vulkan-validation-layers -c clean，但仍然出现同样的错误 错误：任务（/opt/yocto/imx-6.6.52-2.2.0-build/sources/poky/meta/recipes-graphics/vulkan/vulkan-validation-layers_1.3.275.0.bb:do_compile）失败，退出代码为“1” 注意：任务摘要：尝试了 1669 项任务，其中 1668 项无需重新运行，1 项失败。 附加日志文件。 回复：Yocto 构建失败（vulkan-validation-layers） 谢谢。 在配备 16GB 内存的 6 核 12 线程英特尔处理器上运行。 通过将其添加到 local.conf 中，设法使其工作 BB_NUMBER_THREADS = "2" PARALLEL_MAKE = "-j2"

OTP 镜像寄存器图 主题请求提供 PF5020 OTP 镜像寄存器映射图文档 您好， 我们目前正在研究 PF5020 PMIC 与恩智浦控制器之间的通信。在审查 PF5020 数据表期间，我们无法找到有关 OTP 镜像寄存器映射的详细信息，包括与 OTP 配置相关的寄存器地址和引脚级说明。 我们需要的输出电压为 1.1 伏和 1.8 伏和 3.3 伏 请问是否有单独的文件提供这些信息？这对我们在系统中正确解释和配置 OTP 相关设置至关重要。 如果您能提供指导或分享任何相关文件，我们将不胜感激。 提前谢谢！ 希瓦尼 Re: OTP mirror register map 您好， PF5020 数据表第 16.1 节提供了完整的 OTP 镜像寄存器图，包括 -寄存器地址 -配置字段，例如：用于降压输出电压的 OTP_vswx OTP_V LDOX 用于 LDO 输出电压 OTP_SWX_s eq 用于上电排序 OTP_SWX_PDGRP 用于断电分组 OTP_SWXILIM 用于限流设置 OTP_SWXUV_TH 和 OTP_SWXOV_TH 用于 UV/OV 阈值 VDDOTP 引脚决定设备是否从以下位置加载配置： -OTP 熔丝（当 VDDOTP = GND 时） -硬接线默认值（当 VDDOTP = V1P5D 时） TBBEN 引脚启用 “先试后买” (TBB) 模式，允许在承诺进行熔丝编程之前临时配置和测试 OTP 设置。 请记住，客户不允许在生产中使用 OTP 编程。只有恩智浦或授权合作伙伴（数量较少）才能执行此操作。在开发过程中，您可以使用 KITPF502xSKTEVM。 要为 1.1V、1.8V 和 3.3V 电压配置 PF5020，您需要 - 将 OTP_VSWx 或 OTP_VSWND1 设置为 1.1V 和 1.8V 的适当值 - 根据电流要求，将 OTP_VLDO1 或 OTP_VSWND1 设置为 3.3V 这些值可在 OTP 镜像寄存器中可编程，可以在提交之前在 TBB 模式下进行测试。 BRs, Tomas