ERFCR[ERFEN] this register is not precent in S32K322 controller.
an one more thing and can anyone give me step by step example code for can through dma.
Hi@vignesh3
Create a new topic for your new question, this original topic is closed.
So can I use message buffers for receiving and transmitting through DMA instead of using legacy RX FIFO.
an Is the message buffer address is present in the SRAM area because I have studied that we can use non configured message buffers as SRAM in the application notes ?
If message buffer is received a CAN message will it request DMA channel or Is it only legacy fifo is requesting the DMA ?
How can I know that if peripherals are requesting to the DMA channel or not ?
The message buffers and mail boxes you mentioned should be the same concept.
1. When sending, you must use MB.
2. Receiving can be MB or FIFO.
3. Legacy FIFO and Enhanced FIFO cannot be enabled at the same time. The difference is that Enhanced FIFO can be used for CAN FD, while Legacy FIFO cannot support CAN FD.
I have one more doubt also, can you tell me when to use Message buffers , Mail boxes and RXFIO(legacy fifo and enhanced fifo)?
Hi@vignesh3
This part is described in detail in the data sheet.
S32K3xx Reference Manual, Rev. 9, 07/2024:
we are receiving all the CAN messages in this Flexcan_Ip_StateType FlexCAN_BOARD_InitPeripherals_State0; global variable.
the message buffers are implemented in this structure. can anyone tell me how RAM space is assigned as CAN message buffers.
As you can see that the FlexCAN 0 of S32K322 do supports Enhanced Fido
S32K3xx Referernce Manual, Rev9.9/07/2024, the Table 488.
For FlexCAN with DMA used , you may refer to this post by Petr,
Hi @Senlent ,
According to above picture it looks like RxFIFO and mailbox are same is it correct?