Technical Inquiry External Pull--down Design for i.MX8 PCIe RC PERST Background: Currently, PERST# is controlled by a normal GPIO of the i.MX8, and no external pull-up or pull-down resistor has been added. During power-on startup, in the Boot ROM/SPL stage, the GPIO PAD is uninitialized and remains in a high-impedance floating state. In a noisy environment, the pin level toggles, causing abnormal reset of the PCIe endpoint device and preventing the link from being established. We now plan to add external resistors to eliminate floating noise, and have drafted two schemes; we would like to obtain NXP's official opinion. Scheme 1: Connect a pull-up resistor to 3.3V Before the bootloader configures the GPIO, the PAD is in a high-impedance state; PERST# is pulled high continuously, and the reset is released early, so it cannot meet the timing requirement of TPV_PERST in the PCIe CEM specification (PERST# must remain asserted for at least 100 ms after power is stable). Will this cause unreliable power-on? Does NXP approve this scheme? Scheme 2: Connect a pull-down resistor to GND During the boot stage, PERST# remains low, which can meet the power-on reset timing requirement. However, the concern is that during normal system operation, the pull-down resistor in combination with external noise may unexpectedly pull PERST# low, triggering an unexpected device reset. Is this risk real? What resistor value does NXP recommend? Key Questions: In the officially recommended scenario where an i.MX8 GPIO controls PERST#, does NXP allow adding an external pull-down resistor, or does it explicitly prohibit external pull-up/pull-down resistors? Is it recommended to use a POR hardware delay circuit to generate PERST#? We look forward to your reply. Thank you!
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