i.NX RT 1060 PMIC_ON_REQ behavior Hello, I am designing a custom board using the MIMXRT1062CVJ5B. The power supplies are connected as shown in the attached figure. Could you please help clarify the following points regarding this configuration? (1) Does PMIC_ON_REQ go high immediately after VDD_SNVS_IN is applied, or is there any delay before it is asserted? (2) When POR_B is driven low, what is the state of PMIC_ON_REQ? Does it remain high or transition low? (3) When VDD_SNVS_IN power is removed, does PMIC_ON_REQ go low? Is the output voltage level guaranteed in this condition? (4) Does VDD_SNVS_IN have an undervoltage lockout (UVLO) function? If so, at what voltage threshold does it become active? (5) In the case shown as "Waveform - A", where only VCC_3V3 is turned off (0 V) while VDD_SNVS_IN remains powered, is this operating condition supported? In this scenario, POR_B transitions from high to low and then from low to high. Can the i.MX RT1062 boot correctly and operate normally after this sequence? Thank you for your support. i.MXRT 106x Re: i.NX RT 1060 PMIC_ON_REQ behavior Hi,
PMIC_ON_REQ is associated with VDD_SNVS_IN and is a push-pull output. There is no specific reference in the documentation indicating a delay before it is asserted. You could test this on an EVK. For example, on the EVKC, you can measure PMIC_ON_REQ through R282 and VDD_SNVS_IN through J30.
The documentation does not guarantee a logic-low or logic-high output state for PMIC_ON_REQ when POR_B is driven low or when VDD_SNVS_IN power is removed.
You can refer to Section 21.3.3, Power Mode Transitions, of the i.MX RT1060 Processor Reference Manual for different scenarios and how PMIC_ON_REQ behaves in each case.
There is no UVLO specification explicitly documented for VDD_SNVS_IN for the i.MX RT1060. The SNVS digital low-voltage detector described in the reference manual includes a mechanism to detect interruptions of the SNVS_LP power supply that could cause the LP control, status, and secure counter values to change.
Regarding question 5, would these scenarios occur during power-up, power-down, or while the application code is running? Best Regards, Pablo Re: i.NX RT 1060 PMIC_ON_REQ behavior Hi, Thank you for your reply. The scenario described in Question 5 assumes that, during normal operation, a temporary abnormal condition occurred on VCC_3V3, causing the voltage to drop. Best regards, Tomokazu Re: i.NX RT 1060 PMIC_ON_REQ behavior Hi
In Section 4.1.6 Low Power Mode Supply Currents of the i.MX RT1060 Data Sheet, a mode is described in which DCDC_IN = 0 V, VDD_HIGH_IN = 0 V, and VDD_SNVS_IN = 3.3 V. For information regarding SNVS mode, please refer to Section 5.2.4 SNVS Mode of AN12085: How to Use i.MX RT Low Power Features.
For the reset signal to be considered valid, it must be asserted for at least one RTC_XTALI clock cycle, according to the values specified in Table 28 Reset Timing Parameters of the data sheet.
Best Regards, Pablo
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