Multi Source Translation Content

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Multi Source Translation Content

Discussions

Sort by:
MPC5777C MMU configuration for calibration Hello, I'm wondering if the MMU can be reconfigured during runtime by the application or should it only be configured by the startup code of a bootloader? If it is possible to reconfigure it during runtime, what should the process look like? Should the existing entry be deleted and a new one written in the same place or can specific entry just be overwritten? Best regards Re: MPC5777C MMU configuration for calibration Hello, I see no issue here as long as you will make sure executed code in not running from regions being reconfigured and the changes wont affect code access in case it is requested by your SW. You cannot change mapping of actively used region by code as you will get exception. Best regards, Peter Re: MPC5777C MMU configuration for calibration Thank you for your response. The idea was to use MMU for calibration switching during engine testing so it would have to be performed when the engine is running. Do you think this is good idea? Best regards Re: MPC5777C MMU configuration for calibration Hello, I'm wondering if the MMU can be reconfigured during runtime by the application or should it only be configured by the startup code of a bootloader? It is application dependent. I recommend to configure MMU at startup, as you need to initialize more than default 4kB of memory for some meaningful execution. If it is possible to reconfigure it during runtime, what should the process look like? You should take care not to use the regions you are reconfiguring. Should the existing entry be deleted and a new one written in the same place or can specific entry just be overwritten? You can simply overwrite it. Just make sure that code is not executed from such part and also there are no conflicts of regions with your application. Best regards, Peter Re: MPC5777C MMU configuration for calibration Sorry Petervlna, pls ignore my previous comment, the picture was not the correct one. pls checkout the below one Is it possible to partially overwrite 1 entry (e.g 64KB) by 4 others entries ( 16KB each) with different properties e.g: like this First: 0x40060000 -> 0x4006FFFF - 64KB - Cache_Inhibit Then: 0x40060000 -> 0x40064000 - 16KB - Cachable 0x40064000 -> 0x40068000 - 16KB - Cache_Inhibit 0x40068000 -> 0x4006C000 - 16KB - Cache_Inhibit 0x4006C000 -> 0x4006FFFF - 16KB - Cache_Inhibit Thank you Re: MPC5777C MMU configuration for calibration Hi Petervlna, Is it possible to overwrite 1 entry by others entries with some overlaps
View full article
I2S 缓冲区处理 是否有关于 I2S 驱动程序缓冲区处理和状态回调的说明?我正在将一个音频处理项目从 Kinetis 移植到 LPC55S69,在 Kinetis 上我使用的是自己的 I2S DMA 驱动程序,我需要弄清楚我的驱动程序中哪些部分可以用 MCUX SDK 驱动程序替代,或者我是否应该跳过它,将自己的驱动程序调整到新硬件上。 根据我从稀少的 SDK 文档中了解到的情况,驱动程序似乎有一个队列,可以接收 I2S_NUM_BUFFERS (4) 条目。它没有提到任何大小限制,所以我假设队列只接受四个指针。 所有提供的示例项目都只使用一个固定的缓冲区。它们会将同一个缓冲区连续排队两次,以避免播放中出现间隙,但并没有说明如何管理多个缓冲区。环回示例中,发送方和接收方使用的是同一个缓冲区,因此内容在不断变化,但没有任何同步机制--它们只是依赖于两个缓冲区的时钟是一致的,不会出现暂停或不同步的情况。演示只改变内容,而不是发送的缓冲区,这对大多数实际应用来说并不安全。 有一个 i2s_transfer_callback_t 的回调,它提供了一个 status_t 类型的参数"completionStatus" ,但 status_t 只是被类型化为 int32_t,没有关于它可以返回值的文档。 有一个包含 BufferComplete、Done 和 Busy 值的匿名枚举,但没有明确说明这些值会在回调中使用。我假设这些是 status_t 的值,BufferComplete 表示发送了一个缓冲区,Done 表示所有缓冲区都已发送完毕。如果能提前知道最终缓冲区是同时生成 BufferComplete和Done,还是只生成 Done 就更好了。 基本 I2S 驱动程序中提供了这一功能。在 I2S_DMA 驱动程序中,有一个单独的 I2S_DMAC回调。手册中似乎完全没有记录。从代码来看,这只是 ISR 使用的一个内部函数。是这样吗?是否有办法在 SDK 文档中区分哪些是导出函数,哪些仅在内部使用?或者,如果不相关,可以完全排除内部内容? 我是否认为完成回调会在 DMA 传输完成时发生?或者在 I2S FIFO 清空时是否有回调?我的应用程序通常无法连续发送音频,因此我需要知道何时在不中断最后一次传输的情况下关闭 I2S 发射器。(感谢硬件设计师允许你选择空闲的 I2S 发射器是发送零还是重复最后一个值——这是真正让事情变得更容易的小动作之一。我有一些应用软件需要双管齐下)。 编辑:我现在最关心的是确定哪个缓冲区刚刚完成。回调似乎没有指定,用户数据与句柄而不是单个传输相关联,而且 DMA 句柄数据是私有的。先进先出是一个显而易见的假设,但我想避免在传输中止或其他情况下出现缓冲区不同步的可能性。 谢谢! Scott Re: I2S buffer handling 我重新提起这个话题,是因为我还真的需要一个合适的答案。我去查看 SDK 在过去两年中是否有所改进,但现在 MCUX 面板(https://ui01.prod-mcuxsd.nxp.com/mcuxsdk/latest/html/index.html)上的文档链接已经失效,而且没有下载离线副本的选项。我在网上搜索了 MCUX SDK 文档,并按照我在那里找到的内容进行了编写。 目前看来,情况没有任何改善。双缓冲演示不仅不会尝试确定发送的是哪个缓冲区,甚至根本不重要,因为它总是在发送同一个缓冲区的更多副本。在这个例子中,没有任何内容能为实际使用该驱动程序提供参考。 我的主要问题仍然是:如何可靠地确定 I2S DMA 驱动程序刚刚发送完哪个缓冲区,从而保证以正确的顺序加载非活动缓冲区?我只是在每次回调时跟踪一个标记,但如果错过一次中断,系统就会失去同步,所有音频都会出现乱码,而且无法判断是否出了问题。 谢谢! Scott Re: I2S buffer handling 卡洛斯,开什么玩笑?对不对? Re: I2S buffer handling 对不起,快速阅读造成了困惑,工作突然加载,快速回答让我感到困惑,我评论说,每个代码都是由相应领域的专家开发的,因此每个代码都不是由一个人编写的,而是由一群具有不同知识的人编写的,因此,尽管可能会有一些错误(我们都有错误),但我相信,如果您可以信任这些代码的话。   另一方面,我们没有太多关于该代码的文档,我目前正在寻找你的信息,但由于缺乏关于该代码的信息,我想我无法快速给你答复,至于你告诉我的,好吧,我不是提供空缺职位的人,尽管如果你是这方面的专家,我们也不介意 I2S 和其他相关主题的专家,所以如果你想成为我们团队的一员,你可以寻找空缺职位并申请。 https://www.nxp.com/company/about-nxp/careers:CAREERS Re: I2S buffer handling 卡洛斯 请重新阅读我的问题。你会看到我的帖子是关于 I2S 的,这是一个同步串行音频接口,与 I2C 协议无关。你提供的链接都与 I2S 或我的问题无关。 我试图使用 MCUX SDK 驱动程序,因为据说这是恩智浦推荐的解决方案。我为 Kinetis 编写了自己的驱动程序,但我想 利用恩智浦已经为此提供的代码,而不是从头开始为 LPC 编写驱动程序。 听起来你是在告诉我,获得所需信息的唯一方法就是逆向工程 MCUX 代码。设置断点并不能告诉我有哪些值是可能的。我刚才做了,完成回调得到的值是 0xa8c。这究竟说明了什么?如果不通过驱动程序进行回溯,就无法查询,也无法了解其他可能的值及其含义。 回读 I2S_DMACallback(),似乎没有提供用于确定刚刚发送哪个缓冲区的机制。这些信息被保存在标有"成员的私人句柄中,不得在驱动程序之外访问或修改。" 别误会我的意思,如果恩智浦愿意支付适当的薪水,我很乐意整天阅读、测试、记录和改进 MCUX SDK 驱动程序代码。 我提出的问题是在实际应用中可靠使用 I2S 驱动程序时需要回答的问题。如果恩智浦不能提供答案,那么我只能认为这些代码从未在实际应用中进行过测试,因此不应该被认为是完整或安全的。是这样吗? Scott Re: I2S buffer handling 我建议您阅读 i2c 手册(https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/nxp-designs/931/1/UM10204.pdf),并在代码中使用断点和观察变量来确定您需要的所有信息   这些链接也很有趣 https://mcuoneclipse.com/2020/06/29/mcuxpresso-sdk-tutorial-using-i2c-driver-on-okdo-e1-board/ https://mcuoneclipse.com/2012/12/04/a-generic-i2c-high-level-driver/ Re: I2S buffer handling 好吧,那我剩下的问题呢? 如何确定刚才发送的是哪个缓冲区?我担心的是,如果应用程序错过了为完成回调提供服务的最后期限,它就会被去同步。在四个缓冲区轮流运行的情况下,它可以漏掉一两个缓冲区而不中断传输,但前提是必须有办法知道哪些缓冲区已经发送。 何时生成回调?最终缓冲区是否会同时生成"缓冲区发送的" 和"完成的" 回调? status_t 可能有哪些值? 以及如何获得完成整个 I2S 传输的回调,这样你才能关闭发射器? 我已经实现了基本功能,但在不了解细节的情况下,很难保证实现的完整和强大。 谢谢! Scott Re: I2S buffer handling 嗨 @scottm 你可以在 sdk_x.x.x_lpcxpresso55s69\ boards\ lpcxpresso55s69\ boards\ lpcxpresso55s69\ driver_examples\ i2s 中找到我们的例子,我们没有更多关于 i2s 的例子了
View full article
I2S buffer handling Is there a description somewhere of the I2S driver's buffer handling and status callbacks? I'm working on porting an audio processing project from Kinetis to the LPC55S69 and on Kinetis I was using my own I2S DMA driver and I need to figure out which pieces of my driver I can replace with the MCUX SDK driver - or if I should just skip it and adapt my own driver to the new hardware. From what I can tell from the sparse SDK docs, it looks like the driver has a queue that takes I2S_NUM_BUFFERS (4) entries. It doesn't mention any size limits so I'm assuming that queue is just taking four pointers. All of the provided example projects use only a single, fixed buffer. They'll queue the same buffer twice in a row to avoid gaps in the playback, but they don't illustrate how to manage multiple buffers. The loopback examples have the sender and receiver using the same buffer, so the contents are changing, but there's no synchronization mechanism of any kind - they simply rely on the fact that both are clocked together and won't ever pause or experience desynchronization. The demos only change the contents, not the buffer being sent, which isn't safe for most real-world applications. There's a callback of i2s_transfer_callback_t, which provides a parameter "completionStatus" of type status_t, but status_t is simply typedef'd to int32_t  with no documentation of the values it can return. There is an anonymous enum with BufferComplete, Done, and Busy values - but nothing to explicitly that these are used in the callback. I'm assuming these are the values for status_t and that BufferComplete means a single buffer has been sent, and Done means all of them are done. It'd be nice to know in advance if the final buffer generates both a BufferComplete and a Done, or if it's just Done. That's provided in the basic I2S driver. In the I2S_DMA driver there's a separate I2S_DMACallback. It doesn't appear to be documented at all in the manual. From the code, it looks like this is strictly an internal function used by the ISR. Is that correct? Is there some way to distinguish in the SDK docs what's an exported function and what's only used internally? Or maybe exclude the internal stuff entirely if it's not relevant? I assume the completion callback happens when the DMA transfer completes? Or is there a callback when the I2S FIFO empties? My application doesn't normally send audio continuously so I need to know when to shut down the I2S transmitter without cutting off the last transmission. (Kudos to the hardware designers for letting you select whether an idle I2S transmitter sends zeroes or repeats the last value - that's one of those little touches that really makes things easier. I have applications that need it both ways.) Edit: My main concern right now is figuring out with certainty which buffer just completed. The callback doesn't seem to specify, the user data is associated with the handle and not the individual transfer, and the DMA handle data is private. First in, first out is an obvious assumption but I'm trying to avoid the possibility of buffer desynchronization if a transfer is aborted or something. Thanks, Scott Re: I2S buffer handling I'm resurrecting this topic because I could still really use a proper answer. I went to check if maybe the SDK has been improved in the past two years but now the documentation links from the MCUX dashboard (to https://ui01.prod-mcuxsd.nxp.com/mcuxsdk/latest/html/index.html) are dead and there's no option to download an offline copy. I googled MCUX SDK documentation and I'm going with what I found there. So far it doesn't look like anything has improved. The double-buffered demo not only doesn't make any attempt to determine what buffer was sent, it doesn't even matter because it's always sending more copies of the same buffer. There's nothing in that example that informs a real-world use of this driver. My main question remains - how do you reliably determine which buffer the I2S DMA driver just finished sending, so you can guarantee that you're loading an inactive buffer in the proper sequence? I'm just tracking a flag with each callback but a single missed interrupt will mean that the system gets desynchronized and all of the audio will be garbled, with no way of telling that there's a problem. Thanks, Scott Re: I2S buffer handling Carlos, you gotta be kidding. Right? Re: I2S buffer handling Sorry for the confusion of a quick reading, suddenly the work is loaded and to give a quick answer made me confused, I comment that each code was developed by specialists in the corresponding area, so each code was not made by one person, but by a group of people with different knowledge, so that, although it may have some errors (we all have them), I believe that if you can trust the code.   On the other hand, we do not have much documentation on this code, and I am currently looking for your information, but due to the lack of info on this code, I do not think I can give you a quick answer, and for what you tell me, well, I am not the one offering vacancies, although if you are an expert on the subject, we would not mind an expert in I2S and other related topics, so if you want to be part of our team, you can look for a vacancy and apply for it. https://www.nxp.com/company/about-nxp/careers:CAREERS Re: I2S buffer handling Carlos, Please reread my questions. You'll see that my post is about I2S, which is a synchronous serial audio interface that's unrelated to the I2C protocol. None of the links you provided have any relevance to I2S or to my questions. I'm attempting to use the MCUX SDK driver because it's supposedly NXP's recommended solution. I wrote my own driver for Kinetis but I'm trying to take advantage of the code that NXP already provides for this purpose rather than writing something for LPC from scratch. It sounds like you're telling me the only way to get the information I need is to reverse-engineer the MCUX code. Setting breakpoints doesn't tell me what values are possible. I did that just now and the completion callback gets a value of 0xa8c. What exactly does that tell me? There's no way to look that up, or to see what other values are possible and what they indicate, short of tracing back through the driver. Reading back through I2S_DMACallback(), it looks like there is no provided mechanism for determining which buffer was just sent. That information is kept in a private handle marked "Members not to be accessed / modified outside of the driver." Don't get me wrong, I'd be happy to spend my days reading, testing, documenting, and improving MCUX SDK driver code - if NXP wants to negotiate an appropriate salary. The questions I'm asking are things that would need to be answered for any reliable, non-trivial use of the I2S driver in real-world applications. If NXP isn't able to provide answers then I have to assume the code was never tested in real-world applications and shouldn't be considered complete or safe. Is that the case? Scott Re: I2S buffer handling I suggest you read the i2c manual (https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/nxp-designs/931/1/UM10204.pdf) and use breakpoints and watch variables in your code to determine all the information that you need   these links are also interesting https://mcuoneclipse.com/2020/06/29/mcuxpresso-sdk-tutorial-using-i2c-driver-on-okdo-e1-board/ https://mcuoneclipse.com/2012/12/04/a-generic-i2c-high-level-driver/ Re: I2S buffer handling OK, what about the rest of my questions? How do you determine which buffer was just sent? I'm concerned that if the application misses a deadline servicing the completion callback that it'll get desynchronized. With four buffers in rotation it can miss one or two and not interrupt the transmission, but only if there's a way to tell which buffers have been sent. When are the callbacks generated? Does the final buffer generate both a "buffer sent" and "done" callback? What are the possible values for status_t? And how do you get a callback for completion of the whole I2S transmission, so you can shut down the transmitter? I've got my basic functionality working, but it's hard to guarantee a complete and robust implementation without knowing the details. Thanks, Scott Re: I2S buffer handling Hi @scottm the examples that we have you can find in SDK_X.X.X_LPCXpresso55S69\boards\lpcxpresso55s69\driver_examples\i2s, we no have more examples with i2s
View full article
How to setup sai1 tdm mode for imx8mq-evk? The end goal is to configure sai1, txd0 for 8 frame, 32-bit, TDM mode (if it's not already) under Yocto Linux.  In "fsl-imx8mq-evk.dts", I see "fsl,sai-multi-lane" and "fsl,dataline,dsd = ...", but there's no mention (that I can find) in the devicetree documentation fsl-sai.txt file to describe either of these two options.    I don't know if I'm even looking in the right place given my goal.  Where should the sai be configured under Linux?   For what it's worth, I think I see how the ak4458 gets configured in alsa.state and alsa.conf, but I'm guessing that this will tell the ak4458 driver how to configure the ak4458, and what I really need is the other end, the sai configuration.   John i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux Multimedia Yocto Project Re: How to setup sai1 tdm mode for imx8mq-evk? Hello everyone, I'm trying to setup a TDM8 on IMXRT1170-EVKB using SAI1 starting from the example "sai_edma_tdm_playback_cm7",provided by MCUXpresso. I'm not using AUD-EXP-42448 necessary for the example so i'm just connected to J76 pins and my goal is to send someting to SAI_RX0 and resend it on SAI_TX0. Can someone explain me how to correctly configure a TDM communication using SAI1?   Re: How to setup sai1 tdm mode for imx8mq-evk? Thank you John, your suggestions will help me a lot and I will try to implement the tdm mode in SAI driver. thank you once again, Sreedhar Re: How to setup sai1 tdm mode for imx8mq-evk? Sorry it's taken a while to respond, but that was quite a while ago and I'm still trying to remember what I did.   It doesn't readily take the form of a "patch" and in the end, there's very little, if anything, different in fsl_sai.c, and a whole lot of changes in other places.   The sai driver is, I think, set up to handle tdm mode, the trick is to create a codec driver that configures the sai driver with the proper parameters.  In the end, I created a new imx- "codec" file based on an existing codec, added my own parameters for my codec in the devicetree so that I could set the format and the tdm width from the devicetree, and then added the codec to the kernel config so it could be selected and built in the kernel configuration and build.    You might be able to shorten some of those steps by creating your own imx-codec file, but simply hardcode the slots, width and fmt into the imx_(yourcodecname)_hw_params() function.  Take a look at imx-ak4485.c and the calls to snd_soc_dai_set_fmt() and snd_soc_dai_set_tdm_slot().   Hope this helps.  If you still want to see my version of the "not a codec" codec driver, I can provide it, but it may take me a while to clean up the code to be presentable.   John Re: How to setup sai1 tdm mode for imx8mq-evk? Hi John, Good day!! I understand from your post https://community.nxp.com/thread/499282 , you made tdm operation succesful in sai1 as master. Could you please let us know the changes you have made to the fsl_sai.c diver for supporting tdm operation. Could you please post the patch of it. Thank you, Sreedhar Re: How to setup sai1 tdm mode for imx8mq-evk? See https://community.nxp.com/thread/499282  Re: How to setup sai1 tdm mode for imx8mq-evk?  Update, and a follow-up question involving the same setup.  I've had some luck hacking at the fsl_sai.c driver to support 8-frame tdm on sai1 and successfully drove an AKM4458 eval board with the imx8mq eval board as frame sync and bit clock master.  The next step is to configure the imx8mq eval board as frame sync and bit clock slave instead of master.   I thought this would be as simple as: NOT setting the BCD bit in TCR2 NOT setting the FSD bit in TCR4 But having done this, and confirming the register settings (and supplying the external frame sync and bit clock), I no longer see data on the transmit line, and the 'play' operation eventually errors out with an I/O error.  To add to the mystery, MCLK is no longer being generated by the imx8mq EVK.  I thought that would have been independent of the two bits in the TCR2 and TCR4 registers. Is there something else that must be done in software or the kernel configuration to change a working SAI1 clock master to a clock slave ? John Re: How to setup sai1 tdm mode for imx8mq-evk?  Hi John unfortunately currently there are no tdm configurations which could be set through dts file, so one will have to change sai driver according to tdm configuration for used codec (that should be described in codec datasheet). > I'd like to know what "sai-multi-lane" and "dataline,dsd = ..." do.   one can check driver sources: driver linux/sound/soc/fsl/fsl_sai.c fsl_sai.c\fsl\soc\sound - linux-imx - i.MX Linux kernel Note NXP has special service for helping porting drivers for customer needs NXP Professional Services | NXP  Best regards igor Re: How to setup sai1 tdm mode for imx8mq-evk? Hi, Igor, Thank you for replying, but I'm not sure you completely understood.  I know about the documentation you linked to in your reply, I specifically mentioned them in my original.  But there are two options included in the devicetree for the evk (and apparently supported in the sai driver, from what I can tell) that are not included in the documentation.   I'd like to know what "sai-multi-lane" and "dataline,dsd = ..." do.   As for your suggestion to set the slot widths, please forgive my ignorance, but how would that best be accomplished?  In a user-space app ?  Wouldn't it be better to modify the fsl_sai.c driver to support TDM options in the devicetree?  Or is that more complicated than it seems?   John Re: How to setup sai1 tdm mode for imx8mq-evk? Hi John tdm is supported in sai driver linux/sound/soc/fsl/fsl_sai.c fsl_sai.c\fsl\soc\sound - linux-imx - i.MX Linux kernel  fsl-sai.txt\sound\bindings\devicetree\Documentation - linux-imx - i.MX Linux kernel  unfortunately there are no tdm configurations which could be set in dts file. fsl-sai.txt\sound\bindings\devicetree\Documentation - linux-imx - i.MX Linux kernel  one can check driver for tdm settings, in fsl_sai_set_dai_tdm_slot(), sai->slot_width = slot_width; and set them to necessary values. Best regards igor ----------------------------------------------------------------------------------------------------------------------- Note: If this post answers your question, please click the Correct Answer button. Thank you! -----------------------------------------------------------------------------------------------------------------------
View full article
如何为 imx8mq-evk 设置 sai1 tdm 模式? <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 最终目标是在 Yocto Linux 下将 sai1、txd0 配置为 8 帧、32 位、TDM 模式(如果尚未配置)。 在"fsl-imx8mq-evk.dts" 中,我看到"fsl,sai-multi-lane" 和"fsl,dataline,dsd = ..." ,但在 devicetree 文档 fsl-sai.txt 文件中没有提到(我能找到)这两个选项中的任何一个。 我不知道我的目标是否正确。 在 Linux 下应在何处配置 sai? 不管怎样,我想我知道alsa.state 和 alsa.conf 是如何配置 ak4458 的了、但我猜这将告诉 ak4458 驱动程序如何配置 ak4458,而我真正需要的是另一端,即 sai 配置。 约翰 i.MX 8M | i.MX 8M Mini | i.MX 8M Nano Linux 多媒体 Yocto Project Re: How to setup sai1 tdm mode for imx8mq-evk? 大家好,我正在尝试在 IMXRT1170-EVKB 上使用 SAI1 设置 TDM8,从 MCUXpresso 提供的示例"sai_edma_tdm_playback_cm7" 开始。我没有使用示例中所需的 AUD-EXP-42448,所以我只是连接到 J76 引脚,我的目标是向 SAI_RX0 发送信息,然后在 SAI_TX0 上重新发送。 谁能告诉我如何使用 SAI1 正确配置 TDM 通信?   Re: How to setup sai1 tdm mode for imx8mq-evk? <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 谢谢你,约翰、 您的建议对我帮助很大,我会尝试在 SAI 驱动程序中实现 tdm 模式。 再次感谢您、 斯里达尔 Re: How to setup sai1 tdm mode for imx8mq-evk? <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 很抱歉过了很久才回复,但那是很久以前的事了,我还在努力回想我都做了些什么。 "补丁" 的形式,最终,fsl_sai.c 几乎没有什么不同、以及其他地方的许多变化。 我认为 sai 驱动程序安装为处理 tdm 模式,诀窍是创建一个编解码器驱动程序,使用正确的参数配置 sai 驱动程序。最后,我基于现有编解码器创建了一个新的 imx-" 编解码器 " 文件,在 devicetree 中为我的编解码器添加了自己的参数,这样我就可以从 devicetree 中设置格式和 tdm 宽度,然后将编解码器添加到内核配置中,这样就可以在内核配置和版本中进行选择和版本。 您也许可以通过创建自己的 imx-codec 文件来缩短其中的一些步骤,但只需将槽位、宽度和 fmt 硬编码到 imx_(yourcodecname)_hw_params() 函数中即可。 请查看 imx-ak4485.c 以及对 snd_soc_dai_set_fmt() 和 snd_soc_dai_set_tdm_slot() 的调用。 希望对您有所帮助。 如果你还想看我的"not a codec" 编解码器驱动程序版本,我可以提供,但我可能要花一些时间来整理代码,使其更易于使用。 约翰 Re: How to setup sai1 tdm mode for imx8mq-evk? <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,约翰、 日安 我从您的帖子中了解到https://community.nxp.com/thread/499282作为主人,您在 Sai1 成功地进行了 tdm 操作。 你能否与我们联系你对 fsl_sai.c 所做的更改支持 TDM 运行的潜水员。 能否请您发布一下补丁。 谢谢你,斯里达尔 Re: How to setup sai1 tdm mode for imx8mq-evk? <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 参见https://community.nxp.com/thread/499282 Re: How to setup sai1 tdm mode for imx8mq-evk?  <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 更新,以及涉及相同设置的后续问题。 我在黑客攻击 fsl_sai.c 时取得了一些进展。该驱动程序支持 sai1 上的 8 帧 tdm,并成功驱动了使用 imx8mq 评估板作为帧同步和位时钟主器的 AKM4458 评估板。下一步是将 imx8mq 评估板配置为帧同步和位时钟从机而不是主机。 我以为这很简单: 不要在 TCR2 中设置 BCD 位 不设置 TCR4 中的 FSD 位 但是,在完成上述操作并确认寄存器设置(以及提供外部帧同步和位时钟)后,我就再也看不到传输线上的数据了,而且 "播放 "操作最终也因 I/O 错误而出错。 更令人费解的是,MCLK 不再由 imx8mq EVK 产生。 我以为这与 TCR2 和 TCR4 寄存器中的两个位无关。 要将工作中的 SAI1 时钟主控程序变为时钟从属程序,是否还需要在软件或内核配置中做其他操作? 约翰 Re: How to setup sai1 tdm mode for imx8mq-evk?  <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,约翰 遗憾的是,目前还没有可以通过 dts 文件设置的 tdm 配置、 因此,必须根据所用编解码器的 tdm 配置更改 sai 驱动程序(即 应在编解码器数据表中说明)。 > 我想知道" sai-multi-lane" 和"dataline,dsd = ..." 的作用。 可以查看驱动程序源代码:driver linux/sound/soc/fsl/fsl_sai.c fsl_sai.c\fsl\soc\sound - linux-imx - i.MX Linux 内核 注意:恩智浦提供特殊服务,帮助移植驱动程序以满足客户需求 恩智浦专业服务 | 恩智浦 问候 igor Re: How to setup sai1 tdm mode for imx8mq-evk? <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 你好,伊戈尔 谢谢您的回复,但我不确定您是否完全理解。 我知道你在回复中链接到的文档,我在原文中特别提到了它们。 但 evk 的 devicetree 中包含了两个选项(据我所知,sai 驱动程序显然也支持这两个选项),而这两个选项并未包含在文档中。 我想知道" sai-multi-lane" 和"dataline,dsd = ..." 的作用。 至于您提出的设置插槽宽度的建议,请原谅我的无知,但怎样才能最好地实现呢? 在用户空间应用程序中? 修改 fsl_sai.c 是否更好?驱动程序是否支持 Devicetree 中的 TDM 选项? 还是说,这比想象的要复杂得多? 约翰 Re: How to setup sai1 tdm mode for imx8mq-evk? <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 嗨,约翰 sai 驱动程序 linux/sound/soc/fsl/fsl_sai.c 支持 tdm fsl_sai.c\fsl\soc\sound - linux-imx - i.MX Linux 内核 fsl-sai.txt\sound\bindings\devicetree\Documentation - linux-imx - i.MX Linux 内核 遗憾的是,没有可以在 dts 文件中设置的 tdm 配置。 fsl-sai.txt\sound\bindings\devicetree\Documentation - linux-imx - i.MX Linux 内核 可以检查驱动程序的 tdm 设置,在 fsl_sai_set_dai_tdm_slot() 中,sai->slot_width = slot_width; 并将其设置为必要的值。 问候 igor ----------------------------------------------------------------------------------------------------------------------- 注:如果本帖回答了您的问题,请点击 "正确答案 "按钮。Thank you! -----------------------------------------------------------------------------------------------------------------------
View full article
S32k312 的 PLL 计算 大家好 我在设计中使用的是 S32K312 微芯片。请帮我计算 PLL 的输出频率。我们使用的是 40 MHz 的外部晶振。你能提供一个计算示例吗?如果我们使用 40 MHz 晶振可以吗? 请提供 S32K312 的时钟计算器。 Re: PLL calculation for S32k312 你好@mogilipuri_harish,你能解决这个问题吗?我也遇到了同样的问题。我的配置完全相同,使用的是 MCAL 6.0.0 版 S32K312。 面对"PLL ODIV2 = 2" 超出范围的误差 Re: PLL calculation for S32k312 Hi@mogilipuri_hari sh 除数据表外,没有更多关于时钟配置的指导文件 如图所示,RTD 2.0.1 及以上版本有用于 S32K312 的例程。 Re: PLL calculation for S32k312 嗨 我正在尝试进行 PLL 时钟计算。您能提供一些如何进行计算的说明吗?比如参考文档。我没有在工具中找到 S32k312 示例,能否请您分享一下,这将对我有所帮助。 Re: PLL calculation for S32k312 您好, 供你参考,例如: PLL 输出频率范围必须在 640MHz~1,28GHz 之间。 Re: PLL calculation for S32k312 您好, 没有完全理解你的问题,你的意思是哪些分频器值可以改变? 图中的这些参数可以更改,您可以在 S32 DS 中查看这些时钟树配置。 Re: PLL calculation for S32k312 在这里,我们可以更改哪些变量值? Re: PLL calculation for S32k312 谢谢提醒 在 S32K312 中,CORE_CLK=160Mhz 仍可运行,但不建议客户使用这种方式,会有未知风险 Re: PLL calculation for S32k312 你好,森伦特、 实际上,S32k312 的核心时钟频率为 120Mhz。 Re: PLL calculation for S32k312 Hi@mogilipuri_harish FXOSC 的频率可以从 8MHz 到 40MHz,所以 40MHz 的晶振应该没问题。 您可以使用"S32 Design Studio for S32 Platform" 设置时钟树。 例如: PS: 我们提供的 S32K312EVB 使用 16MHz 外部晶振
View full article
SFPモジュールがLinuxで動作しない 現在、カスタム LS1046A ベースのボードの立ち上げ作業の真っ最中で、Linux を正常に起動できるまでになりました (lsdk2108_yocto_tiny_LS_arm64.itb を使用)。 現在直面している問題は、SFP モジュールがスイッチとのリンクを確立しないということですが、Linux の u-boot でのみ正常に動作します。 出力は次のとおりです。 [ 2.105567] sfp sfp-xfi0: Host maximum power 3.0W [ 2.110647] sfp sfp-xfi1: Host maximum power 3.0W [ 2.133460] fsl_dpaa_mac 1ae2000.ethernet eth0: Probed interface eth0 [ 2.158141] fsl_dpaa_mac 1ae8000.ethernet eth1: Probed interface eth1 [ 2.182874] fsl_dpaa_mac 1aea000.ethernet eth2: Probed interface eth2 [ 2.207768] fsl_dpaa_mac 1af0000.ethernet eth3: Probed interface eth3 [ 2.232690] fsl_dpaa_mac 1af2000.ethernet eth4: Probed interface eth4 [ 2.239517] clk: Disabling unused clocks [ 2.244553] Freeing unused kernel memory: 3008K [ 2.249175] Run /init as init process INIT: version 2.99 booting Starting udev [ 2.358215] udevd[125]: starting version 3.2.10 [ 2.434319] sfp sfp-xfi0: module FLEXOPTIX P.8596.02 rev A sn F7B2H4B dc 240827 [ 2.488055] sfp sfp-xfi1: module FLEXOPTIX P.C30.1 rev 1.0 sn F7B0V11-B dc 240722 [ 2.495775] hwmon hwmon6: temp1_input not attached to any thermal zone [ 3.394590] random: crng init done [ 3.401138] udevd[126]: starting eudev-3.2.10 [ 3.442182] fsl_dpaa_mac 1ae2000.ethernet fm1-mac2: renamed from eth0 [ 3.483254] fsl_dpaa_mac 1ae8000.ethernet fm1-mac5: renamed from eth1 [ 3.514694] fsl_dpaa_mac 1aea000.ethernet fm1-mac6: renamed from eth2 [ 3.538708] fsl_dpaa_mac 1af0000.ethernet fm1-mac9: renamed from eth3 [ 3.566712] fsl_dpaa_mac 1af2000.ethernet fm1-mac10: renamed from eth4 ご覧のとおり、挿入された両方のモジュールが正しく検出され、いずれのインターフェースでも問題は報告されておらず、起動すると正常に動作します。 root@TinyLinux:~# ip link set fm1-mac9 up [ 14.332682] fsl_dpaa_mac 1af0000.ethernet fm1-mac9: configuring for inband/10gbase-kr link mode root@TinyLinux:~# ip link set fm1-mac10 up [ 19.500673] fsl_dpaa_mac 1af2000.ethernet fm1-mac10: configuring for inband/10gbase-kr link mode root@TinyLinux:~# ip a 1: lo: mtu 65536 qdisc noqueue qlen 1000 link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00 inet 127.0.0.1/8 scope host lo valid_lft forever preferred_lft forever 2: fm1-mac2: mtu 1500 qdisc noop qlen 1000 link/ether 00:04:9f:08:06:4a brd ff:ff:ff:ff:ff:ff 3: fm1-mac5: mtu 1500 qdisc noop qlen 1000 link/ether 00:04:9f:08:06:4b brd ff:ff:ff:ff:ff:ff 4: fm1-mac6: mtu 1500 qdisc noop qlen 1000 link/ether 00:04:9f:08:06:4c brd ff:ff:ff:ff:ff:ff 5: fm1-mac9: mtu 1500 qdisc mq qlen 1000 link/ether 00:04:9f:08:06:4d brd ff:ff:ff:ff:ff:ff 6: fm1-mac10: mtu 1500 qdisc mq qlen 1000 link/ether 00:04:9f:08:06:4e brd ff:ff:ff:ff:ff:ff デバイス ツリーでどのモードを試しても、キャリアなしになる理由がわかりません。xfi、xsgmii、10gbase-r を試しましたが、何も機能しません。 お知らせ下さい。 QorIQ LS1デバイス Re: SFP module not working in Linux Serdes クロックをどのように設定しますか?私も興味があります Re: SFP module not working in Linux こんにちは 、 私たちも同じ問題に直面しています。私たちは、serdes1 レーン 1 上の LX2160ardb ベースのカスタム開発ボードに 10G の物理インターフェースを導入しています。ケージは検出できますが、リンクを確立できません。また、SerDes リファレンス クロックを 156.25Mhz に設定しました。 ありがとう Re: SFP module not working in Linux 後世のために: 問題を修正しました。クロック MUX を低く駆動していたピンの RCW を構成するのを忘れていたため、必要な156.25 MHzではなく、 100 MHz のクロックが Serdes リファレンス クロック入力に供給されていたことが判明しました。RCW を修正した後、すべてが正常に動作するようになりました。
View full article
关于 ADC 通道分配 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 你好,社区 在数据表 99 中分配给 ADC1_IN0 至 ADC1_IN3。 另一方面,在《参考手册》的 ADC 存储器映射中,ADC1 有 CH_A 到 CH_D。 是否可以将通道 0 指定为 CHA_SEL,通道 1 指定为 CHB_SEL,通道 2 指定为 CHC_SEL,通道 3 指定为 CHD_SEL,以支持以下操作? IN0-CH_A IN1-CH_B IN2-CH_C IN3-CH_D 顺祝商祺! 请访问 i.MX7 双核 About ADC channel assignment 你好,伊戈尔帕季科夫。 这是一个解决方案,但我不明白,所以我有一个问题。 根据数据手册中的引脚分配,ADC1_IN0 至 ADC2_IN3 共有八个物理输入端。 在参考手册中,adcx_ch_A_CFG1 的 CHA_SEL 的范围从 0 到 15。 ADC1_INx 和 Channelx 对应的是什么? 还是它们互不相关? 应如何设置 ADC2_IN0? 顺祝商祺! Re: About ADC channel assignment <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 后藤 是的,这是可能的。如第 14.1.1 节所述概述 i.MX 7Dual 应用处理器参考手册 "ADC 最多支持五个逻辑组(ChA / ChB / ChC / ChD / SW)的转换。每组可从 0 - 15 个物理通道中选择一个通道 。" 问候 igor ----------------------------------------------------------------------------------------------------------------------- 注:如果本帖回答了您的问题,请点击 "正确答案 "按钮。Thank you! -----------------------------------------------------------------------------------------------------------------------
View full article
如何使用 s32k144 aips? HI 我需要动态保护和解除保护闪存。 因此,我研究了 MPU、闪存保护寄存器和 AIPS。 无法解决 MPU 和闪存保护寄存器问题。 而 AIPS(外设访问保护)的解释不足以在 RM 中使用。 我认为 OPACR 中的 wp bits 与此有关。 但我不知道每个 wp 位都指向哪里。 请详细说明如何使用 AIPS? 谢谢! 顺祝商祺! 菲利普 Re: How to use s32k144 aips? 你好,@minsky、 您能创建一个新的主题吗? Re: How to use s32k144 aips? 你好,请问外设的访问控制如何确定在哪个寄存器的哪个插槽中? Re: How to use s32k144 aips? 你好,菲利普、 X "表示 S32K1 衍生型号上有外设访问控制。 FTFC 的外设访问控制位于 OPACRA 的 0 号插槽。 这取决于您的要求,如果您想保护 FTFC 寄存器不被写入,则设置 OPACRA[WP0] = 1。 此致, 丹尼尔 Re: How to use s32k144 aips? 你好,丹尼尔 X'是什么意思? 您想对哪些外设寄存器进行写保护? :我想对 FTFC 进行写保护。 因此,应该是 OPACR Slot1。 但我该如何保护呢? 谢谢! 顺祝商祺! 菲利普 Re: How to use s32k144 aips? 你好,菲利普、 您想对哪些外设寄存器进行写保护? 请参阅 RM 随附的S32K1xx_Mamory_Map.xlsx。 此致, 丹尼尔
View full article
リモートアクティベーションサーバーへのアクティベーション要求の送信中にエラーが発生しました NXPソフトウェアアクティベーション リモート アクティベーション サーバーにアクティベーション要求を送信し、結果の応答をプロセッシングするときにエラーが発生しました。ライセンス サーバーまたは Operations サーバーに接続できませんでした。(FNPエラー50041,41143,34) これはオンライン インストール中です、オフライン インストールも実行されていません、無効なオフライン応答、応答タイプが表示されています 回复: Error sending an activation request to a remote activation server S32 Design Studio for ARM バージョン 2.2 のインストール中に、「リモート アクティベーション サーバーにアクティベーション要求を送信し、結果の応答を処理中にエラーが発生しました。」というエラーが発生しました。ライセンス サーバーまたは Operations サーバーへの接続に失敗しました。(FNPエラー50041,41143,34)の問題を解決するにはどうすればよいですか?以下はログです。 Re: Error sending an activation request to a remote activation server ありがとうございます。解決しました。公式サイトを参考にしました。 https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/S32-Design-Studio-Offline-activation-issue-hot-fix/ta-p/1119120 Re: Error sending an activation request to a remote activation server これはインストール ログです。 Re: Error sending an activation request to a remote activation server これはログ内のエラー メッセージですが、管理者として実行しています。 Re: Error sending an activation request to a remote activation server これはオフラインの状況です Re: Error sending an activation request to a remote activation server こんにちは、 どのアプリケーションをアクティブ化しようとしているのかを教えていただけますか?また、エラーの画像を共有していただけますか? ぜひお知らせください。
View full article
ksz8863およびlwipとのインターフェースとなるLPC1768 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> ハイ LPC1768 をリファレンス デザインとして使用すると、lwip tcp の例で問題なく動作します。 UDP の例では、Windows アプリからデータを送受信 CAN。 Microchip の 3 ポート スイッチ ksz8863 を LPC1768 にコネクテッドしましたが、udp が動作しません。 ステータスは次のとおりです: 1.スイッチへのリンクがあり、PHYレジスタを読み取るのと同じコードで読み取ることができます(mdioとmdcはfunc1です) 2. ビットバン、SMI、MIIを使用してチップにアクセスできます(mdioとmdcをgpio - func0に変更します) 3. スイッチで PHY モードではなく MAC モードを使用しようとしましたが、どちらも機能しませんでした。 マイクロコントローラにイーサネット・スイッチをコネクテッドして lwip を操作した人はいますか? コードに変更を加える必要はありますか? スイッチを phymore モードまたは mac モードで動作するように設定する必要がありますか (念のため) 質問はLPC1768 + ksz8863 + lwip + udpに直接CAN ただし、任意のマイクロ コントローラ -> ポート スイッチ -> lwip + udp にも適用されます。 どのような情報でも歓迎します。 よろしくお願いします。 LPC17xx LPCOpen Re: LPC1768 to interface with ksz8863 and lwip 可能であれば、ksz8863とlpc1768のインターフェース図を共有してください。 Re: LPC1768 to interface with ksz8863 and lwip こんにちは、 KSZ8863 と LPC4088 をインターフェースすることも計画しています。同じシリーズの NXP の LPC1768 を使用したことがあるので、LPC4088 用のドライバを実装する際に役立つコードを共有していただけませんか? ご返信をお待ちしております。 よろしくお願いします。 ディーパク Re: LPC1768 to interface with ksz8863 and lwip <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> 問題を発見しました emac_config.h内 PHYアドレスがある /* MII/RMIIにコネクテッドされたPHYアドレス */ #LPC_PHYDEF_PHYADDR 3 を定義する 物理アドレスは3であるべきである スイッチには3つのポートがあり、MIIは現在ポート3にコネクテッドされているため リファレンス・デザインではポート1にコネクテッドされていた これが唯一行うべき変更点です。
View full article
AH1902 アプリケーションのヒント UJA1169Aのデータシート(2020年5月12日改訂版)の12.2節では、AH1902アプリケーションヒント - ミニ高速CANシステムの基礎に関する文書について説明しています。 チップ UJA116xA。このドキュメントを NXP の Web サイトで見つけることができません。入手可能でしょうか? デイブ 回复: AH1902 Application hints 私も同じです。この文書は見つかりましたか?
View full article
AH1902 Application hints In the data sheet (Rev 1,12 May 2020) for the UJA1169A, section 12.2 describes a document, AH1902 Application Hints - Mini high speed CAN system basis chips UJA116xA. I am unable to find this document on the NXP website. Is it available? Dave 回复: AH1902 Application hints The same to me. Do you find this document now?
View full article
ADCチャネル割り当てについて <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> こんにちは、コミュニティの皆様 データシートの表99のADC1_IN0~ADC1_IN3に割り当てられます。 一方、リファレンスマニュアルのADCメモリマップでは、ADC1にはCH_AからCH_Dがあります。 以下をサポートするために、チャネル 0 を CHA_SEL、チャネル 1 を CHB_SEL、チャネル 2 を CHC_SEL、チャネル 3 を CHD_SEL に割り当てることは可能ですか? IN0-CH_A IN1-CH_B IN2-CH_C IN3-CH_D よろしくお願いいたします www.freescale.comのサイトに入って下さい i.MX7Dual About ADC channel assignment こんにちは、igorpadykovさん。 解決策なのですが、理解できないSO質問があります。 データシートのピン割り当てによると、ADC1_IN0 から ADC2_IN3 までの 8 つの物理入力があります。 リファレンスマニュアルでは、ADCx_CH_A_CFG1 の CHA_SEL の範囲は 0 ~ 15 です。 ADC1_INx と Channelx は何に対応していますか? それとも無関係でしょうか? ADC2_IN0はどのように設定すればよいでしょうか? よろしくお願いいたします。 Re: About ADC channel assignment <meta http-equiv="Content-Type" content="text/html; charset=utf-8" /> こんにちは後藤 はい、可能です。14.1.1節で説明したように概要 i.MX 7デュアルアプリケーションプロセッサリファレンスマニュアル 「ADCは最大5つのロジックグループ(ChA / ChB / ChC / ChD / SW)をサポートします。各グループは1つのチャンネルを選択できます 0 〜 15 の物理チャネル。 よろしくお願いします イゴール ----------------------------------------------------------------------------------------------------------------------- 注: この投稿で質問が解決した場合は、「正解」ボタンをクリックしてください。ありがとう! -----------------------------------------------------------------------------------------------------------------------
View full article
PLL calculation for S32k312 hello team, i am using the S32K312 microchip in our design. can please help me to calculate the PLL output frequency. We are using 40 MHz external crystal oscillator. can you provide one example calculation? is it okay if you we are using 40 MHz crystal oscillator?  please provide the clock calculator for S32K312. Re: PLL calculation for S32k312 Hi @mogilipuri_harish , were you able to resolve this issue. i am also dealing with same issue. i do have exactly same configuration , using MCAL 6.0.0 for S32K312. facing error with "PLL ODIV2 = 2 " out of range Re: PLL calculation for S32k312 Hi@mogilipuri_hari sh Apart from the data sheet, there is no more guidance document for clock configuration As shown in the figure,the version RTD 2.0.1 and above have routines for S32K312 Re: PLL calculation for S32k312 hi  i am trying do this PLL clock calculation. can you given some notes how to do this calculation? like reference document. and i didn't find S32k312 example in tools, can you please share that it will be helpful to me. Re: PLL calculation for S32k312 Hi, for your reference,for example: PLL output frequency must be in range:640MHz~1,28GHz. Re: PLL calculation for S32k312 Hi, Didn't fully understand your question, do you mean which divider values can be changed? these parameters in the picture can be changed, you can view these clock tree configuration in S32 DS. Re: PLL calculation for S32k312 here what are the variable values we can change?? Re: PLL calculation for S32k312 thanks for reminding In S32K312, CORE_CLK=160Mhz can still run, but it is not recommended for customers to use this way, there will be unknown risks Re: PLL calculation for S32k312 hello senlent, actually core clock frequency for S32k312 is 120Mhz. Re: PLL calculation for S32k312 Hi@mogilipuri_harish The FXOSC can be from 8MHz to40MHz,so the 40MHz crystal oscillator should be ok. you can use "S32 Design Studio for S32 Platform" to set the clock tree. for example: PS:The S32K312EVB we provide uses a 16MHz external crystal oscillator
View full article
AH1902 应用提示 在 UJA1169A 的数据表(2020 年 5 月 12 日修订版 1)中,第 12.2 节介绍了一份文件,即 AH1902 应用提示 - Mini 高速 CAN 系统基础 芯片 UJA116xA。我无法在恩智浦网站上找到这份文件。有吗? 戴夫 回复: AH1902 Application hints 我也一样。你现在找到这份文件了吗?
View full article
How to use s32k144 aips? Hi I need to protect and unprotect the flash memory dynamicaly. So I studied MPU and Flash protection register and AIPS. MPU and Flash protection register cannot be solution. And the AIPS(peripheral access protection) explanation is not enough to use in RM. I think wp bits in OPACR is something related. But I can't figure out that each wp bits indicate to where. Can you please explain how to use AIPS in detail? Thanks Best Regards Phillip Re: How to use s32k144 aips? Hi @minsky, Can you create a new thread? Re: How to use s32k144 aips? Hi, how is the access control for a peripheral determined in which register in which slot? Re: How to use s32k144 aips? Hi Phillip, the 'X' means that the Peripheral Access Control is present on the S32K1 derivative. The Peripheral Access Control for FTFC is in OPACRA, Slot 0. It depends on your requirements, if you want to write-protect the FTFC registers agains any write, set OPACRA[WP0] = 1. Regards, Daniel Re: How to use s32k144 aips? Hi Daniel What does the 'x's mean? Which peripheral registers do you want to write-protect? : I want to write-protect the FTFC. So OPACR Slot1 would be the one. But how can I protect? Thanks Best Regards Phillip Re: How to use s32k144 aips? Hello Phillip, Which peripheral registers do you want to write-protect? Please refer to the S32K1xx_Mamory_Map.xlsx that is attached to the RM. Regards, Daniel
View full article
Error sending an activation request to a remote activation server NXP Software Activation Error sending an activation request to a remote activation server and processing theresulting response.Failed to connect to the license server or Operations server. (FNP error50041,41143,34) 这是在线安装,离线安装也不行,显示invalid offline response,response type 回复: Error sending an activation request to a remote activation server I encountered while installing S32 Design Studio for ARM Version 2.2, Error sending an activation request to a remote activation server and processing theresulting response . Failed to connect to the license server or Operations server. (FNP error 50041,41143,34) problem, how to solve it, here is the log Re: Error sending an activation request to a remote activation server thanks I have solved it, the official website referenced https://community.nxp.com/t5/S32-Design-Studio-Knowledge-Base/S32-Design-Studio-Offline-activation-issue-hot-fix /ta-p/1119120 Re: Error sending an activation request to a remote activation server This is the installation log Re: Error sending an activation request to a remote activation server This is the log error message, but I'm running it as administrator Re: Error sending an activation request to a remote activation server This is offline situation Re: Error sending an activation request to a remote activation server Hi, Can you let us know which application you are trying to activate? Also, can you share an image of your error? Please, let us know.
View full article
About ADC channel assignment Hello,Community Assigned to ADC1_IN0 to ADC1_IN3 in Table 99 of the data sheet. On the other hand, in the ADC memory map of Reference Manual, ADC1 has CH_A to CH_D. Is it possible to assign Channel 0 to CHA_SEL, Channel 1 to CHB_SEL, Channel 2 to CHC_SEL, and Channel 3 to CHD_SEL to support the following? IN0-CH_A IN1-CH_B IN2-CH_C IN3-CH_D best regards Goto i.MX7Dual About ADC channel assignment Hello igorpadykov. This is a solution, but I don't understand it, so I have a question. According to the pin assignment in the datasheet, there are eight physical inputs, ADC1_IN0 to ADC2_IN3. In the reference manual, CHA_SEL of ADCx_CH_A_CFG1 ranges from 0 to 15. What do ADC1_INx and Channelx correspond to? Or are they unrelated? How should I set ADC2_IN0? Best regards. Re: About ADC channel assignment Hi Goto yes this is possible. As described in sect.14.1.1 Overview i.MX 7Dual Applications Processor Reference Manual "ADC supports conversion up to five logic groups (ChA / ChB / ChC / ChD / SW). Each group can select one channel from 0 - 15 physical channels." Best regards igor ----------------------------------------------------------------------------------------------------------------------- Note: If this post answers your question, please click the Correct Answer button. Thank you! -----------------------------------------------------------------------------------------------------------------------
View full article
s32k144 aips の使い方は? ハイ フラッシュメモリを動的に保護したり保護解除したりする必要があります。 SO、MPU とフラッシュ保護レジスタ、AIPS について勉強しました。 MPU およびフラッシュ保護レジスタは解決できません。 また、AIPS(ペリフェラルアクセス保護)の説明は、RM で使用するには不十分です。 OPACR の wp ビットは関連していると思います。 しかし、各 wp ビットがどこを示しているのかわかりません。 AIPSの使い方を詳しく教えていただけますか? よろしくお願いします。 よろしくお願いいたします。 フィリップ Re: How to use s32k144 aips? こんにちは@minsky 、 新しいThreadを作成していただけますか? Re: How to use s32k144 aips? こんにちは。周辺機器のアクセス制御では、どのレジスタとどのスロットにあるかをどのように決定するのでしょうか? Re: How to use s32k144 aips? こんにちは、フィリップ。 「X」は、S32K1 派生製品にペリフェラル アクセス制御が存在することを意味します。 FTFC の周辺アクセス制御は、OPACRA のスロット 0 にあります。 要件によって異なりますが、FTFCレジスタを書き込みから保護する場合は、OPACRA[WP0] = 1を設定します。 よろしくお願いいたします。 ダニエル Re: How to use s32k144 aips? こんにちは、ダニエル 「x」は何を意味していますか? どのペリフェラルレジスタを書き込み保護しますか? : FTFC を書き込み禁止にしたいです。 SO OPACR Slot1 が該当します。 でもどうやってCAN? よろしくお願いします。 よろしくお願いいたします。 フィリップ Re: How to use s32k144 aips? こんにちは、フィリップ。 どのペリフェラルレジスタを書き込み保護しますか? RM に添付されているS32K1xx_Mamory_Map.xlsxを参照してください。 よろしくお願いいたします。 ダニエル
View full article