hello team,
i am using the S32K312 microchip in our design. can please help me to calculate the PLL output frequency. We are using 40 MHz external crystal oscillator. can you provide one example calculation? is it okay if you we are using 40 MHz crystal oscillator?
please provide the clock calculator for S32K312.
facing error with "PLL ODIV2 = 2 " out of range
Hi@mogilipuri_hari
Apart from the data sheet, there is no more guidance document for clock configuration
As shown in the figure,the version RTD 2.0.1 and above have routines for S32K312
hi
i am trying do this PLL clock calculation. can you given some notes how to do this calculation? like reference document. and i didn't find S32k312 example in tools, can you please share that it will be helpful to me.
Hi,
for your reference,for example:
PLL output frequency must be in range:640MHz~1,28GHz.
Hi,
Didn't fully understand your question, do you mean which divider values can be changed?
these parameters in the picture can be changed, you can view these clock tree configuration in S32 DS.
here what are the variable values we can change??
thanks for reminding
In S32K312, CORE_CLK=160Mhz can still run, but it is not recommended for customers to use this way, there will be unknown risks
hello senlent,
actually core clock frequency for S32k312 is 120Mhz.
The FXOSC can be from 8MHz to40MHz,so the 40MHz crystal oscillator should be ok.
you can use "S32 Design Studio for S32 Platform" to set the clock tree.
for example:
PS:The S32K312EVB we provide uses a 16MHz external crystal oscillator