Create Key & Certificate for HTTPS Server using IP on Windows Introduction HTTP is a protocol used to enable communication between web browsers and servers. A secure variation of this protocol is HTTPS, which adds encryption to protect data exchanged between the client and the server. This ensures that even if someone intercepts the communication, they cannot understand the transmitted information. In embedded systems and MCU-based applications, libraries such as mbedTLS are commonly used to implement secure communication. These libraries rely on cryptographic keys and digital certificates. For production environments, certificates are typically signed by a Certificate Authority (CA), which guarantees their authenticity and allows web browsers to trust the connection. However, when a certificate is generated manually (self-signed), web browsers do not inherently trust it. Despite this, self-signed certificates are a practical option for internal or development use cases, since the communication remains encrypted. Additionally, it is possible to configure client devices to trust these certificates when required.   Download OpenSSL First, verify whether OpenSSL is installed on your system. If not, it must be downloaded and installed. To check if OpenSSL is already installed, run next line in command prompt: openssl --version If the command is not recognized, OpenSSL is not installed. If OpenSSL is not already installed on your system, you can easily find installation instructions by searching the web for your specific operating system. There are many reliable step‑by‑step guides available for Windows, Linux, and macOS that explain how to download, install, and verify OpenSSL properly. Following an up‑to‑date guide for your OS will help ensure the installation is completed correctly and securely.   Preparation Select a folder where all keys and certificates will be stored. Open a command prompt in this folder and proceed with the following steps.   Create Keys NOTE: Please replace %%Name%% according to your preference. Create a private key for the Server Certificate openssl genrsa -out %%KeyName%%.key 2048 Create a private key to simulate Certificate Authority (CA) openssl genrsa -out %%CAKeyName%%.key 2048 Create Certificate Authority Generate a self-signed CA certificate: openssl req -x509 -new -nodes -key %%CAKeyName%%.key -sha256 -days 3650 -out %%CAName%%.crt Create Server Certificate Config file to request certificate Create a configuration file named %%ConfigFileName%%.cnf using the following template, this can be created with Notepad. [req] default_bits = 2048 prompt = no distinguished_name = dn req_extensions = v3_req [dn] C=%%Country%% ST=%%State%% L=%%City%% O=%%Owner%% OU=%%Division%% CN=%%CommonName%% [v3_req] subjectAltName = @alt_names [alt_names] IP.1 = %%ServerIP%% Generate Certificate Signing Request (CSR) openssl req -new -key %%KeyName%%.key -out %%CertificateRequestName%%.csr -config %%ConfigFileName%%.cnf Sign Certificate with simulated CA openssl x509 -req -in %%CertificateRequestName%%.csr -CA %%CAName%%.crt -CAkey %%CAKeyName%%.key -CAcreateserial -out %%CertificateName%%.crt -days 365 -extensions v3_req -extfile %%ConfigFileName%%.cnf Prepare to use with mbedTLS Convert private Key to DER (Distinguished Encoding Rules) openssl rsa -in %%KeyName%%.key -outform DER -out %%KeyName%%_key.der Convert Certificate to DER (Distinguished Encoding Rules) openssl x509 -in %%CertificateName%%.crt -outform DER -out %%CertificateName%%.der Convert Key DER to array in a source file xxd -i %%KeyName%%_key.der > %%KeyName%%_key.c Convert Certificate DER to array in a source file xxd -i %%CertificateName%%.der > %%CertificateName%%_cert.c Install CA Certificate (Optional – Avoid Browser Warnings) To prevent browser warnings, install the CA certificate on the client device (PC, phone, etc.). Double-click the CA certificate file (.crt). Click Install Certificate. Select Local Machine. Choose Place all certificates in the following store. Click Browse and select Trusted Root Certification Authorities. Click Next → Finish. After this step, the system will trust certificates signed by this CA.

MCUXpresso Config Tools 26.06 Now Available We are pleased to announce that MCUXpresso Config Tools 26.06 are now available. Downloads Also via installer in MCUXpresso for VS Code https://marketplace.visualstudio.com/items?itemName=NXPSemiconductors.mcuxpresso In order to use it with other toolchains, download the installer for all platforms, please login to our download site via:  https://www.nxp.com/mcuxpresso/config Please refer to https://docs.mcuxpresso.nxp.com/config/latest/ for installation and quick start guides. For online version, login into MCUXpresso site: MCUXpresso WEB Release Notes Full details at https://docs.mcuxpresso.nxp.com/config/latest/ Version 26.06 Update for the latest NPI support

Config Tools for i.MX 26.06 Now Available We are pleased to announce that Config Tools for i.MX 26.06 are now available. Downloads & links To download the installer for all platforms, please login to our download site via:  https://www.nxp.com/design/designs/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX Please refer to  Documentation  for installation and quick start guides. For further information about DDR config and validation, please go to this  blog post. Release Notes Full details on the release (features, known issues...) Version 26.06 DDR tool – NXP-validated memory configurations for multiple vendors is available System Manager – extended CLI support for a headless setting

S32K388 GMAC0 lwIP FreeRTOS S32DS36 RTD600 Debug Error Dear 1. The original project was developed based on S32DS3.5 + RTD5.0.0, Build OK & Run OK 2. Development requires basic RTD 6.0.0. Development environment: S32DS 3.6.2 + RTD 6.0.0 + TCPIP_STACK_3.0.0 + FreeRTOS_11.1.0_6.0.0 3. RTD5.0.0 and RTD6.0.0 have significant differences, so projects based on the original RTD5.0.0 cannot be used. Instead, refer to the example code provided in the forum ( Example: S32K388 GMAC0 lwIP FreeRTOS S32DS 3.6.1 RTD600 ). 4. Modify the corresponding PIN according to your hardware platform as follows:          5. Debugging the example code revealed that some initialization steps failed, as follows:    6. If the corresponding code is masked, the program can run, but the PHY address cannot be found. The attached file contains a debug example. I'm not sure if the reference example provided on the forum has been modified, or if I only modified the PIN definition, or if there's some other configuration error.

What kind of port does the T Embed have? I have the standard model T Embed, but i have no Idea what kind of port it has (the other port, not usb c), because the official site says its a grove port, the lilygo Wiki site says its a qwiic port. Can anyone help me please? Boot ROM|Booting | Flash Re: What kind of port does the T Embed have? Hello @papaku , The T‑Embed is not an NXP product, so this may be outside the scope of our support. Thank you for your understanding. BR Celeste

FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 经理： FS32K144UAT0VLLT电路采用5VDC供电，20MHZ外部晶振，匹配电容10pF,外部晶振没有起振，上位机使用SW不能正常连接此芯片。 测量此32K144UA芯片第97脚PTA5（RESET）电平出现三角波，频率1280HZ，幅度3.3Vp-p， 如下图所示，请经理各位老师帮助分析原因，使用LDO电源芯片5V供电正常，晶振为什么没有起振，复位管脚怎么产生三角波，是哪儿虚焊造成，谢谢！ Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 Hi 复位引脚现在接了电容所以变成了三角波，要么先移除电容观察复位引脚波形。 然后参考 S32K1xx系列MCU应用指南之芯片锁死(lockup)复位原因分析与恢复方法详解的 "7. S32K1xx系列MCU芯片锁死(lockup)原因分析及恢复方法"章节内容判断具体什么情况。 复位引脚周期性拉低，程序都没运行起来，晶振无法根据程序里的使能位起振。 不要测之前那片VDD 3.3v供电，但VREFH却5v供电的芯片，建议重新焊接一块芯片然后使用调试器下载程序。 Best Regards, Robin 回复： FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 各位老师： 补充： 上面FS32K144UAT0VLLT复位电路，复位管脚接10K电阻上拉到+5V，同时接100nF电容到GND，谢谢！ Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 复位引脚波形看起来符合 ： ②RESET引脚输出周期性复位脉冲信号 a. 若复位信号周期为~118us，高电平时间为~660ns的方波信号  可以通过SWD/JTAG调试接口执行mass erase命令解密恢复MCU； 建议直接使用该文章百度云盘里那个脚本操作吧。 Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 经理： 复位电路去掉电容后，就是脉冲，如图所示。 1.参考“ 7. S32K1xx系列MCU芯片锁死(lockup)原因分析及恢复方法"，J-llnk总是不能和电脑正常连接，但ST-link可以，但软件不支持； 2. 复位电路不能正常和J-Link连接 ，连接时复位电路需要焊接电容吗？目前复位电路是10k上拉5V，5V供电，100nF接GND，仍然不能连接J-link，需要采取什么措施？ 3. FS32K144UAT0VLLT是新的，已经更换了2片，为什么新的芯片也出现加密情况？ 谢谢！ Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 Robin_Shen: 电路5V供电，复位电路10K上拉电阻到5V，没有接地电容，连接时需要添加接地电容吗？ 在J-Link>输入unlock kinetis命令，电脑回复如下： Unlocking device...ERROR: Read from DP/AP register failed! 1. 复位管脚脉冲波形见下图，周期接近118uS, 2. 整个脉冲的长度时间为1500nS，如果FS32K144工作在5V，复位高电平阈值多大？下图高电平时间是660nS吗？下图高电平合格吗？ 3. 在J-Link>下输入命令截图： （1）在J-Link>下输入connect，回复后输入“？”，使用FS32K144UAT0VLLT选择 S32K144 (ALLOW SECURITY)，对吗？如下图： （2）当输入频率112000KHZ后，出来的没有合适选项，此处应该怎么输入频率？ （3）下面时J-Link下输入Comnnect，unlock Kinetis等命令的回复截图，请经理看看哪儿输入错误，谢谢！ Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 1、2都可以的。 3(1)  开发阶段建议先别选 allow security(微信文章里都有介绍建议仔细看一遍) 3(2) 你的芯片是FS32K144UAT0VLLT，但截图Device为什么选择S32K11系列？我没明白你提到的112000KHZ是什么频率，SWD或者JTAG速率可以选择低一些。 3(3) 你不是说5V供电的么，怎么VTref=3.309V。 请问调试接口是否符合AN5426的“Table 8. S32K1xx - JTAG and SWD interface” 和 “Figure 11. JTAG/SWD signal connections”。或者你把原理图最小电路部分发给我检查一下。 另外注意给S32K144供电的LDO需要满足至少250mA(详细参考ERR052094) Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 Robin_Shen: 老师你好： 1. 在J-Link下输入unlock kinetis命令，回复： 这表示已经解锁成功了吧？ 2. 但是测量PTA5复位管脚，仍然是三角波： 3. 当电路板和上位机下载软件连接时，当打开查看内核时如下图，复位管脚电平才是4V的直线， 一旦关闭下面窗口，复位管脚又变为三角波，这种状态正常吗？ 并且解锁后的芯片，进行SWDIO连接时需要添加复位信号线，不然无法连接，这是为什么？ 谢谢！ Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 1. 是的。然后你需要给芯片下载程序，复位引脚才恢复高电平。  2. 微信文章里有提到：如果Flash中没有代码(比如新芯片，Flash为空)，MCU将由于内核死锁(lockup)不断地周期性复位。   这就是空芯片的复位引脚在接电容情况下观察到三角波、不接电容情况下观察到周期性脉冲的原因。 3. 连接、复位、下载或编程流程中通常会 halt CPU, 一旦 halt住CPU就不会复位了。 但是复位电平怎么会只有4V呢？ 请容我再次向你确认调试接口电路是否正确： S32K1的reset信号需要连接调试器的复位信号。

调用 SDK 闪存 API，但 S32K144 的 D_Flash 中缺少一些数据 大家好： 我在我的项目（S32K144）中调用 SDK flash init API，然后调用 Flash erase 和 Flash write。然后我发现 Flash 中的一些数据变成了 0xFF。然后我尝试在 Flash 初始化和 Flash 擦除/写入之间添加延迟，然后数据就正常了。然后我尝试检查 while (!(FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK)); 而不是使用延迟函数。但它还是失败了。所以，我想知道是否需要延迟一段时间，等待闪存模块在硬件层完成初始化。 BR 洛基

LLCE + PFE CAN2ETHを使用した時の時間デターミニスティック(TAS)トラフィックのベストプラクティス NXPチームの皆様、こんにちは。 私たちは、HPCにコネクテッドされたゾーンコントローラとしてS32G399Aを用いる ゾーンアーキテクチャ に取り組んでいます 現在のアーキテクチャ： 現在、GMACは完全なTime-Aware Shaper(TAS / 802.1Qbv)サポートと完全なTSN機能を備えています。 DDSはこのGMACパス上で動作し、サービス指向トラフィックに関して良好な時間決定性を確保しています。 新たな探査： AN13423で説明された公式のNXP LLCE + PFEサンプルアプリケーション(CAN2ETH / ETH2CAN)を成功裏に立ち上げてテストしました。 目的は、選択された高周波・低遅延CAN信号をLLCE→PFE(IEEE1722 AVTP over UDP)を通じてECUから直接オフロードし、ゾーンコントローラのCPU負荷とレイテンシを削減することです。 コミュニティの議論から、PFEは802.1AS-Rev(時間同期)のみをサポートしており、GMACとは異なりTime-Aware Shaper(802.1Qbv / TAS)やフレームプリエンプションをサポートしていないことが分かっています。 質問／ガイダンス依頼： LLCEはPFEと密接に統合されているため（PFE_HIF3を使用）、このシナリオにおけるNXPの推奨するベストプラクティスは何ですか？ NXPが提供するPFEのソースコードを使ったりカスタマイズしたりすることで、PFEでTASサポートを有効にすることは可能でしょうか?(NXPがPFEのソースコードを提供しているのを見ましたが、これでTAS機能の追加や有効化に役立つでしょうか?) PFEでTASを有効化できない場合、LLCE + PFEトラフィックの強固な時間決定性を実現するためのNXPの推奨ベストプラクティスCAN2ETH何でしょうか? 重要な時間敏感なCAN信号は引き続きGMAC + TAS経路を使い、非クリティカルまたは大量の信号のみがLLCE + PFEを使うべきでしょうか? 推奨される方法は、PFEポートの下流にある外部TSNスイッチ(例えばSJA1110)に依存して、トンネルされたトラフィックの完全なTASスケジューリングを提供することでしょうか? 将来的にPFEでTASサポートを追加する計画やファームウェアアップデートはありますか? GMACとPFEの適切な分岐を決めつつ、セーフティに関わる決定性やハードリアルタイム信号の決定性を損なわないことを望んでいます。 公式なガイダンスやリファレンス・デザイン、構成のおすすめがあれば大変助かります。 お手数ですが、よろしくお願いいたします。 よろしくお願いいたします。 アルサル・イマーム SDVアーキテクト @ GK Automobiltechnologie (Disrupt) ゴールドVIP Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH こんにちは、アルサリマム ご連絡と詳細な情報提供をありがとうございました。 ご質問を拝受いたしました。確認のお手伝いをさせていただきます。 BR ジョーイ

A triangular waveform level was observed at pin 97 (PTA5) of the FS32K144UAT0VLLT (RESET). manager: The FS32K144UAT0VLLT circuit uses a 5VDC power supply, a 20MHz external crystal oscillator, and a 10pF matching capacitor. The external crystal oscillator does not start oscillating, and the host computer cannot connect to this chip normally using SW. Measuring the PTA5 (RESET) level at pin 97 of this 32K144UA chip revealed a triangular wave with a frequency of 1280Hz and an amplitude of 3.3Vp-p. As shown in the image below, please help me analyze the cause. The LDO power supply chip is working normally with 5V, so why is the crystal oscillator not oscillating? How can the reset pin generate a triangular wave? Where is the poor soldering causing this? Thank you! Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 Hi The reset pin is currently connected to a capacitor, causing it to display a triangular wave. You can either remove the capacitor first and observe the reset pin waveform, or refer to section 7, " Analysis of Causes and Recovery Methods for Lockup Resets in S32K1xx Series MCUs," in the S32K1xx Series MCU Application Guide to determine the specific situation. The reset pin is periodically pulled low, and the program does not start running, so the crystal oscillator cannot start oscillating according to the enable bit in the program. Do not test the chip that was previously powered by VDD 3.3V but VREFH is powered by 5V. It is recommended to resolder a chip and then use a debugger to download the program. Best Regards, Robin 回复： FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 Dear teachers: Replenish: The reset circuit for the FS32K144UAT0VLLT above has a 10K resistor connected to the reset pin to pull it up to +5V, and a 100nF capacitor connected to GND. Thank you! Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 The reset pin waveform appears to match: ② The RESET pin outputs a periodic reset pulse signal. a. If the reset signal period is ~118µs and the high-level time is ~660ns, it is a square wave signal. The MCU can be decrypted and recovered by executing the mass erase command through the SWD/JTAG debug interface. I suggest using the script in the Baidu Cloud Drive link provided in this article. Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 manager: After removing the capacitor from the reset circuit, it generates a pulse, as shown in the figure. 1. Referring to " 7. Analysis and Recovery Methods for Lockup of S32K1xx Series MCU Chips", J-llnk cannot connect to the computer normally, but ST-link can, but the software does not support it; 2. The reset circuit cannot connect to the J-Link properly. Does the reset circuit need to be soldered with a capacitor during connection? Currently, the reset circuit has a 10k pull-up to 5V, a 5V power supply, and a 100nF capacitor connected to GND, but it still cannot connect to the J-Link. What measures should be taken? 3. The FS32K144UAT0VLLT is new, and two have already been replaced. Why is the encryption issue occurring even with the new chip? Thanks! Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 Robin_Shen: The circuit is powered by 5V, and the reset circuit has a 10K pull-up resistor to 5V. There is no grounding capacitor. Is it necessary to add a grounding capacitor when connecting? After entering the command "unlock kinetis" in J-Link, the computer responded as follows: Unlocking device...ERROR: Read from DP/AP register failed! 1. The reset pin pulse waveform is shown in the figure below, with a period of approximately 118µs. 2. The entire pulse duration is 1500 ns. If the FS32K144 operates at 5V, what is the high-level reset threshold? Is the high-level duration in the diagram below 660 ns? Is the high-level duration in the diagram below acceptable? 3. Enter the command under J-Link> and take a screenshot: (1) Enter "connect" under J-Link>, and enter "?" in the reply. Select S32K144 (ALLOW SECURITY) using FS32K144UAT0VLLT, is that correct? See the figure below: (2) When the frequency is 112000KHZ, no suitable options appear. How should the frequency be entered here? (3) Below are screenshots of the responses when entering commands such as Command and Unlock Kinetis in J-Link. Please check where the input is incorrect, thank you! Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 Either 1 or 2 is fine. 3(1) During the development phase, it is recommended not to select "allow security" (this is explained in WeChat articles, so please read them carefully). 3(2) Your chip is FS32K144UAT0VLLT, but why did you choose the S32K11 series for the Device in the screenshot? I don't understand what frequency 112000KHZ you mentioned is. You can choose a lower SWD or JTAG rate. 3(3) Didn't you say it's powered by 5V? How come VTref=3.309V? Please tell me if the debugging interface conforms to AN5426's "Table 8. S32K1xx - JTAG and SWD interface" and "Figure 11". "JTAG/SWD signal connections". Or you can send me the minimum circuit part of the schematic for me to check. Also note that the LDO powering the S32K144 needs to provide at least 250mA (see ERR052094 for details). Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 Robin_Shen: Hello teacher: 1. Enter the command "unlock kinetis" in J-Link, and the response will be: This means it has been successfully unlocked, right? 2. However, measuring the PTA5 reset pin still yields a triangular wave: 3. When the circuit board and the host computer download software are connected, as shown in the image below when viewing the kernel, the reset pin level should be a straight 4V line. Once the window below is closed, the reset pin changes to a triangular wave again. Is this normal? Furthermore, after the chip is unlocked, a reset signal line needs to be added when making SWDIO connections, otherwise the connection cannot be made. Why is this? Thanks! Re: FS32K144UAT0VLLT第97脚PTA5（RESET）出现三角波电平 1. Yes. Then you need to download the program to the chip so that the reset pin returns to a high level. 2. The WeChat article mentions that if there is no code in the Flash memory (e.g., in a new chip where the Flash is empty), the MCU will continuously reset periodically due to a core lockup . This explains why a triangular wave is observed on the reset pin of an empty chip when a capacitor is connected, and periodic pulses are observed when no capacitor is connected. 3. During the connection, reset, download, or programming process, the CPU is usually halted. Once halted, the CPU will not reset. However, why is the reset level only 4V? Please allow me to confirm again whether the debugging interface circuit is correct: The S32K1's reset signal needs to be connected to the debugger's reset signal.

S32k388 ブートROM リファレンスマニュアルにはBoot ROMについて言及がありますが、それ以上の情報はありません。 RMは、32KBのブートROMが5つ利用可能であるとだけ述べています。 ブートROMが重要になるのはどの時点か。sbafが実行される前にHSEによってここから実行されるファームウェアはありますか？

FRDM-i.MX95 EVK の Ubuntu インストール ガイド (Ubuntu 22.04/24.04) こんにちは、 現在 FRDM-i.MX95 EVK を使っていて、このプラットフォームで Ubuntu(22.04または24.04) を動かしたいと考えています。 i.MX8MPにUbuntuをインストールするための以下のガイドを見つけました： https://community.nxp.com/t5/i-MX-Processors/How-to-install-ubuntu-on-imx8mp/td-p/1744295 私の質問は以下のとおりです。 このi.MX8MPガイドで説明されている手順をFRDM-i.MX95 EVKで使ってもいいですか? i.MX95向けに公式にサポートされているUbuntuイメージやBSPはありますか？ もし直接互換性がない場合、i.MX95でUbuntuを動かす際に推奨される方法は何でしょうか? (例:Yocto + Ubuntu rootfs、またはプリビルドイメージなど) ブートローダー、カーネル、デバイスツリー、GPU/NPUのサポートなど、既知の制限や違いはありますか? i.MX95上でUbuntuを動作させるためのガイダンスや参考資料があれば、ぜひ教えていただきたいです。 事前に感謝いたします。 よろしくお願いします、 ジャック Re: Ubuntu installation guide for FRDM-i.MX95 EVK (Ubuntu 22.04/24.04) こんにちは、 @JK-IMXさん。 Ubuntu OSのサポートは終了しました。現在、私たちはDebian OSをサポートしています。Debianシステムに関する情報については、下記のリンクを参照してください。 https://www.nxp.com/design/design-center/software/embedded-software/linux-software-and-development-tools/nxp-debian-linux-sdk-distribution-for-i-mx-and-layerscape:NXPDEBIAN BR

SDKのフラッシュAPIと、欠けているデータD_Flash呼び出S32K144 チームの皆さん、こんにちは。 プロジェクト(S32K144)でSDKのflash init APIを呼び出し、その後Flash消去とFlash書き込みを呼び出します。その後、フラッシュメモリ内の一部のデータが0xFFになっていることに気づきました。そこで、フラッシュ初期化とフラッシュ消去/書き込みの間に遅延時間を追加してみたところ、データが正常になりました。そして、遅延関数を使用する代わりに、while (!(FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK)); をチェックしてみます。しかし、それでも失敗に終わった。SO、ハードウェア層でフラッシュモジュールの初期化が完了するまで待つ時間を少し遅らせなければならないのかもしれません。 BR ロキー

S32K388 GMAC0 lwIP FreeRTOS S32DS36 RTD600 Debug Error Dear     1、原来的工程基于S32DS3.5 + RTD5.0.0开发，Build Ok & Run OK     2、基于开发需要必须基本RTD6.0.0开发，开发环境：S32DS3.6.2 + RTD6.0.0 + TCPIP_STACK_3.0.0 + FreeRTOS_11.1.0_6.0.0    3、RTD5.0.0与RTD6.0.0变化较大，不能使用原RTD5.0.0的工程，只好参考论坛提供的例程(示例 S32K388 GMAC0 lwIP FreeRTOS S32DS 3.6.1 RTD600)    4、根据自己硬件平台修改相应PIN如下:           5、Debug 例程，发现部分初始化过不去，如下：    6、如果把相应代码Mask掉，虽然程序可以Run，但是PHY Address都找不到 附件是Debug的例程，不清楚是不是论坛提供的参考例程存在修改之处，是不是我仅仅修改PIN定义，是不是始终之类配置错误？

S32k388 Boot ROM There is mention of Boot ROM in the reference manual, but no further information is available. RM just says five instances of 32kb boot rom is available  At what point boot rom becomes relevant. Is there a firmware that run from here by the HSE even before sbaf is ran 

S32K388 GMAC0 lwIP FreeRTOS S32DS36 RTD600 デバッグエラー 親愛なる 1. 元のプロジェクトは S32DS3.5 + RTD5.0.0 ビルドに基づいて開発されました。OK & 実行OK 2. 開発には基本RTD 6.0.0が必要です。開発環境：S32DS 3.6.2 + RTD 6.0.0 + TCPIP_STACK_3.0.0 + FreeRTOS_11.1.0_6.0.0 3. RTD5.0.0とRTD6.0.0には大きな違いがあるため、元のRTD5.0.0に基づいたプロジェクトは使用できません。代わりに、フォーラムで提供されているサンプルコードを参照してください（例：S32K388 GMAC0 lwIP FreeRTOS S32DS 3.6.1 RTD600 ）。 4. ハードウェアプラットフォームに応じて、対応するPINを以下のように変更してください。          5. サンプルコードのデバッグを行った結果、以下のような初期化手順の一部が失敗していることが判明しました。    6. 対応するコードがマスクされている場合、プログラムは実行できますが、PHYアドレスを見つけることはできません。 添付ファイルにはデバッグ用の例が含まれています。フォーラムで提供されている参照例が変更されているのか、私がPIN定義だけを変更したのか、あるいは他の設定エラーがあるのかが分かりません。

Ubuntu installation guide for FRDM-i.MX95 EVK (Ubuntu 22.04/24.04) Hello, I am currently working with the FRDM-i.MX95 EVK and would like to run Ubuntu (22.04 or 24.04) on this platform. I found the following guide for installing Ubuntu on the i.MX8MP: https://community.nxp.com/t5/i-MX-Processors/How-to-install-ubuntu-on-imx8mp/td-p/1744295 My questions are: Can I follow the same procedure described in this i.MX8MP guide for the FRDM-i.MX95 EVK? Are there any officially supported Ubuntu images or BSPs available for i.MX95? If not directly compatible, what would be the recommended approach to run Ubuntu on i.MX95? (e.g., Yocto + Ubuntu rootfs, or any prebuilt images) Are there any known limitations or differences (e.g., bootloader, kernel, device tree, GPU/NPU support) that I should be aware of? I would really appreciate any guidance or references for running Ubuntu on i.MX95. Thank you in advance. Best regards, Jack Re: Ubuntu installation guide for FRDM-i.MX95 EVK (Ubuntu 22.04/24.04) Hi @JK-IMX  We no longer support Ubuntu OS.  We now support Debian OS. Please refer to the link below for information about the Debian system. https://www.nxp.com/design/design-center/software/embedded-software/linux-software-and-development-tools/nxp-debian-linux-sdk-distribution-for-i-mx-and-layerscape:NXPDEBIAN B.R

FRDM-i.MX95 EVK 的 Ubuntu 安装指南 (Ubuntu 22.04/24.04) 你好， 我目前正在使用FRDM-i.MX95 EVK ，并且想在这个平台上运行Ubuntu（22.04 或 24.04） 。 我找到了以下关于在 i.MX8MP 上安装 Ubuntu 的指南： https://community.nxp.com/t5/i-MX-Processors/How-to-install-ubuntu-on-imx8mp/td-p/1744295 我的问题是： 我可以按照 i.MX8MP 指南中描述的步骤来操作 FRDM-i.MX95 EVK 吗？ 是否有官方支持的适用于 i.MX95 的 Ubuntu 镜像或 BSP？ 如果不能直接兼容，那么在 i.MX95 上运行 Ubuntu 的推荐方法是什么？ （例如，Yocto + Ubuntu rootfs，或任何预构建的映像） 是否存在我应该注意的已知限制或差异（例如，引导加载程序、内核、设备树、GPU/NPU 支持）？ 我非常感谢您能提供任何关于在 i.MX95 上运行 Ubuntu 的指导或参考资料。 提前谢谢您。 此致， 杰克 Re: Ubuntu installation guide for FRDM-i.MX95 EVK (Ubuntu 22.04/24.04) 你好@JK-IMX 我们已停止对Ubuntu操作系统的支持。我们现在支持 Debian 操作系统。有关 Debian 系统的信息，请参阅以下链接。 https://www.nxp.com/design/design-center/software/embedded-software/linux-software-and-development-tools/nxp-debian-linux-sdk-distribution-for-i-mx-and-layerscape:NXPDEBIAN BR

T Embedにはどのようなポートがありますか？ 標準モデルのTエンベッドを持っていますが、どのポートか全く分かりません(もう一つのポートで、USB-Cではありません)。公式サイトではGroveポートと書いてあり、LilygoのWikiサイトではQwiicポートと書かれています。どなたか助けていただけませんか? ブートROM|ブート|フラッシュ Re: What kind of port does the T Embed have? こんにちは、 @papaku さん、 T-EmbedはNXP製品ではないため、当社のサポート範囲外かもしれません。ご理解いただきありがとうございます。 BR セレステ

Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH Hello NXP Team, We are working on a zonal architecture using S32G399A as Zone Controllers connected to HPC Current Architecture: We are currently using the GMAC with full Time-Aware Shaper (TAS / 802.1Qbv) support along with complete TSN features. DDS runs over this GMAC path, and we have good time determinism for our service-oriented traffic. New Exploration: We have successfully brought up and tested the official NXP LLCE + PFE sample application (CAN2ETH / ETH2CAN) as described in AN13423. The goal is to offload selected high-frequency / low-latency CAN signals from ECUs directly via LLCE → PFE (IEEE1722 AVTP over UDP) to reduce CPU load and latency on the Zone Controller. From community discussions, we understand that PFE only supports 802.1AS-Rev (time synchronization) and does not support Time-Aware Shaper (802.1Qbv / TAS) or Frame Preemption, unlike GMAC. Question / Request for Guidance: Since LLCE is tightly integrated with PFE (using PFE_HIF3), what is NXP’s recommended best practice in this scenario? Can we enable TAS support on PFE by using / customizing the PFE source code provided by NXP? (I saw that NXP provides PFE source code – would this help us add or enable TAS functionality?) If TAS cannot be enabled on PFE, what is NXP’s recommended best practice to achieve strong time determinism for the LLCE + PFE CAN2ETH traffic? Should critical time-sensitive CAN signals continue to use the GMAC + TAS path, while only non-critical or high-volume signals use LLCE + PFE? Is the recommended approach to rely on an external TSN switch (such as SJA1110) downstream of the PFE port to provide full TAS scheduling for the tunneled traffic? Are there any plans or firmware updates that will add TAS support on PFE in the future? We want to decide the right split between GMAC and PFE paths without compromising determinism for safety-relevant or hard real-time signals. Any official guidance, reference designs, or configuration recommendations would be very helpful. Thank you in advance! Best regards, Arsal Imam SDV Architect @ GK Automobiltechnologie (Disrupt) GoldVIP Re: Best practice for time-deterministic (TAS) traffic when using LLCE + PFE CAN2ETH Hi,arsalimam Thank you for your contacting and detail information. I have received your questions and will help you to check it. BR Joey

Call SDK flash API and some data in D_Flash missing of S32K144 Hi team:  I call SDK flash init API in my project (S32K144), and then call Flash erase and Flash write. Then I find some data in Flash became to 0xFF. Then I try to add a Delay between Flash init and flash Erase/Write, and then the data is normal. And then I try to check while (!(FTFC->FSTAT & FTFC_FSTAT_CCIF_MASK)); instead of using delay function. But it still failed. So, I wonder if it has to delay some time to wait for the flash module to complete initialization on hardware layer. BR Loky