Building AI/ML Devices at the Edge? Start with FRDM From smart sensing and anomaly detection to computer vision, voice recognition, and multimodal GenAI—AI/ML use cases are rapidly moving onto the device. But if you're an engineer getting started, the real questions usually are: What hardware products should I use? What NXP tools actually work for embedded AI applications? Do I need the cloud for anything? Let’s break it down ! Why Edge AI is important? Running AI models directly on-device enables: Real-time decisions (low latency) Better security Offline operation (no cloud dependency) Optimized power consumption That’s exactly where the FRDM development platform comes in Quick Positioning: From MCU to Edge AI Processor Category Boards AI Capability Level Typical Use Case MCU (Low Power Edge ML) FRDM-MCXA156 + ⭐ sensor AI, TinyML MCU + Neural Acceleration FRDM-MCXN947 ++ ⭐⭐ Edge AI with vision/audio, TinyML Application Processor (Entry Edge AI) FRDM-IMX93 +++ ⭐⭐⭐ HMI + AI inference High-Performance Edge AI FRDM-IMX8MPLUS ++++ ⭐⭐⭐⭐ Vision AI, Advanced HMI Next-Gen AI + Safety FRDM-IMX95 / PRO +++++ ⭐⭐⭐⭐⭐ Gen AI, Advanced Edge Computing AI/ML applications can run on general-purpose hardware, but leveraging dedicated hardware acceleration significantly improves performance, enables faster results, and reduces power consumption. Below is a reference list of FRDM development boards that support AI/ML applications, helping you choose the right platform based on your target use case   Board Positioning AI Acceleration Hardware Capabilities (AI-relevant) Best For FRDM-MCXA156 Entry-level MCU (TinyML)  No NPU (CPU-only) Sensors via Expansion headers (Arduino, MikroBUS, Pmod) Parallel display support Sensor ML Anomaly detection Basic TinyML FRDM-MCXN947 MCU with neural acceleration NPU Parallel camera interface (basic) Parallel display Audio (PDM/I2S) Voice AI  Low-res vision Object classification Anomaly Detection FRDM-IMX93 Entry Edge AI MPU NPU  MIPI CSI camera Display (MIPI DSI/LVDS) Audio + connectivity Smart HMI Light vision AI Edge gateways FRDM-IMX8MPLUS Advanced Multimedia + Edge AI platform NPU Multi-camera (MIPI CSI) High-res display (HDMI/DSI)  Audio DSP Connectivity (Wi-Fi, BLE, Ethernet) Some PCIe expansion Computer vision Object detection Industrial AI FRDM-IMX95 Next-gen AI + real-time MPU Next-gen NPU + heterogeneous compute Multi-camera pipelines Advanced HMI Industrial connectivity M.2 expansion(Up to 1 AI accelerators) Robotics Industrial AI Safety applications FRDM-IMX95-PRO Full-featured AI dev platform High-performance NPU + scalable AI (Ara240 Discrete NPU)  Multi-camera Advanced display M.2 expansion (Up to 2 AI accelerators) Advanced AI prototyping Gen AI Edge servers Edge computing  Software and tools for ML/AI applications   GoPoint GoPoint accelerates AI/ML evaluation on FRDM platforms powered by i.MX application processors by providing a ready-to-use, graphical environment with pre-integrated demos. Developers can quickly run applications such as image classification, object detection, and voice recognition directly on the hardware without complex setup. These demos are already optimized for available compute resources—including CPU, GPU, DSP, and NPU—allowing users to immediately visualize performance and understand how AI workloads map to the system. This makes GoPoint an ideal starting point for exploring edge AI capabilities and validating use cases before moving into full application development. Application Code Hub (ACH) Application Code Hub complements rapid evaluation tools by offering a centralized repository of reusable, production-oriented software examples for FRDM boards. It provides full application projects, source code, and documentation that developers can directly import into MCUXpresso IDE or VS Code. With filtering based on use case—such as vision AI, audio processing, or anomaly detection, ACH enables developers to quickly find and customize reference implementations. This helps bridge the gap between proof-of-concept and real product development, significantly reducing development time while enabling scalable AI/ML application design. Application Code Hub Guide eIQ Time Series Studio (TSS) eIQ Time Series Studio is purpose-built for developing AI models based on sensor and time-series data, making it highly relevant for FRDM-based edge intelligence applications. It provides a guided workflow for data collection, labeling, model training, and validation, all optimized for MCU-class devices. Developers can easily transform raw sensor data—such as vibration, motion, or environmental signals—into deployable machine learning models for use cases like predictive maintenance, anomaly detection, and condition monitoring. With built-in analytics and seamless deployment to FRDM boards, TSS simplifies the path from data to intelligent behavior on the edge. eIQ AI/ML Software Environment The eIQ software environment is the foundation that enables AI/ML development across the entire FRDM ecosystem, providing an end-to-end workflow from model creation to on-device inference. It supports importing and optimizing models from popular frameworks such as TensorFlow, PyTorch, and ONNX, and integrates tightly with MCUXpresso and Linux-based environments. eIQ includes tools for model optimization—such as quantization and pruning—as well as runtime engines designed for efficient execution on CPUs, DSPs, and NPUs. By combining these capabilities with hardware acceleration available on FRDM boards, eIQ allows developers to build, deploy, and run real-time AI applications directly on embedded devices with minimal reliance on cloud computing. eIQ Training Curriculum FQA What is an NPU ? A Neural Processing Unit (NPU) in the FRDM platform is a dedicated hardware accelerator integrated into certain microcontrollers (such as the MCX-N family) that is specifically designed to execute machine learning and neural network workloads efficiently. Unlike general-purpose CPUs, the NPU is optimized for the mathematical operations used in AI models, enabling significantly faster inference—up to tens of times higher throughput—while consuming less power. In FRDM boards, the NPU works alongside the CPU and DSP to offload complex AI computations, allowing real-time processing for applications such as image recognition, voice detection, and sensor-based anomaly detection directly on the device. Combined with NXP’s eIQ® software environment, the NPU becomes the core execution engine that transforms FRDM platforms into efficient, low-power edge AI systems capable of running intelligent applications without relying on the cloud What is a Discrete NPU? A Discrete Neural Processing Unit (DNPU) is a standalone AI accelerator designed specifically to execute machine learning and neural network workloads efficiently. Unlike integrated NPUs that are built into a processor, a DNPU exists as a separate chip or module that can be added to a system. It offloads compute-intensive AI operations, such as matrix multiplications and deep learning inference from the main CPU or GPU, delivering significantly higher performance and better energy efficiency. This makes DNPUs ideal for advanced edge AI applications like computer vision, generative AI, and real-time multimodal processing. How do I use Ara modules (DNPU) with FRDM boards? Ara modules, based on NXP’s DNPU technology, can be used with compatible FRDM boards to extend AI processing capabilities. On supported i.MX-based FRDM platforms such as FRDM-IMX95 or FRDM-IMX95-PRO—developers can connect Ara modules (e.g., Ara240) through the M.2 expansion interface. Once connected, the Ara module works alongside the main processor to offload complex AI workloads, enabling faster inference, lower latency, and improved power efficiency. Using the eIQ® AI software environment, developers can prototype and validate models on FRDM, then scale performance by enabling Ara acceleration, creating a seamless path from development to high-performance edge AI deployment. From TinyML to advanced edge AI and GenAI, discover how to build intelligent systems directly on-device with FRDM, no cloud dependency required. FRDM-IMX8 FRDM-IMX8MP FRDM-IMX9 FRDM-MCXN i.MX Application Processors MCU

Vision AI/ML with i.MX RT700 The i.MX RT700 microcontroller family includes an eIQ Neutron N3-64 NPU for accelerating neural network models. The i.MX RT700 EVK can be combined with a camera and LCD screen to showcase running TinyML vision models on a microcontroller.  i.MX RT700 Camera Hardware Setup: The following hardware is used: i.MX RT700 EVK RK055HDMIPI4MA0 LCD panel Camera Options: USB Camera with USB A to micro-B converter OV7670 parallel camera (with optional wide-angle lens) The USB camera should be attached to the i.MX RT700 EVK on USB OTG port J40. The parallel camera interface is available on J53 and uses FlexIO with eDMA to read in the camera data. AN14836 describes the details. Note that the links in that app note for the demo software do not work but the demo code is in the process of being posted on NXP’s Application Code Hub.  When inserting the parallel camera align it to the left most side, as shown in the image below: Directions for attaching the LCD panel to the J52 connector on the underside of the i.MX RT700 EVK can be found on this Community post.  Note that there are multiple names used for the LCD panel and all these part numbers refer to the exact same panel: RK055HDMIPI4MA0 RK055MHD091 RK055MHD091-CTG RK055MHD091A0-CTG i.MX RT700 Vision ML Examples: There are two vision AI/ML examples for i.MX RT700 available today: Object Detection (part of AN14718) Hand Gesture Recognition Both of these examples use a USB camera.  i.MX RT700 Vision MPP Examples:  The Media Processing Pipeline (MPP) interference examples in i.MX RT700 MCUXpresso SDK 26.06 and later support both parallel and USB camera interfaces. These SDK examples are only available for command line GCC and VS Code MCUXpresso SDK layouts. They are not available for MCUXpresso IDE, IAR, or Keil.  A parallel camera is used by default in the RT700 MPP projects. A USB camera can be enabled by adding a USE_USB_CAMERA declaration in the project's CMakeLists.txt file by adding the following macro: mcux_add_macro(     CC "-DUSE_USB_CAMERA"     CX "-DUSE_USB_CAMERA" )

U-Boot Falconモードを使用してi.MX 8QXPを高速で起動する この記事では、U-Boot Falconモードを使用して、i.MX 8QXPの起動時間を短縮する方法について説明しています。一般的な手法はAN14093で紹介されています。この記事の内容は、LF-6.6.23-2.0.0 BSPでテストされました。 手順 1. i.MX Yoctoプロジェクトのユーザーガイドの記載ステップに従って、Yoctoのビルド環境を準備します。ここでは、BSPが~/imx-yocto-bspディレクトリにあり、ビルド・ディレクトリは~/imx-yocto-bsp/buildであると想定します。 2. 添付のアーカイブを~/imx-yocto-bsp/sourcesに解凍します。これにより~/imx-yocto-bsp/sources/meta-imx-fastbootディレクトリが作成されます。 3. 次のコマンドを使用して、meta-imx-fastbootレイヤをビルドに追加します。 bitbake-layers add-layer ~/imx-yocto-bsp/sources/meta-imx-fastboot 4. 同じツリーでイメージを以前にビルドしたことがある場合は、次のコマンドを使用してu-boot-imxとimx-bootパッケージをクリーンアップします。 bitbake -c clean u-boot-imx imx-boot 5. 新しいイメージをビルドします。このパッケージはすぐに使用できるようにcore-image-minimal向けに構成されています。他のイメージへの応用方法を以下でご紹介します。 bitbake core-image-minimal 6. 結果のイメージを好みの方法でeMMC/SDに書き込み、ボードを起動します。 7. デフォルトでは、ボードは通常通り起動します。高速起動を有効にするには、U-Bootでボードを停止し、次のコマンドを実行してください。 u-boot => run prepare_fdt 8. ボードを再起動します。この段階から、ボードは高速モードで起動するはずです。起動中にカーネルまたはsystemdによって出力されるメッセージは大幅に減少します。カーネルから不要な機能を削除したり、systemdによって開始された不要なサービスを削除したりすることで、起動時間はさらに最適化可能です。詳細は、AN14093を参照してください。 9. U-Bootに再度入る場合は、ボードの電源をオンにしたときに、シリアル・コンソールで「c」キーを長押しします。電源をオンにする前やリセット・ボタンを押す前に「c」キーを押し続けると最も簡単です。 仕組み 追加したレイヤには、U-Boot、ATF、imx-mkimageのパッチが含まれているほか、core-image-minimalレシピを変更します。 U-Bootでは、Falconモードに必要なオプションが「imx8qxp_mek_falcon_defconfig」という名前の新しい構成ファイルと、spl_start_uboot()関数の実装が追加されます。 ATFでは、デバイス・ツリーのロード・アドレスが正しいパラメータに追加されます。 mkimageでは、kernel-atf-container.img（ブート・パーティションにデプロイ）とuImage（rootfsにデプロイ）の2つのターゲットが新たに作成されます。 core-image-minimalレシピの変更により、新しいファイルが生成されたイメージに確実にコピーされます。 別のイメージをビルドする場合は、そのイメージに適した名前を付けた新しいファイルにcore-image-minimal.bbappendの内容をコピーする必要があります。たとえば、imx-image-fullをビルドする場合は、次のコマンドを使用できます。 cp ~/imx-yocto-bsp/sources/meta-imx-fastboot/recipes-fsl/images/core-image-minimal.bbappend ~/imx-yocto-bsp/sources/meta-imx-fastboot/recipes-fsl/images/imx-image-full.bbappend *** 免責事項 *** NXPが提供するあらゆるサポート、情報、テクノロジー（以下「資料」）は、明示的または黙示的を問わず、いかなる保証もなく現状のまま提供され、NXPは、適用法で認められる最大限の範囲で、資料に関連する直接的および間接的な責任および損害を一切否認します。 NXPは、アプリケーションまたは製品設計に関するいかなる支援についても責任を負いません。資料は、NXP製品に関連してのみ使用できます。 NXPは資料に関して提供されたフィードバックを制限なく使用できます。 i.MX 8ファミリ | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Yocto Project

基于 U-Boot Falcon 模式的 i.MX 8QXP 快速启动 本文旨在展示如何利用 U-Boot Falcon 模式缩短 i.MX 8QXP 的启动时间。通用技术方案详见 AN14093 应用笔记。本文测试基于 LF-6.6.23-2.0.0 BSP 版本。 如何做 1. 按照《i.MX Yocto 项目用户指南》搭建 Yocto 编译环境。假设 BSP 位于 ~/imx-yocto-bsp 目录，构建目录为 ~/imx-yocto-bsp/build。 2. 将附件压缩包解压至 ~/imx-yocto-bsp/sources 目录，将自动创建 ~/imx-yocto-bsp/sources/meta-imx-fastboot 子目录。 3. 通过以下命令添加 meta-imx-fastboot 层到构建系统： bitbake-layers add-layer ~/imx-yocto-bsp/sources/meta-imx-fastboot 4. 若此前已在相同目录树构建过镜像，请使用以下命令清理 u-boot-imx 和 imx-boot 软件包： bitbake -c clean u-boot-imx imx-boot 5. 构建新镜像。本软件包默认配置为 core-image-minimal。下文将演示如何适配其他镜像类型： bitbake core-image-minimal 6. 使用您偏好的方法将生成的映像写入 eMMC/SD 并启动电路板。 7. 默认情况下，电路板将正常启动。要启用快速启动，请在 U-Boot 中停止电路板，然后运行以下命令： u-boot => run prepare_fdt 8. 重启开发板此后开发板将进入快速启动模式。内核和 systemd 在启动过程中输出的信息将大幅减少。您可以通过移除内核中不必要的功能和禁用 systemd 启动的非必要服务，进一步优化启动时间。具体优化方法请参阅AN14093。 9. 如需重新进入 U-Boot 模式，在开发板通电启动时，持续按住串口控制台的 'c' 键。最简单的操作方式是，在通电/按下复位键前就按住 'c' 键并保持。 工作原理 我们添加的层包含 U-Boot、ATF 和 imx-mkimage 的补丁。此外，它修改了 core-image-minimal 配方。 在 U-Boot 中，新增配置文件 imx8qxp_mek_falcon_defconfig 实现 Falcon 模式所需选项，同时新增 spl_start_uboot() 函数实现。 AFT 在对应参数中添加了设备树加载地址。 在 mkimage 中，创建了两个新的目标：kernel-atf-container.img（部署到 boot 分区）和uImage（部署到 rootfs）。 core-image-minimal 配方文件的修改确保新文件被正确复制到最终镜像。 如需构建其他镜像类型，需将 core-image-minimal.bbappend 内容复制到新建文件中，并按目标镜像命名。例如构建 imx-image-full 时，可使用如下命令： cp ~/imx-yocto-bsp/sources/meta-imx-fastboot/recipes-fsl/images/core-image-minimal.bbappend ~/imx-yocto-bsp/sources/meta-imx-fastboot/recipes-fsl/images/imx-image-full.bbappend *** 免责声明 *** NXP 提供的任何支持、信息和技术（“材料”）均按“现状”提供，不附带任何明示或暗示的保证， NXP 在适用法律允许的最大范围内，免除与材料相关的所有直接或间接责任及损害赔偿。 NXP 不对任何应用程序或产品设计方面的协助承担任何责任。材料仅可用于与 NXP 产品相关的用途。 您向 NXP 提供的任何关于材料的反馈均可由 NXP 无限制地使用。 i.MX 8 系列 | i.MX 8QuadMax (8QM) | 8QuadPlus Linux Yocto Project

Fast Boot for i.MX 8QXP Using U-Boot Falcon Mode The layer attached to this article is obsolete. Please use the meta-imx-fastboot GitHub repo instead. The purpose of this article is to show how to reduce the boot time on i.MX 8QXP using U-Boot Falcon Mode. The general technique is presented in the AN14093. This article was tested on LF-6.6.23-2.0.0 BSP. How to do it 1. Follow the steps in the i.MX Yocto Project User's Guide and prepare your Yocto building environment. We will further assume that the BSP is in the ~/imx-yocto-bsp directory and the build directory is ~/imx-yocto-bsp/build. 2. Unpack the attached archive in ~/imx-yocto-bsp/sources. This should create the ~/imx-yocto-bsp/sources/meta-imx-fastboot directory.  3. Add the meta-imx-fastboot layer to your build using the following command: bitbake-layers add-layer ~/imx-yocto-bsp/sources/meta-imx-fastboot 4. If you've previously built an image in the same tree, clean the u-boot-imx and imx-boot packages using the following command: bitbake -c clean u-boot-imx imx-boot 5. Build the new image. Out of the box, this package is configured for core-image-minimal. We will show you below how to adapt it for other images: bitbake core-image-minimal 6. Write the resulted image on eMMC/SD using your preferred method and boot the board. 7. By default, the board will boot normally. To enable fast boot, stop the board in U-Boot, and run the following command: u-boot => run prepare_fdt 8. Reboot the board. From this point on, the board should boot in fast mode. Far less messages will be printed by the kernel or systemd during boot. You may further optimize the boot time by removing unnecessary features from the kernel and/or removing unnecessary services started by systemd. Please refer to AN14093. 9. If you ever want to re-enter U-Boot, please keep the 'c' key pressed in the serial console during board power-on. It's easiest if you press and keep the 'c' key pressed before powering on/pressing the reset button. How it works The layer we've added contains patches for U-Boot, ATF and imx-mkimage. In addition, it modifies the core-image-minimal recipe. In U-Boot, the necessary options for Falcon Mode are added in a new configuration file, named imx8qxp_mek_falcon_defconfig, as well as an implementation of the spl_start_uboot() function. In ATF, the device tree load address is added in the correct parameter. In mkimage, two new targets are created: kernel-atf-container.img (to be deployed in the boot partition) and uImage (to be deployed in the rootfs). The change in the core-image-minimal recipe ensures that the new files are copied in the resulting image. If you want to build a different image, you need to copy the content of core-image-minimal.bbappend in a new file, named according to the image you want to build. For example, if you want to build imx-image-full, you could use the following command: cp ~/imx-yocto-bsp/sources/meta-imx-fastboot/recipes-fsl/images/core-image-minimal.bbappend ~/imx-yocto-bsp/sources/meta-imx-fastboot/recipes-fsl/images/imx-image-full.bbappend *** DISCLAIMER *** Any support, information, and technology (“Materials”) provided by NXP are provided AS IS, without any warranty express or implied, and NXP disclaims all direct and indirect liability and damages in connection with the Material to the maximum extent permitted by the applicable law. NXP accepts no liability for any assistance with applications or product design. Materials may only be used in connection with NXP products. Any feedback provided to NXP regarding the Materials may be used by NXP without restriction.

Developing a Dual-Motor EV Control System with Model-Based Design Toolbox 1 Table of Contents • Introduction • Overview • Context • References • Conclusion 2 Introduction This article series presents the Motor Control System (MCS) within an electric vehicle (EV) architecture. It introduces the end-to-end development flow, from controller and plant modeling to simulation, code generation, hardware deployment, and integration with the rest of the vehicle network. This opening article establishes the technical foundation for a series focused on the architecture, implementation, and integration of a dual-motor control system for EV traction applications. The series also shows how MathWorks tools can be used together with NXP software and hardware to support a Model-Based Design workflow. This approach helps engineers develop, verify, and deploy motor control applications more efficiently while maintaining traceability across the development cycle. Figure 1-1. Role of the Motor Control System within the EV traction domain 3 Overview 2.1. What will this series of articles cover? The articles in this series define the development roadmap for the Motor Control System within a broader EV architecture. The series covers the following topics: Software and Hardware Environment - Overview of the MathWorks and NXP tools used to develop, test, and validate a dual-motor control system. Architecture and Model Description - Description of the model architecture, signal interfaces, and core control algorithms implemented in the Motor Control System. Model-in-the-Loop Development - Simulation of the controller and plant in Simulink to validate algorithms before code generation. Software-in-the-Loop Validation - Code generation for the validated controller and comparison of the generated software against the Model-in-the-Loop baseline. Processor-in-the-Loop Validation - Execution of the controller on NXP hardware while the plant remains simulated on the host system. Deployment and Validation on Real Hardware - Integration with physical hardware, scaling from single-motor to dual-motor operation, and configuration of the NXP MCU peripherals required for motor control. CAN Integration - Definition of the CAN communication interface, including database design and integration on the target NXP platform. Results and System Validation - Presentation of the final implementation results and validation of the complete system behavior. 2.2. What is the Motor Control System? Electric vehicles depend on traction systems that deliver efficient propulsion, accurate torque control, and safe operation. At the center of this functionality is the Motor Control System (MCS), which combines real-time control software, power electronics, sensing, actuation, and communication interfaces into a tightly coordinated embedded system. Figure 2-1. PMSM motor and controller as core elements of the traction system In modern EVs, the traction system delivers the torque and power needed to propel the vehicle. It is typically composed of the following elements: Electric motor - converts electrical energy from the battery into mechanical power at the wheels. Inverter system - converts DC energy from the battery into the controlled AC waveforms required by the motor. Transmission system - transfers the generated torque from the motor to the wheels. At its core, the Motor Control System regulates motor torque, speed, and position by controlling the voltage and current applied to the motor phases. A typical MCS includes the following functional layers: Control Algorithm - implements torque and current control strategies such as Field-Oriented Control (FOC). Sensing and Feedback - measures motor currents, voltages, rotor position, and temperature. Power Electronics - inverter circuitry that switches DC power into AC waveforms for motor drive. Embedded Processor - microcontroller executing real-time control loops. Communication Interfaces - CAN, LIN, or Ethernet for integration with other system modules. Together, these layers form a closed-loop control system that operates at high switching frequencies and under strict real-time constraints. Figure 2-2. Field-Oriented Control (FOC) architecture EV traction systems can be implemented using different architectures depending on the required balance of efficiency, performance, cost, and system complexity. A single-motor architecture uses one traction motor to drive either the front or rear axle. This approach reduces hardware complexity and cost, and it often improves vehicle range because of lower mass and lower overall energy consumption. A dual-motor architecture uses two independent traction machines that can be arranged in several drivetrain topologies. This configuration enables higher total power, better traction, improved vehicle dynamics, and stronger acceleration. The tradeoff is increased electrical and mechanical complexity, together with higher system cost. Figure 2-3. Example dual-motor traction architecture Advantages & Disadvantages of Dual Motor: Acceleration faster due to torque from both motors Superior traction and handling, especially in snow, rain or off-road conditions Slightly lower range due to increased weight and power consumption More expensive but can include AWD and performance benefits Advantages & Disadvantages of Single Motor: Slightly better range due to less energy consumption More affordable Moderate traction, suitable for most road conditions Slower acceleration Note: The example used throughout this series is based on a dual-motor rear-axle architecture, where each rear wheel is driven by its own motor. 2.3. Target Audience This series is intended for engineers and technical stakeholders involved in the development, integration, and evaluation of electric drive systems, including the following audiences: Embedded Software Engineers Motor Control & Power Electronics Engineers System Architects & Vehicle Architecture Engineers Hardware Engineers Model-Based Design and Simulink Developers Academic and Research Communities 4 Context In the electric vehicle architecture presented in this series, the Motor Control System is located in the rear zone of the vehicle. Each rear wheel is driven by an independent Permanent Magnet Synchronous Motor (PMSM). The Motor Control System ECU coordinates both motors and exchanges real-time data with the rest of the vehicle over the CAN network. Figure 3-1. Motor Control System highlighted within the EV architecture The traction ECU is built around NXP's S32K396 microcontroller, which supports both single 6-phase motor control and dual 3-phase motor configurations. The inverter stage is driven by the MC33937 pre-driver, which provides three high-side and three low-side FET pre-drivers for automotive motor control applications. Note: The inverter receives DC power from the vehicle battery, while battery operation and safety are supervised by the Battery Management System. The Motor Control System communicates over CAN with the Zone Node controller, which in turn exchanges commands and status information with the main vehicle control node responsible for speed and torque requests. 5 References PMSM Control Workshop BLDC Control Workshop A Model-Based Design (MBDT) Environment for Motor Control Algorithm Development Deploy Motor Control Algorithms on NXP S32K3 from Simulink Motor Control Rapid Prototyping on NXP S32M2 with MathWorks and Model-Based Design Toolbox Next Generation of NXP EV Traction Inverter with S32K39 MCU and FS26 SBC AN14326: 3-phase Motor Control Kit with S32K396 Application Note AN13884: 3-phase Sensorless PMSM Motor Control Kit with S32K344 using RTD AUTOSAR API Application Note Advancing Motor Control Performance with Digital Twins Extended Range Dual-Motor Electric Vehicle Model 6 Conclusion This article introduced the Motor Control System within an EV architecture and established the technical context for the rest of the series. It explained the role of the Motor Control System, compared single-motor and dual-motor traction topologies, and outlined how a Model-Based Design workflow can be applied using MathWorks tools together with NXP software and hardware. The next article will focus on the software and hardware environment required to develop, simulate, and deploy the Motor Control System using MathWorks and NXP solutions.

Vehicle Lighting Control Course Using NXP FRDM-A-S32K3 Automotive Platforms 1. Introduction This article demonstrates how to get started with the Vehicle Lighting Control for Daylight and Hazard Signals application using the FRDM-A-S32K312 or FRDM-A-S32K344 evaluation board and Application Code Hub (ACH). The example showcases a simplified automotive lighting system where various vehicle lights—such as headlights, hazards, turn indicators, and brake lights—are controlled based on user input conditions, while providing real-time visual feedback through LEDs. This demo highlights how embedded peripherals can be used to implement automotive body control features on the S32K3 platform. FRDM-A-S32K344FRDM-A-S32K344 FRDM-A-S32K312FRDM-A-S32K312   2.1 Software Required S32K3 FRDM Automotive Board Installation Package FreeMASTER Run-Time Debugging Tool Automotive Math and Motor Control Library (AMMCLib) Rev 1.1.44 2.2 Hardware Required FRDM-A-S32K344 board/FRDM-A-S32K312 board Personal computer USB Type-C cable (power + debug) FRDM-K64 Click Shield Analog Key Click module 4x4 RGB Click module   3. System Architecture The application implements a simplified automotive lighting control workflow, demonstrating how user inputs, embedded processing, and lighting outputs interact in real time. The RGB Click has the following LED mapping: The system operates as follows: The user interacts with the Analog Key Click module, where each button (T1–T6) generates a distinct analog signal corresponding to a specific lighting function. The ADC peripheral continuously samples the analog input and converts it into digital values. The application decodes the input and identifies which button has been pressed. Based on the detected input, the system executes the associated lighting function: T1 – Low Beam Headlights Activates LEDs 13, 14 in warm white Used for standard night driving illumination Turning OFF low beam automatically disables high beam Must be ON before high beam can be activated T2 – High Beam Headlights Activates LEDs 8, 9, 10, 11 in cool white Provides enhanced long-range visibility Can only be enabled if low beam is already ON Remains active during turn signal blinking T3 – Left Turn Signal Controls LEDs 0, 12 in blinking amber Generates continuous left indicator signal Operates independently of other lighting functions T4 – Right Turn Signal Controls LEDs 3, 15 in blinking amber Generates continuous right indicator signal Operates independently of other lighting functions T5 – Brake Lights Activates LEDs 1, 2, 5, 6 in red Simulates braking condition Fully independent of other systems T6 – Hazard Lights Activates LEDs 0, 3, 12, 15 in blinking amber Synchronizes left and right turn signals (all blink together) High beam state is preserved and restored between blinking cycles The application processes logic constraints (e.g., dependency between low beam and high beam). The FlexIO peripheral updates the output signals accordingly to drive the LEDs.  The 4x4 RGB Click LEDs provide real-time visual feedback of the current lighting state. This workflow models a simplified automotive Body Control Module (BCM) behavior, showing how multiple lighting functions, dependencies, and independent subsystems are coordinated within a real-time embedded system. 4. Open a Demo from ACH (Application Code Hub) Open S32 Design Studio 3.6.5, select Import Project from Application Code Hub This will open a new Window: Click on Search window and enter "Lighting"   Select the desired project for your FRDM board. Click on GitHub link — this will trigger S32 Design Studio IDE to automatically retrieve project attributes, then click Next>. Select main branch and then click Next>. Select your local path for the repo in Destination->Directory window. The S32 Design Studio IDE will clone the repo into this path, click Next>. Select Import existing Eclipse projects then click Next>. Select the project in this repo (only one project in this repo) then click Finish. In Project Explorer, right-click the project and select Update Code and Build Project: This will generate the configuration (Pins, Clocks, Peripherals), update the source code and build the project using the active configuration (e.g.  Debug_FLASH ). Make sure the build completes successfully and the  *.elf  file is generated without errors. Go to Debug and select Debug Configurations. There will be a debug configuration for this project: Select the desired debug configuration and click on Debug.  Now the perspective will change to the Debug Perspective. Use the controls to control the program flow. 5. Results FRDM-A-S32K312FRDM-A-S32K312 FRDM-A-S32K344FRDM-A-S32K344 6. Educational value This course can be used as: Eat-Sleep-Code-Repeat University laboratory material Automotive embedded systems training S32K3 hands-on workshop content Introduction to automotive safety-related software Application Code Hub learning path Students gain practical experience with ADC acquisition, signal processing, real-time decision making, and peripheral control using real automotive hardware. Conclusion This demo demonstrates how a complete vehicle lighting control system can be prototyped on the NXP S32K3 platform using FRDM-A-S32K312or FRDM-A-S32K344 board. By combining analog input acquisition, real-time processing, and multi-channel LED control, the example provides a practical introduction to automotive lighting system design. Through the implementation of multiple lighting functions—such as low beam, high beam, turn signals, brake lights, and hazard lights, including their dependencies and constraints—the application illustrates how real-world Body Control Module (BCM) logic can be modeled in an embedded environment. Developers can use this example to understand how user inputs, peripheral drivers (ADC, FlexIO), and application-level logic interact to control complex lighting behaviors, offering a solid foundation for building scalable and safety-aware automotive applications on modern microcontrollers. References https://mcuxpresso.nxp.com/appcodehub?search=dm-vehicle-lighting-signals-frdm-a-s32k312 https://mcuxpresso.nxp.com/appcodehub?search=dm-vehicle-lighting-signals-frdm-a-s32k344 

PN7642 - Basic RF power limitation using DPC RF power regulation is a critical factor in the development of NFC devices, as it directly influences performance, reliability, and compliance with industry standards. There are three main reasons for this:  If the PN7642 VUP current exceeds the limit given by the product Data sheet, the PN7642 can be damaged. If too high RF power is radiated from the antenna, there exists a risk for NFC Cards. Too high RF power might lead to exceeding a given RF limit (NFC Forum, ISO, EMVCo). NXP provides comprehensive documentation on Dynamic Power Control for the PN7642 and PN5190. Designers are expected to adhere to these guidelines, especially when aiming for compliance with standards such as EMVCo. PN5190 Dynamic Power Control Quick Calibration and TxShaping Demo Automatic DPC Calibration for PN7642 and PN5190 However, if the user's design is intended for infrastructure applications, such as a smart lock. At a minimum, Dynamic Power Control (DPC) should be enabled to serve as a current limiter. The evaluation can be done with the help of NFC Cockpit.  1// Start DPC Calibration  "Press" Start DPC Calibration  "Press" Load protocol  Make sure that the DPC is "Enabled" 2// Adjust current reduction table  Set all entries to "0" Write into EEPROM 3// Set the "Target" current Use approx. the same current as "TxLDO Values"  The limit may be set higher, e.g., to 300 mA, if the purpose is solely to provide overcurrent protection for the IC. Save to EEPROM Restart the board (Close port -> Press VEN->Open port)   4// Check the power regulation  Start DPC Calibration  Place a card or any metal object in the antenna's proximity  Observe VDDPA and "TxLDO" current  The current should stay around the given target  The VDDPA will drop once the antenna is loaded  5// Set a minimum VDDPA in DPC  In the case that the current is still too high, a user can define a minimum VDDPA that is used for the DPC regulation. By default, this value is set to 2.2V. The user can decrease it up to 1.5V.  In that case, NXP also recommends disabling the RDOn control.  Note: The User has to consider the "DPC_TXLDO_MAX_DROPOUT" parameter, which defines the maximum voltage drop on TXLDO. By default, it is set to 3.6 V. That means if the user wants to use the minimum VDDPA 1.5 V, then the maximum TXLDO input shall not exceed 5.1 V. This feature protects the TXLDO from overheating.  Once the evaluation is done, the customer shall program the following EEPROM entries in their application. For more info, see PN7642 Product Data sheet.  DPC_CONFIG (Address: 0x0068) -> example: enabled -> 0x01 DPC_TARGET_CURRENT (Address: 0x0069) -> example: 229 mA -> 0xE5 DPC_TXLDO_MAX_DROPOUT (Addresses: 0x0073 - 0x0074) -> example: 3.6 V -> 0x10,0x0E DPC_TXLDOVDDPALow (Address: 0x006F) -> example: 1.5 V -> 0x00 DPC_HYSTERESIS_LOADING (Address: 0x006B) -> example: 20 mA -> 0x14 DPC_HYSTERESIS_UNLOADING (Address: 0x006E) -> example: 10 mA - 0x0A DPC lookup table entries (Addresses: 0x007D - 0x0125) -> example: for current limitation only -> all 0x00 If a user does not want to use a maximum range of VDDPA during DPC (5.7V), e.g., their system uses a 3.3V supply domain. Then, the maximum VDDPA in DPC can be limited by the following EEPROM settings:  TXLDO_VDDPA_MAX_RDR (Address: 0x0007)-> example: 3.0 V -> 0x0F Note: TXLDO has approx. 0.3V voltage drop. Always set this parameter 0.3V lower. Once this is done, the user has to check the "TxLDO" current and adjust the target current accordingly. In this case, to approximately 150 mA. If you don´t change it, the DPC starts to limit the power around 229 mA, as has been set in a previous step.  NFC Controller Solutions

PN7642 - ULPCD evaluation in NFC Cockpit This article describes how to evaluate ULPCD feature together with PN7642 EVK (OM27642EVK) and NFC Cockpit.  1// Disable DC-DC in EEPROM  OM27642EVK does not required any HW changes for ULPCD (**). User is only required to change the following settings in EEPROM  (disable DC-DC converter). Address: 0x0000 (Secure_Lib_Config) Value: 0x21  Reset the board after writing the value.  **Note: To ensure an accurate and reliable ULPCD evaluation—particularly for ULPCD current measurements. We strongly recommend implementing the following hardware modifications on the OM27642EVK. Note: New revision of the board already have R4=DNP, R8=0Ω. Kindly check this on your board. 2//Set required ULPCD settings in EEPROM  ULPCD VDDPA -> Typically 1.5V. If the HF attenuator is 0x00, increase e.g. to 1.8 Since the detection range does not significantly depend on the power level, there is no need to set VDDPA above 2 V. Higher VDDPA results in increased current consumption in ULPCD, but does not significantly improve detection performance. RF On Guard time -> This value can be reduced to the minimum -> 5.2 us RSSI Guard time -> Recommended value is 25 RSSI Threshold -> Typically 4~6 Number of RSSI samples -> Typically -> 0 (4 rounds) 3// Perform "Reads HF Attenuator"  Once the required ULPCD settings is set (Guard times, Threshold....). Then User has to perform "Reads HF Attenuator". Make sure that the "HF Attenuator" option is checked.  As written above, the value must not be 0x00. If so, increase VDDPA. 4// Perform ULPCD Calibration and check RSSI Value  For OM27642EVK, the RSSI value for unloaded antenna is typically around 1400dec - 1600dec. 5//Enter ULPCD mode  User can enter the ULPCD mode. The board will again be connected once the load change is detected (e.g. NFC card or smartphone in the antenna proximity). 6// Typical detection performance for 65 mm x 65 mm Antenna tuned to 35Ω. MIFARE DESFire EV3: Class 1 Antenna  ICODE SLIX: Class 1 Antenna  ICODE 3: Class 6 Antenna  NFC Controller Solutions

Difference in ADC noise between BCTU Control Mode and Trigger Mode Hello, I am working on an application using the [S32k322] where I use the eMIOS timer to trigger the BCTU every 100 µs to read analog data. I am observing a strange behavior between the two BCTU modes: Control Mode: When the ADC CTU mode is set to Control Mode, the ADC conversions are completely stable. The data read via FreeMASTER is clean and free of noise or glitches. Trigger Mode: When I switch the ADC CTU mode to Trigger Mode (keeping the 100 µs eMIOS trigger identical), the sampled analog data becomes noisy and exhibits noticeable glitches in FreeMASTER. Are there specific architectural configurations, timing constraints, or register settings (such as trigger delays, FIFO configurations, or clock synchronization) required for Trigger Mode to prevent this noise? Thank you for your help. Output with ADC ctu mode : Trigger Mode output with ADC ctu mode : Control Mode Re: Difference in ADC noise between BCTU Control Mode and Trigger Mode Hi@Stark_ could you please share the test project and i will test it on myside. Re: Difference in ADC noise between BCTU Control Mode and Trigger Mode Hi @Senlent ,    Thanks for the response. My ADC clock is 160MHz, and I've attached my ADC configuration and register values below. Clock ADC Configuration Output with ADC ctu mode : Trigger Mode output with ADC ctu mode : Control Mode Re: Difference in ADC noise between BCTU Control Mode and Trigger Mode Hi@Stark_ Based on the configuration screenshot you provided, there are some configuration issues, specifically the division ratios for the module clock and calibration clock. The ADC clock configuration must strictly follow the table below. please change it and test  again, Re: Difference in ADC noise between BCTU Control Mode and Trigger Mode Hi @Senlent  I have attached test code. is it possible to work on BCTU and normal conversion for the some selected channels (ADC_Instance0 and ADC_Instance1)? Re: Difference in ADC noise between BCTU Control Mode and Trigger Mode Hi @Senlent  " yes, it is possible to work on BCTU and normal conversion." is there any example code for reference? " Also, your program still doesn't modify the ADC module clock and calibration clock divider. Below are my test results; I connected the port externally to GND. You can see there isn't a significant difference. " could you please share the modified test project and i will test it on myside. Re: Difference in ADC noise between BCTU Control Mode and Trigger Mode Hi@Stark_ I don't have a demo like that; the attached file is a modified project. Re: Difference in ADC noise between BCTU Control Mode and Trigger Mode Hi@Stark_ yes, it is possible to work on BCTU and normal conversion. I tested the program you provided and made some modifications. Your external clock is 25MHz, while mine is 16MHz. Also, your program still doesn't modify the ADC module clock and calibration clock divider. Below are my test results; I connected the port externally to VDD（my typing error）. You can see there isn't a significant difference.

找不到 FRDM MCX A266 的引脚配置工具 找不到现场引脚配置工具。 FRDM 培训 Re: Can't find pin configuration tool for FRDM MCX A266 你好， 如果您是该工具的初学者，以下信息或许对您有所帮助。 MCUXpresso 配置工具的快速入门指南 MCUXpresso 配置工具用户指南（IDE） 如果您需要查找某些信息或工具，与我们联系。 此致敬礼，路易斯 Re: Can't find pin configuration tool for FRDM MCX A266 找到https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-config-tools-pins-clocks-and-peripherals:MCUXpresso-Config-Tools

S32G399A-RDB3 QNX PFE 驱动程序问题 问候， 我们尝试在搭载 QNX 的 S32G399A-RDB3 板上运行 PFE。据我所知，这是一个有效的组合： BSP 37.0 PFE-FW_S32G_1.7.0 PFE-DRV-S32G_A53_QNX_1.4.0 最后所有网络接口都出现无载波错误。将网线插入不同的以太网端口没有任何变化。 它以前可以用 gmac0。 您有什么想法吗？ io 包调用： io-pkt-v6-hc -p tcpip -d pfe-2 pfe0_mac=000a0b0c0d66,pfe1_mac=001a1b1c1d66,pfe2_mac=002a2b2c2d66,class_fw=/proc/boot/s32g_pfe_class.fw,no_reset,mode0=sgmii,phy0=0,mode1=sgmii,phy1=1 Uboot参数： Uboot 与 Linux sdcard 镜像中的 Uboot 相同，只是修改了 qnx 启动的参数。 setenv hwconfig "pcie0:mode=rc,clock=ext;pcie1:mode=sgmii,clock=ext,fmhz=125,xpcs_mode=2G5" setenv pfeng_mode 'enable,sgmii,sgmii,rgmii' 设置环境变量 s32cc_gmac_mode 为禁用 setenv pfeng enable; s32ccgmac disable; s32ccgmac enable; setenv boot_qnx_atf 'mmc dev 0; fatload mmc 0:1 0x83e00000 s32g399a-rdb3.dtb;pfeng 启用；s32ccgmac 禁用；s32ccgmac 启用；fatload mmc 0:1 0x80080000 ifs-s32g399a-rdb.ui；bootm 0x80080000 - 0x83E00000' setenv bootcmd 'run boot_qnx_atf' 保存环境 日志： U-Boot 2020.04+g156b168010（2023年6月9日 10:14:25 +0000）   CPU：NXP S32G399A rev.1.1 型号：NXP S32G399A-RDB3 动态随机存取存储器(DRAM)：3.5 GiB MMC：FSL_SDHC：0 从MMC加载环境... 成功 将 PCIe0 配置为根复合体 PCIe0：连接失败 PCI：自动配置失败，第 1c 条 输入：serial@401c8000 输出：serial@401c8000 错误：serial@401c8000 板修订：RDB3 修订版 F 网络：EQOS phy：rgmii @ 1   警告：eth_eqos (eth0) 使用随机 MAC 地址 - 26:e4:e6:43:15:ad eth0：eth_eqos 无法获取 emac1_xpcs 的 XPCS 速度 PFE：emac0：sgmii emac1：sgmii emac2：rgmii ，eth1：eth_pfeng 按任意键停止自动启动：3 2 1 0 切换到分区 #0，确定 mmc0 is current device 读取50640字节耗时17毫秒（2.8 MiB/s） 读取了 11948752 字节，耗时 540 毫秒（21.1 MiB/s） ## 从位于 80080000 的传统映像启动内核... 图片名称： 镜像类型：AArch64 Linux 内核镜像（未压缩） 数据大小：11948688 字节 = 11.4MiB 加载地址：80080000 入口点：80080000 校验和验证中... 成功 ## 位于 83e00000 的扁平化设备树 blob 使用位于 0x83e00000 的 fdt blob 启动 正在加载内核映像 使用位于 0000000083e00000 的设备树，结束于 0000000083e0f5cf 修复：pfe0 设置为 00:01:be:be:ef:11 修复：pfe1 设置为 00:01:be:be:ef:22 修复：pfe1：将物理地址更新为 0x8 修复：pfe2 设置为 00:01:be:be:ef:33   正在启动内核...   在 EVB/RDB 上为 PFE 驱动程序保留 RAM 区域 完成。 ClockCycles 示例： 0 43600679 1 43600679 2 43600678 3 43600679 4 43600678 5 43600678 6 43600678 7 43600679 所有时钟周期偏移均在容差范围内 欢迎使用 QNX Neutrino 7.1.0在 NXP S32G399A RDB 板上！ 启动监督机制…… 正在启动串口驱动程序... 正在启动网络驱动程序（/dev/socket）...   进程 4107 (ifconfig) 退出状态=0。   进程 10 (sh) 退出状态=0。   进程 9 (dhclient) 退出状态=0。 cp：无法打开源文件。（/proc/boot/libfci_cli）   进程 20489 (cp) 退出状态=1。 正在启动 SPI 驱动程序（/dev/spi0,1,2,3,4,5）... 正在启动 I2C 0/1/2/3/4 驱动程序 (/dev/i2c0,1,2,3,4)... 正在启动 USDHC0 存储卡驱动程序... [00] SIM="SDMMC" HBA="imx" [00,0,0] type=00 ver=05 resp=00 SDMMC:   进程 24596 (chkqnx6fs) 退出状态=0。   进程 28692 (mount) 退出状态=0。 正在启动QSPI Flash驱动程序... 启动 USB 主机驱动程序 (/dev/usb/*) 检测到 QSPI Flash：Macronix MX25UW512，JEDEC 0xC2 - 0x813A，容量：0x4000000 正在为 /dev/usb/* 启动 devb-umass ... # 进程 36891（睡眠）退出状态=0。 sh: /var/cetitec2/startup.sh:没有这样的文件或目录   进程 45081 (sh) 终止 signo=0 code=0 由进程 0 value=0。 slog2info   1月1日 00:00:00.023随机.4low* 0 qcrypto：正在加载配置文件“/etc/qcrypto.conf”[qcrypto_common.c(190)] 1月1日 00:00:00.024random.4..0 slog* 700 Random 使用的是 Fortuna 伪随机数生成器 1月1日 00:00:00.031随机.4low 0 qcrypto: 'openssl' 插件已加载 [qcrypto_plugins.c(354)] 1月1日 00:00:00.031random.4..0 slog 700 选择计时器作为熵源 1月1日 00:00:00.032random.4..0 slog 700 已注册路径名 1月1日 00:00:00.032random.4..0 slog 700 random: 开始 resmgr 1月1日 00:00:00.032random.4..0 slog 700 random：进程已守护化 1月1日 00:00:00.042devc_serlinflexd.7slog* 0 serlinflexd_interrupt_attach: 连接到中断 114 1月1日 00:00:00.047iopkt.8主缓冲区* 0 TCP/IP 开始 1月1日 00:00:00.047iopkt.8main_buffer 0 smmu 支持已禁用 1月1日 00:00:00.049iopkt.8main_buffer 0 正在初始化 IPsec... 1月1日 00:00:00.049iopkt.8主缓冲区 0 完成   1月1日 00:00:00.049iopkt.8main_buffer 0 IPsec：已初始化网络安全关联处理。   1月1日 00:00:00.051iopkt.8main_buffer 0 devnp-pfe-2.so pfe0_mac=000a0b0c0d66,pfe1_mac=001a1b1c1d66,pfe2_mac=002a2b2c2d66,class_fw=/proc/boot/s32g_pfe_class.fw,pfe0_mode=sgmii,pfe0_phy=0,pfe1_mode=sgmii,pfe1_phy=1 1月1日 00:00:00.052io_pkt_v6_hc.8slog* 0 INF[src/pfe_drv.c:1377]:版本信息 驱动程序版本：1.4.0 驱动程序提交哈希值：2f3265a49ac18f94ba5e48254c8f870fe7bfc511 PFE_CFG_MULTI_INSTANCE_SUPPORT: 0 PFE_CFG_LOCAL_IF：6 PFE_CFG_MASTER_IF：6 PFE_CFG_SC_HIF：1 PFE_CFG_HIF_RING_LENGTH: 256 PFE_CFG_PFE0_PROMISC: 1 PFE_CFG_PFE1_PROMISC: 1 PFE_CFG_PFE2_PROMISC: 1     1月1日 00:00:00.052io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1384]:--- 安全中断已启用。不允许使用 InterruptAttach() 或 InterruptAttach_r()。   1月1日 00:00:00.052io_pkt_v6_hc.8slog 0 INF[src/pfe_fw.c:83]:读取 42792 字节   1月1日 00:00:00.053io_pkt_v6_hc.8slog 0 INF[src/pfe_fw.c:89]:已加载固件文件：/proc/boot/s32g_pfe_class.fw   1月1日 00:00:00.053io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1477]:未找到 pfe0/EMAC0 的 MII 模式配置。使用 SGMII。   1月1日 00:00:00.053io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1477]:未找到 pfe1/EMAC1 的 MII 模式配置。使用 SGMII。   1月1日 00:00:00.053io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1477]:未找到 pfe2/EMAC2 的 MII 模式配置。使用 RGMII。   1月1日 00:00:00.053io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1495]:发出 PFE 外设 RESET 指令...   1月1日 00:00:00.274io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1496]:PFE RESET OK.   1月1日 00:00:00.274io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:3519]:PFE CBUS p0x46000000 映射到 v0x38f2e23000   1月1日 00:00:00.274io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:3524]:硬件版本 0x101   1月1日 00:00:00.274io_pkt_v6_hc.8slog 0 INF[src/pfe_hw_feature.c:95]: Silicon S32G3   1月1日 00:00:00.274io_pkt_v6_hc.8slog 0 WRN[hw/s32g/pfe_platform_master.c:3536]:故障停止模式已禁用   1月1日 00:00:00.275io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2687]:PFE_ERRORS：已创建 Parity 实例   1月1日 00:00:00.275io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2702]:PFE_ERRORS：已创建监视程序实例   1月1日 00:00:00.275io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2718]:PFE_ERRORS：总线错误实例已创建   1月1日 00:00:00.275io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2731]:PFE_ERRORS：FW 故障停止实例已创建   1月1日 00:00:00.275io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2744]:PFE_ERRORS：主机故障停止实例已创建   1月1日 00:00:00.275io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2757]:PFE_ERRORS：已创建故障停止实例   1月1日 00:00:00.275io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2770]:PFE_ERRORS：ECC 错误实例已创建   1月1日 00:00:00.275io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:1766]:BMU1 缓冲区基址：p0xc0000000   1月1日 00:00:00.277io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:1810]:BMU2 缓冲区基址：p0x83000000（0x200000 字节）   1月1日 00:00:00.279io_pkt_v6_hc.8slog 0 INF[src/oal_irq_qnx.c:117]:PFE BMU IRQ 工作进程已启动（IRQ ID：226）   1月1日 00:00:00.279io_pkt_v6_hc.8slog 0 WRN[hw/s32g/pfe_platform_master.c:2194]:选项“g2_ordered_class_writes”已禁用。   1月1日 00:00:00.279io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_bmu_csr.c:96]: BMU_EMPTY_INT (BMU @ p0x88000)。泳池已准备就绪。   1月1日 00:00:00.279io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_bmu_csr.c:96]: BMU_EMPTY_INT (BMU @ p0x8c000)。泳池已准备就绪。   1月1日 00:00:00.281io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2239]:固件 .elf检测到   1月1日 00:00:00.281io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2248]:正在上传 CLASS 固件   1月1日 00:00:00.281io_pkt_v6_hc.8slog 0 INF[src/pfe_pe.c:609]:选择固件加载操作，并行加载 8 个 PE。   1月1日 00:00:00.285io_pkt_v6_hc.8slog 0 INF[src/pfe_pe.c:1945]:pfe_ct.h文件版本“92367c0e25f21f49217a9b08168ad2c8”   1月1日 00:00:00.288io_pkt_v6_hc.8slog 0 INF[src/pfe_pe.c:2422]:[固件版本] 1.7.0构建版本：2023年6月2日 13:48:57 (nogitaaa)，ID：0x31454650   1月1日 00:00:00.406io_pkt_v6_hc.8slog 0 WRN[hw/s32g/pfe_platform_master.c:2312]:VLAN ID 不正确或未设置。使用默认 VLAN ID = 0x01。   1月1日 00:00:00.406io_pkt_v6_hc.8slog 0 WRN[hw/s32g/pfe_platform_master.c:2318]:VLAN统计信息大小不正确或未设置。使用默认 VLAN 统计信息大小 = 20。   1月1日 00:00:00.406io_pkt_v6_hc.8slog 0 INF[src/pfe_l2br.c:1181]:软件 VLAN 哈希表 @ p0x20001228     1月1日 00:00:00.406io_pkt_v6_hc.8slog 0 INF[src/pfe_l2br.c:1286]:备用桥接功能域 @ 0x20000a7c（类）   1月1日 00:00:00.406io_pkt_v6_hc.8slog 0 INF[src/pfe_l2br.c:1287]:默认桥接功能域 @ 0x20000a74（类）   1月1日 00:00:00.406io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2412]:路由表已创建，哈希表位于 p0x80014000，池位于 p0x8001c000（65536 字节）   1月1日 00:00:00.407io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_chnl.c:1997]: 初始化 RX 缓冲池。深度：256；缓冲区大小：2048；缓存行大小：64   1月1日 00:00:00.408io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_chnl.c:1997]: 初始化 RX 缓冲池。深度：256；缓冲区大小：2048；缓存行大小：64   1月1日 00:00:00.409io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_chnl.c:1997]: 初始化 RX 缓冲池。深度：256；缓冲区大小：2048；缓存行大小：64   1月1日 00:00:00.508io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:3705]:功能错误 err051211_workaround：已禁用   1月1日 00:00:00.509iopkt.8主缓冲区 0 pfe0   1月1日 00:00:00.509io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2152]:pfe0：使用 PHY 模式：MDIO=0，ADDR=0，CLAUSE=0，RESET=0   1月1日 00:00:00.509io_pkt_v6_hc.8slog 0 INF[src/oal_irq_qnx.c:117]:PFE HIF0 IRQ 工作进程已启动（IRQ ID：222）   1月1日 00:00:00.509io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1795]:将 00:0a:0b:0c:0d:66 添加到 pfe0   1月1日 00:00:00.511iopkt.8主缓冲区 0 pfe1   1月1日 00:00:00.511io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2298]:未找到 pfe0 的速度/双工配置。使用 1 Gbps/全双工。   1月1日 00:00:00.511io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:336]: 尝试注册 HIF 客户端：0   1月1日 00:00:00.511io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF 驱动程序已启动   1月1日 00:00:00.511io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2363]:新PFE设备：0，ID：0   1月1日 00:00:00.511io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2152]:pfe1：使用 PHY 模式：MDIO=1，ADDR=0，CLAUSE=0，RESET=0   1月1日 00:00:00.511io_pkt_v6_hc.8slog 0 INF[src/oal_irq_qnx.c:117]:PFE HIF1 IRQ 工作进程已启动（IRQ ID：223）   1月1日 00:00:00.511io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1795]:将 00:1a:1b:1c:1d:66 添加到 pfe1   1月1日 00:00:00.513iopkt.8主缓冲区 0 pfe2   1月1日 00:00:00.513io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2298]:未找到 pfe1 的速度/双工配置。使用 1 Gbps/全双工。   1月1日 00:00:00.513io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:336]: 尝试注册 HIF 客户端：1   1月1日 00:00:00.513io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF 驱动程序已启动   1月1日 00:00:00.513io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2363]:新的PFE设备：1，ID：2   1月1日 00:00:00.513io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2145]:pfe2：使用静态 PHY 模式，RESET=0   1月1日 00:00:00.513io_pkt_v6_hc.8slog 0 INF[src/oal_irq_qnx.c:117]:PFE HIF2 IRQ 工作进程已启动（IRQ ID：224）   1月1日 00:00:00.513io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1795]:将 00:2a:2b:2c:2d:66 添加到 pfe2   1月1日 00:00:00.515io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2298]:未找到 pfe2 的速度/双工配置。使用 1 Gbps/全双工。   1月1日 00:00:00.515io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:336]: 尝试注册 HIF 客户端：2   1月1日 00:00:00.515io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF 驱动程序已启动   1月1日 00:00:00.515io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2363]:新型PFE设备：2，ID：4   1月1日 00:00:00.530io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2702]:将 00:0a:0b:0c:0d:66 添加到 pfe0   1月1日 00:00:00.530io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2707]:无法将 MAC 地址 00:0a:0b:0c:0d:66 分配给 pfe0   1月1日 00:00:00.530io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式   1月1日 00:00:00.538io_pkt_v6_hc.8slog 0 INF[src/pfe_mdio.c:427]：pfe0：未找到总线 0 地址 0 上的 PHY。切换到静态模式。   1月1日 00:00:00.538io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2829]:目前不支持 SGMII 的 EMAC 速度更改。   1月1日 00:00:00.538io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0   1月1日 00:00:00.540io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式   1月1日 00:00:00.540io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:00:00:00:01 添加到 emac0   1月1日 00:00:00.542io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0   1月1日 00:00:00.542io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:ff:0c:0d:66 添加到 emac0: 17   1月1日 00:00:00.542io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式   1月1日 00:00:00.542io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:00:00:00:01 添加到 emac0   1月1日 00:00:00.542io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:00:00:00:01 添加到 emac0: 17   1月1日 00:00:00.542io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0   1月1日 00:00:00.542io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:ff:0c:0d:66 添加到 emac0: 17   1月1日 00:00:00.542io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式   1月1日 00:00:00.542io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2829]:目前不支持 SGMII 的 EMAC 速度更改。   1月1日 00:00:00.542io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 01:00:5e:00:00:01 添加到 emac0   1月1日 00:00:00.544io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:00:00:00:01 添加到 emac0   1月1日 00:00:00.544io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:00:00:00:01 添加到 emac0: 17   1月1日 00:00:00.544io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0   1月1日 00:00:00.544io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:ff:0c:0d:66 添加到 emac0: 17   1月1日 00:00:00.544io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式   1月1日 00:00:00.554spi_master.24585 normal* 0 启动 spi-master 资源管理器 1月1日 00:00:00.558spi_master.24587 normal* 0 正在启动 spi-master 资源管理器 1月1日 00:00:00.561spi_master.24588 normal* 0 启动 spi-master 资源管理器 1月1日 00:00:00.565spi_master.24589 normal* 0 启动 spi-master 资源管理器 1月1日 00:00:00.582devb_sdmmc_mx8x.24595 slog* 1800 devb-sdmmc-mx8x 1.00A (2026年6月23日 09:45:48) 1月1日 00:00:00.583devb_sdmmc_mx8x.24595 slog 0 libcam.so (2020年6月22日 21:33:15) bver 7010003 1月1日 00:00:00.594devb_sdmmc_mx8x.24595 slog 1800 sdio_cd: 插入路径 0，cd 状态 0x1 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 SD CID: 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 MID 0x27，OID 0x5048，PNM SD32G 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 PRV 0x62，PSN 0x6c62d132，MDT 4-2023 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 SD CSD: 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 CSD_STRUCTURE 1, SPEC_VERS 0, CCC 0x5b5 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 TAAC 14, NSAC 0, TRAN_SPEED 50 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 C_SIZE 59023, C_SIZE_MULT 0 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 READ_BL_LEN 9, WRITE_BL_LEN 9 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 ERASE GRP_SIZE 0, GRP_MULT 0, SIZE 127 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 blksz 512，扇区数 60440576，dtr 25000000 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 SD SW CAPS: 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 总线模式 0x3，命令系统 0x1 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 驱动类型 0x1，当前限制 0x1 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 dtr 50000000 1月1日 00:00:00.644devb_sdmmc_mx8x.24595 slog 1800 CFG：时序 HS，DTR 50000000，总线宽度 4 位   1月1日 00:00:00.645devb_sdmmc_mx8x.24595 slog 100 cam-disk.so (2020年6月22日 21:33:17) 1月1日 00:00:00.647devb_sdmmc_mx8x.24595 slog 0 scsi_interpret_sense (sdmmc ptl-0:0:0): cam_status=c4, scsi_status=2, flag=00000040, vuflag=0008, cmd=1a, error=70, 感知=5, asc=24, ascq=0 1月1日 00:00:00.647devb_sdmmc_mx8x.24595 slog 0 scsi_interpret_sense (sdmmc ptl-0:0:0): cam_status=c4, scsi_status=2, flag=00000040, vuflag=0008, cmd=5a, error=70, 感知=5, asc=24, ascq=0 1月1日 00:00:00.647devb_sdmmc_mx8x.24595 slog 0 scsi_interpret_sense (sdmmc ptl-0:0:0): cam_status=c4, scsi_status=2, flag=00000040, vuflag=0008, cmd=5a, error=70, 感知=5, asc=24, ascq=0 1月1日 00:00:01.827devb_sdmmc_mx8x.24595 slog 1000 fs-qnx6：分配策略 0 1月1日 00:00:01.827devb_sdmmc_mx8x.24595 slog 1000 fs-qnx6：使用 btree 目录 0 1月1日 00:00:01.828devb_sdmmc_mx8x.24595 slog 1000 fs-qnx6: fs-qnx6: 未请求 trim (0,1048576,2)，且不支持此操作。 1月1日 00:00:01.833io_usb_otg.36885 slog* 0 main(453)[tid:1]: io-usb-otg (2020年6月13日 20:10:17) 参数: -d hcd-ehci-mx28 ioport=0x44064100,irq=243,ulpi,no_stream,verbose=5 1月1日 00:00:01.835devf_qspi_s32g.36884 slog* 0 (devf t1::f3s_qspi_ident:73) 页面大小：256 1月1日 00:00:01.835devf_qspi_s32g.36884 slog 0 (devf t1::f3s_qspi_ident:74) 总芯片大小：0x4000000，单元大小：0x10000 1月1日 00:00:01.839io_usb_otg.36885 slog 0 ehci_init: 使用服务器版本 2 进行初始化 1月1日 00:00:01.839io_usb_otg.36885 slog 0 ehci_controller_init(4303): devu-hcd-ehci-mx28.so (2024年4月19日 13:44:54): args ulpi,no_stream,verbose=5 1月1日 00:00:01.840io_usb_otg.36885 slog 8 usb_enum_port(94)[tid:1]: 总线号 0，父级 -1，端口 0，高速 1月1日 00:00:01.840io_usb_otg.36885 slog 11 usb_client_descriptor_get(198)[tid:1]: (类型 1，索引 0，长度 😎 1月1日 00:00:01.840io_usb_otg.36885 slog 12 usb_device_set_address(245)[tid:1]: b:0 devno 0 1月1日 00:00:01.840io_usb_otg.36885 slog 11 usb_client_descriptor_get(198)[tid:1]: (类型 1，索引 0，长度 18) 1月1日 00:00:01.841io_usb_otg.36885 slog 11 usb_client_descriptor_get(198)[tid:1]: (类型 2，索引 0，长度 9) 1月1日 00:00:01.841io_usb_otg.36885 slog 11 usb_client_descriptor_get(198)[tid:1]: (类型 2，索引 0，长度 25) 1月1日 00:00:01.841io_usb_otg.36885 slog 8 usb_enum_port(141)[tid:1]: vid 0x0000, did 0x0000 enumerated(busno 0, devno 0:0) 1月1日 00:00:01.841io_usb_otg.36885 slog 11 hub_state_inserted(569)[tid:1]: bdentry 0, dentry 0 0 1月1日 00:00:01.841io_usb_otg.36885 slog 13 hub_configuration_enable(263)[tid:1]: 1 1月1日 00:00:01.943io_usb_otg.36885 slog 0 usbh_timeout_init(203)[tid:1]: 完成 1月1日 00:00:01.954io_usb_otg.36885 slog 0 read_vid_pid: ULPI VID 0x0424 PID 0x0009 1月1日 00:00:01.954io_usb_otg.36885 slog 0 s32g_phy_set_vbus: 设置 vbus 关闭 1月1日 00:00:01.968io_usb_otg.36885 slog 0 s32g_phy_set_vbus: set_vbus on 1月1日 00:00:01.979io_usb_otg.36885 slog 0 ehci_get_port_status(3568 0x44064100): port=0, tpstatus 10100 e_pstatus 8c001000 1月1日 00:00:01.979io_usb_otg.36885 slog 8 usb_enum_port_extract(172)[tid:7]: (总线号 0，设备号 0，端口号 1) 1月1日 00:00:01.979io_usb_otg.36885 slog 8 usb_enum_port_extract(192)[tid:7]: 状态 (2) 1月1日 00:00:01.983devb_umass.36886 slog* 900 devb-umass 1.00A (2020年6月22日 21:33:41) 1月1日 00:00:01.984devb_umass.36886 slog 0 libcam.so (2020年6月22日 21:33:15) bver 7010003 1月1日 00:00:01.985io_usb_otg.36885 slog 0 usbdi_client_connect(58)[tid:5]: pid 36886 proc=proc/启动/devb-umass usbdi_client 32eebb9a80 1月1日 00:00:01.986io_usb_otg.36885 slog 0 usbdi_resmgr_connect(310)[tid:5]: usbdi_resmgr_connect: pid 36886 usbdi_client 32eebb9a80 1月1日 00:00:01.986devb_umass.36886 slog 0 usbdi 调试路径 /pps/usb/debug/ 不存在   进程 49177 (slog2info) 退出状态=0。 # ifconfig   lo0：标志=8049 mtu 33136 inet 127.0.0.1 子网掩码 0xff000000 inet6 ::1 prefixlen 128 inet6 fe80::1%lo0 prefixlen 64 scopeid 0x1 pfe0：标志=8843 mtu 1500 capabilities=1f 已启用=0 地址：00:0a:0b:0c:0d:66 介质：以太网无（1000baseT 全双工） 状态：活跃 inet 0.0.0.0 netmask 0xff000000 broadcast 255.255.255.255 inet6 fe80::20a:bff:fe0c:d66%pfe0 prefixlen 64 scopeid 0x11 pfe1：标志=8802 mtu 1500 capabilities=1f 已启用=0 地址：00:1a:1b:1c:1d:66 介质：以太网无（1000baseT 全双工） 状态：无承运商 pfe2：标志=8802 mtu 1500 capabilities=1f 已启用=0 地址：00:2a:2b:2c:2d:66 介质：以太网无（1000baseT 全双工） 状态：无承运商   进程 57369 (ifconfig) 退出状态=0。 # Re: S32G399A-RDB3 QNX PFE Driver Problems 好的，我已经将 s32g_pfe_class.fw 和 s32g_pfe_util.fw 替换成了PFE-FW_S32G_1.6.0.zip 中的文件： https://nxp.flexnetoperations.com/control/frse/download?agree=Accept&element=14074877 Uboot参数： setenv boot_qnx_atf 'mmc dev 0; fatload mmc 0:1 0x83e00000 s32g399a-rdb3.dtb;运行 atf_fdt_0to3；运行 atf_fdt_4to7；加载 mmc 0:1 0x80080000 ifs-s32g399a-rdb.ui；pfeng 启用；s32ccgmac 禁用；s32ccgmac 启用；bootm 0x80080000 - 0x83E00000' setenv atf_fdt_0to3 'fdt addr 0x83e00000; fdt resize; fdt set /cpus/cpu@1 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@100 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@101 cpu-release-addr <0x0 0xa0000010>;' setenv atf_fdt_4to7 'fdt set /cpus/cpu@2 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@3 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@102 cpu-release-addr <0x0 0xa0000010>; fdt set /cpus/cpu@103 cpu-release-addr <0x0 0xa0000010>;' setenv release_cpus 'run cpu_trap; mp 1 release 0xa0000000; mp 2 release 0xa0000000; mp 3 release 0xa0000000; mp 4 release 0xa0000000; mp 5 release 0xa0000000; mp 6 release 0xa0000000; mp 7 release 0xa0000000;' setenv cpu_trap 'dcache off; mw.l 0xa0000000 0xd503205f; mw.l 0xa0000004 0x58000060; mw.l 0xa0000008 0xb4ffffc0; mw.l 0xa000000C 0xd61f0000; mw.q 0xa0000010 0x00000000; dcache on;' setenv bootcmd 'run boot_qnx_atf' setenv hwconfig "pcie0:mode=rc,clock=ext;pcie1:mode=sgmii,clock=ext,fmhz=125,xpcs_mode=2G5" setenv pfeng_mode 'enable,sgmii,sgmii,rgmii' 设置环境变量 s32cc_gmac_mode 为禁用 保存环境 注意：我从 boot_qnx_atf 中删除了 release_cpus 命令，因为那样会导致 CPU 1 错误。 在我看来，情况并没有好转多少： 注意：BL2：v2.5（版本）：bsp37.0_rc6-2.5 通知：BL2：版本：2023年6月13日 09:12:21 注意：BL2：正在启动 BL31     U-Boot 2020.04+g156b168010（2023年6月9日 10:14:25 +0000）   CPU：NXP S32G399A rev.1.1 型号：NXP S32G399A-RDB3 动态随机存取存储器(DRAM)：3.5 GiB MMC：FSL_SDHC：0 从MMC加载环境... 成功 将 PCIe0 配置为根复合体 PCIe0：连接失败 PCI：自动配置失败，第 1c 条 输入：serial@401c8000 输出：serial@401c8000 错误：serial@401c8000 板修订：RDB3 修订版 F 网络：EQOS phy：rgmii @ 1   警告：eth_eqos (eth0) 使用随机 MAC 地址 - 16:ec:a0:4e:1d:7c eth0：eth_eqos 无法获取 emac1_xpcs 的 XPCS 速度 PFE：emac0：sgmii emac1：sgmii emac2：rgmii ，eth1：eth_pfeng 按任意键停止自动启动：3 2 1 0 切换到分区 #0，确定 mmc0 is current device 读取50640字节耗时17毫秒（2.8 MiB/s） 读取了 11950600 字节，耗时 534 毫秒（21.3 MiB/s） ## 从位于 80080000 的传统映像启动内核... 图片名称： 镜像类型：AArch64 Linux 内核镜像（未压缩） 数据大小：11950536 字节 = 11.4MiB 加载地址：80080000 入口点：80080000 校验和验证中... 成功 ## 位于 83e00000 的扁平化设备树 blob 使用位于 0x83e00000 的 fdt blob 启动 正在加载内核映像 使用位于 0000000083e00000 的设备树，结束于 0000000083e0ffff 修复：pfe0 设置为 00:01:be:be:ef:11 修复：pfe1 设置为 00:01:be:be:ef:22 修复：pfe1：将物理地址更新为 0x8 修复：pfe2 设置为 00:01:be:be:ef:33   正在启动内核...   在 EVB/RDB 上为 PFE 驱动程序保留 RAM 区域 完成。 ClockCycles 示例： 0 43642864 1 43642864 2 43642864 3 43642864 4 43642864 5 43642864 6 43642864 7 43642864 所有时钟周期偏移均在容差范围内 欢迎使用 QNX Neutrino 7.1.0在 NXP S32G399A RDB 板上！ 启动监督机制…… 正在启动串口驱动程序... 正在启动网络驱动程序（/dev/socket）...   进程 4107 (ifconfig) 退出状态=0。   进程 10 (sh) 退出状态=0。   进程 9 (dhclient) 退出状态=0。 cp：无法打开源文件。（/proc/boot/libfci_cli）   进程 20489 (cp) 退出状态=1。 正在启动 SPI 驱动程序（/dev/spi0,1,2,3,4,5）... 正在启动 I2C 0/1/2/3/4 驱动程序 (/dev/i2c0,1,2,3,4)... 正在启动 USDHC0 存储卡驱动程序... [00] SIM="SDMMC" HBA="imx" [00,0,0] type=00 ver=05 resp=00 SDMMC:   进程 24596 (chkqnx6fs) 退出状态=0。   进程 28692 (mount) 退出状态=0。 正在启动QSPI Flash驱动程序... 启动 USB 主机驱动程序 (/dev/usb/*) 检测到 QSPI Flash：Macronix MX25UW512，JEDEC 0xC2 - 0x813A，容量：0x4000000 正在为 /dev/usb/* 启动 devb-umass ... # ifconfig   lo0：标志=8049 mtu 33136 inet 127.0.0.1 子网掩码 0xff000000 inet6 ::1 prefixlen 128 inet6 fe80::1%lo0 prefixlen 64 scopeid 0x1 pfe0：标志=8843 mtu 1500 capabilities=1f 已启用=0 地址：00:0a:0b:0c:0d:66 介质：以太网无（1000baseT 全双工） 状态：活跃 inet 0.0.0.0 netmask 0xff000000 broadcast 255.255.255.255 inet6 fe80::20a:bff:fe0c:d66%pfe0 prefixlen 64 scopeid 0x11 pfe1：标志=8802 mtu 1500 capabilities=1f 已启用=0 地址：00:1a:1b:1c:1d:66 介质：以太网无（1000baseT 全双工） 状态：无承运商 pfe2：标志=8802 mtu 1500 capabilities=1f 已启用=0 地址：00:2a:2b:2c:2d:66 介质：以太网无（1000baseT 全双工） 状态：无承运商   进程 40985 (ifconfig) 退出状态=0。 # 进程 36891（睡眠）退出状态=0。 sh: /var/cetitec2/startup.sh:没有这样的文件或目录   进程 53273 (sh) 终止 signo=0 code=0 由进程 0 value=0。   # ifconfig   lo0：标志=8049 mtu 33136 inet 127.0.0.1 子网掩码 0xff000000 inet6 ::1 prefixlen 128 inet6 fe80::1%lo0 prefixlen 64 scopeid 0x1 pfe0：标志=8843 mtu 1500 capabilities=1f 已启用=0 地址：00:0a:0b:0c:0d:66 介质：以太网无（1000baseT 全双工） 状态：活跃 inet 0.0.0.0 netmask 0xff000000 broadcast 255.255.255.255 inet6 fe80::20a:bff:fe0c:d66%pfe0 prefixlen 64 scopeid 0x11 pfe1：标志=8802 mtu 1500 capabilities=1f 已启用=0 地址：00:1a:1b:1c:1d:66 介质：以太网无（1000baseT 全双工） 状态：无承运商 pfe2：标志=8802 mtu 1500 capabilities=1f 已启用=0 地址：00:2a:2b:2c:2d:66 介质：以太网无（1000baseT 全双工） 状态：无承运商   # slog2info | grep pfe 1月1日 00:00:00.051 iopkt.8main_buffer 0 devnp-pfe-2.so pfe0_mac=000a0b0c0d66,pfe1_mac=001a1b1c1d66,pfe2_mac=002a2b2c2d66,class_fw=/proc/boot/s32g_pfe_class.fw 一月 01 00:00:00.052 io_pkt_v6_hc.8slog* 0 INF[src/pfe_drv.c:1377]:版本信息 一月 01 00:00:00.052 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1384]:--- 安全中断已启用。不允许使用 InterruptAttach() 或 InterruptAttach_r()。 一月 01 00:00:00.052 io_pkt_v6_hc.8slog 0 INF[src/pfe_fw.c:83]:读取 49480 字节 一月 01 00:00:00.052 io_pkt_v6_hc.8slog 0 INF[src/pfe_fw.c:89]:已加载固件文件：/proc/boot/s32g_pfe_class.fw 一月 01 00:00:00.053 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1477]:未找到 pfe0/EMAC0 的 MII 模式配置。使用 SGMII。 一月 01 00:00:00.053 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1477]:未找到 pfe1/EMAC1 的 MII 模式配置。使用 SGMII。 一月 01 00:00:00.053 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1477]:未找到 pfe2/EMAC2 的 MII 模式配置。使用 RGMII。 一月 01 00:00:00.053 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1495]:发出 PFE 外设复位指令... 一月 01 00:00:00.274 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1496]:PFE重置成功。 一月 01 00:00:00.274 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:3519]:PFE CBUS p0x46000000 映射到 v0x1abef95000 一月 01 00:00:00.274 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:3524]:硬件版本 0x101 一月 01 00:00:00.274 io_pkt_v6_hc.8slog 0 INF[src/pfe_hw_feature.c:95]: Silicon S32G3 一月 01 00:00:00.274 io_pkt_v6_hc.8slog 0 WRN[hw/s32g/pfe_platform_master.c:3536]:故障停止模式已禁用 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2687]:PFE_ERRORS：已创建 Parity 实例 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2702]:PFE_ERRORS：已创建监视程序实例 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2718]:PFE_ERRORS：总线错误实例已创建 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2731]:PFE_ERRORS：FW 故障停止实例已创建 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2744]:PFE_ERRORS：主机故障停止实例已创建 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2757]:PFE_ERRORS：已创建故障停止实例 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2770]:PFE_ERRORS：ECC 错误实例已创建 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:1766]:BMU1 缓冲区基址：p0xc0000000 一月 01 00:00:00.277 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:1810]:BMU2 缓冲区基址：p0x83000000（0x200000 字节） 一月 01 00:00:00.279 io_pkt_v6_hc.8slog 0 WRN[hw/s32g/pfe_platform_master.c:2194]:选项“g2_ordered_class_writes”已禁用。 一月 01 00:00:00.279 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_bmu_csr.c:96]: BMU_EMPTY_INT (BMU @ p0x88000)。泳池已准备就绪。 一月 01 00:00:00.279 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_bmu_csr.c:96]: BMU_EMPTY_INT (BMU @ p0x8c000)。泳池已准备就绪。 一月 01 00:00:00.281 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2239]:固件 .elf检测到 一月 01 00:00:00.281 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2248]:正在上传 CLASS 固件 一月 01 00:00:00.281 io_pkt_v6_hc.8slog 0 INF[src/pfe_pe.c:609]:选择固件加载操作，并行加载 8 个 PE。 一月 01 00:00:00.285 io_pkt_v6_hc.8slog 0 INF[src/pfe_pe.c:1945]:pfe_ct.h文件版本“92367c0e25f21f49217a9b08168ad2c8” 一月 01 00:00:00.288 io_pkt_v6_hc.8slog 0 INF[src/pfe_pe.c:2422]:[固件版本] 1.6.0构建版本：2023年3月15日 12:37:54 ()，ID：0x31454650 1 月 1 日 00:00:00.406 io_pkt_v6_hc.8slog 0 WRN[hw/s32g/pfe_platform_master.c:2312]:VLAN ID 不正确或未设置。使用默认 VLAN ID = 0x01。 1 月 1 日 00:00:00.406 io_pkt_v6_hc.8slog 0 WRN[hw/s32g/pfe_platform_master.c:2318]:VLAN统计信息大小不正确或未设置。使用默认 VLAN 统计信息大小 = 20。 1 月 1 日 00:00:00.406 io_pkt_v6_hc.8slog 0 INF[src/pfe_l2br.c:1181]:软件 VLAN 哈希表 @ p0x20001208 1 月 1 日 00:00:00.406 io_pkt_v6_hc.8slog 0 INF[src/pfe_l2br.c:1286]:备用桥接域 @ 0x20000a44（类） 1 月 1 日 00:00:00.406 io_pkt_v6_hc.8slog 0 INF[src/pfe_l2br.c:1287]:默认桥接功能域 @ 0x20000a3c（类） 1 月 1 日 00:00:00.406 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2412]:路由表已创建，哈希表位于 p0x80014000，池位于 p0x8001c000（65536 字节） 一月 01 00:00:00.407 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_chnl.c:1997]: 初始化 RX 缓冲池。深度：256；缓冲区大小：2048；缓存行大小：64 一月 01 00:00:00.408 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_chnl.c:1997]: 初始化 RX 缓冲池。深度：256；缓冲区大小：2048；缓存行大小：64 一月 01 00:00:00.409 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_chnl.c:1997]: 初始化 RX 缓冲池。深度：256；缓冲区大小：2048；缓存行大小：64 一月 01 00:00:00.508 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:3705]:功能错误 err051211_workaround：已禁用 1月1日 00:00:00.509 iopkt.8主缓冲区 0 pfe0 一月 01 00:00:00.509 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2145]:pfe0：使用静态 PHY 模式，RESET=0 1 月 1 日 00:00:00.510 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1795]:将 00:0a:0b:0c:0d:66 添加到 pfe0 1月1日 00:00:00.512 iopkt.8主缓冲区 0 pfe1 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2298]:未找到 pfe0 的速度/双工配置。使用 1 Gbps/全双工。 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:336]: 尝试注册 HIF 客户端：0 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF 驱动程序已启动 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2363]:新PFE设备：0，ID：0 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2145]:pfe1：使用静态 PHY 模式，RESET=0 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1795]:将 00:1a:1b:1c:1d:66 添加到 pfe1 1月1日 00:00:00.514 iopkt.8主缓冲区 0 pfe2 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2298]:未找到 pfe1 的速度/双工配置。使用 1 Gbps/全双工。 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:336]: 尝试注册 HIF 客户端：1 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF 驱动程序已启动 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2363]:新的PFE设备：1，ID：2 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2145]:pfe2：使用静态 PHY 模式，RESET=0 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1795]:将 00:2a:2b:2c:2d:66 添加到 pfe2 一月 01 00:00:00.516 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2298]:未找到 pfe2 的速度/双工配置。使用 1 Gbps/全双工。 1 月 1 日 00:00:00.516 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:336]: 尝试注册 HIF 客户端：2 一月 01 00:00:00.516 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF 驱动程序已启动 1 月 1 日 00:00:00.516 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2363]:新型PFE设备：2，ID：4 一月 01 00:00:00.531 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2702]:将 00:0a:0b:0c:0d:66 添加到 pfe0 一月 01 00:00:00.531 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2707]:无法将 MAC 地址 00:0a:0b:0c:0d:66 分配给 pfe0 一月 01 00:00:00.531 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式 一月 01 00:00:00.531 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2829]:目前不支持 SGMII 的 EMAC 速度更改。 一月 01 00:00:00.532 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0 一月 01 00:00:00.534 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式 一月 01 00:00:00.534 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:00:00:00:01 添加到 emac0 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:ff:0c:0d:66 添加到 emac0: 17 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:00:00:00:01 添加到 emac0 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:00:00:00:01 添加到 emac0: 17 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:ff:0c:0d:66 添加到 emac0: 17 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2829]:目前不支持 SGMII 的 EMAC 速度更改。 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 01:00:5e:00:00:01 添加到 emac0 一月 01 00:00:00.538 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:00:00:00:01 添加到 emac0 一月 01 00:00:00.538 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:00:00:00:01 添加到 emac0: 17 一月 01 00:00:00.538 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0 一月 01 00:00:00.538 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:ff:0c:0d:66 添加到 emac0: 17 一月 01 00:00:00.538 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式 # slog2info | grep io_pkt_v6_hc 一月 01 00:00:00.052 io_pkt_v6_hc.8slog* 0 INF[src/pfe_drv.c:1377]:版本信息 一月 01 00:00:00.052 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1384]:--- 安全中断已启用。不允许使用 InterruptAttach() 或 InterruptAttach_r()。 一月 01 00:00:00.052 io_pkt_v6_hc.8slog 0 INF[src/pfe_fw.c:83]:读取 49480 字节 一月 01 00:00:00.052 io_pkt_v6_hc.8slog 0 INF[src/pfe_fw.c:89]:已加载固件文件：/proc/boot/s32g_pfe_class.fw 一月 01 00:00:00.053 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1477]:未找到 pfe0/EMAC0 的 MII 模式配置。使用 SGMII。 一月 01 00:00:00.053 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1477]:未找到 pfe1/EMAC1 的 MII 模式配置。使用 SGMII。 一月 01 00:00:00.053 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1477]:未找到 pfe2/EMAC2 的 MII 模式配置。使用 RGMII。 一月 01 00:00:00.053 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1495]:发出 PFE 外设复位指令... 一月 01 00:00:00.274 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1496]:PFE重置成功。 一月 01 00:00:00.274 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:3519]:PFE CBUS p0x46000000 映射到 v0x1abef95000 一月 01 00:00:00.274 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:3524]:硬件版本 0x101 一月 01 00:00:00.274 io_pkt_v6_hc.8slog 0 INF[src/pfe_hw_feature.c:95]: Silicon S32G3 一月 01 00:00:00.274 io_pkt_v6_hc.8slog 0 WRN[hw/s32g/pfe_platform_master.c:3536]:故障停止模式已禁用 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2687]:PFE_ERRORS：已创建 Parity 实例 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2702]:PFE_ERRORS：已创建监视程序实例 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2718]:PFE_ERRORS：总线错误实例已创建 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2731]:PFE_ERRORS：FW 故障停止实例已创建 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2744]:PFE_ERRORS：主机故障停止实例已创建 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2757]:PFE_ERRORS：已创建故障停止实例 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2770]:PFE_ERRORS：ECC 错误实例已创建 一月 01 00:00:00.275 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:1766]:BMU1 缓冲区基址：p0xc0000000 一月 01 00:00:00.277 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:1810]:BMU2 缓冲区基址：p0x83000000（0x200000 字节） 一月 01 00:00:00.279 io_pkt_v6_hc.8slog 0 WRN[hw/s32g/pfe_platform_master.c:2194]:选项“g2_ordered_class_writes”已禁用。 一月 01 00:00:00.279 io_pkt_v6_hc.8slog 0 INF[src/oal_irq_qnx.c:117]: PFE BMU IRQ 工作进程已启动（IRQ ID：226） 一月 01 00:00:00.279 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_bmu_csr.c:96]: BMU_EMPTY_INT (BMU @ p0x88000)。泳池已准备就绪。 一月 01 00:00:00.279 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_bmu_csr.c:96]: BMU_EMPTY_INT (BMU @ p0x8c000)。泳池已准备就绪。 一月 01 00:00:00.281 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2239]:固件 .elf检测到 一月 01 00:00:00.281 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2248]:正在上传 CLASS 固件 一月 01 00:00:00.281 io_pkt_v6_hc.8slog 0 INF[src/pfe_pe.c:609]:选择固件加载操作，并行加载 8 个 PE。 一月 01 00:00:00.285 io_pkt_v6_hc.8slog 0 INF[src/pfe_pe.c:1945]:pfe_ct.h文件版本“92367c0e25f21f49217a9b08168ad2c8” 一月 01 00:00:00.288 io_pkt_v6_hc.8slog 0 INF[src/pfe_pe.c:2422]:[固件版本] 1.6.0构建版本：2023年3月15日 12:37:54 ()，ID：0x31454650 1 月 1 日 00:00:00.406 io_pkt_v6_hc.8slog 0 WRN[hw/s32g/pfe_platform_master.c:2312]:VLAN ID 不正确或未设置。使用默认 VLAN ID = 0x01。 1 月 1 日 00:00:00.406 io_pkt_v6_hc.8slog 0 WRN[hw/s32g/pfe_platform_master.c:2318]:VLAN统计信息大小不正确或未设置。使用默认 VLAN 统计信息大小 = 20。 1 月 1 日 00:00:00.406 io_pkt_v6_hc.8slog 0 INF[src/pfe_l2br.c:1181]:软件 VLAN 哈希表 @ p0x20001208 1 月 1 日 00:00:00.406 io_pkt_v6_hc.8slog 0 INF[src/pfe_l2br.c:1286]:备用桥接域 @ 0x20000a44（类） 1 月 1 日 00:00:00.406 io_pkt_v6_hc.8slog 0 INF[src/pfe_l2br.c:1287]:默认桥接功能域 @ 0x20000a3c（类） 1 月 1 日 00:00:00.406 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:2412]:路由表已创建，哈希表位于 p0x80014000，池位于 p0x8001c000（65536 字节） 一月 01 00:00:00.407 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_chnl.c:1997]: 初始化 RX 缓冲池。深度：256；缓冲区大小：2048；缓存行大小：64 一月 01 00:00:00.408 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_chnl.c:1997]: 初始化 RX 缓冲池。深度：256；缓冲区大小：2048；缓存行大小：64 一月 01 00:00:00.409 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_chnl.c:1997]: 初始化 RX 缓冲池。深度：256；缓冲区大小：2048；缓存行大小：64 一月 01 00:00:00.508 io_pkt_v6_hc.8slog 0 INF[hw/s32g/pfe_platform_master.c:3705]:功能错误 err051211_workaround：已禁用 一月 01 00:00:00.509 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2145]:pfe0：使用静态 PHY 模式，RESET=0 一月 01 00:00:00.509 io_pkt_v6_hc.8slog 0 INF[src/oal_irq_qnx.c:117]: PFE HIF0 IRQ 工作进程已启动（IRQ ID：222） 1 月 1 日 00:00:00.510 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1795]:将 00:0a:0b:0c:0d:66 添加到 pfe0 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2298]:未找到 pfe0 的速度/双工配置。使用 1 Gbps/全双工。 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:336]: 尝试注册 HIF 客户端：0 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF 驱动程序已启动 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2363]:新PFE设备：0，ID：0 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2145]:pfe1：使用静态 PHY 模式，RESET=0 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/oal_irq_qnx.c:117]: PFE HIF1 IRQ 工作进程已启动（IRQ ID：223） 一月 01 00:00:00.512 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1795]:将 00:1a:1b:1c:1d:66 添加到 pfe1 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2298]:未找到 pfe1 的速度/双工配置。使用 1 Gbps/全双工。 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:336]: 尝试注册 HIF 客户端：1 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF 驱动程序已启动 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2363]:新的PFE设备：1，ID：2 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2145]:pfe2：使用静态 PHY 模式，RESET=0 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/oal_irq_qnx.c:117]: PFE HIF2 IRQ 工作进程已启动（IRQ ID：224） 一月 01 00:00:00.514 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:1795]:将 00:2a:2b:2c:2d:66 添加到 pfe2 1 月 1 日 00:00:00.516 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2298]:未找到 pfe2 的速度/双工配置。使用 1 Gbps/全双工。 1 月 1 日 00:00:00.516 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:336]: 尝试注册 HIF 客户端：2 1 月 1 日 00:00:00.516 io_pkt_v6_hc.8slog 0 INF[src/pfe_hif_drv_sc.c:1189]: HIF 驱动程序已启动 1 月 1 日 00:00:00.516 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2363]:新型PFE设备：2，ID：4 一月 01 00:00:00.531 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2702]:将 00:0a:0b:0c:0d:66 添加到 pfe0 一月 01 00:00:00.531 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2707]:无法将 MAC 地址 00:0a:0b:0c:0d:66 分配给 pfe0 一月 01 00:00:00.531 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式 一月 01 00:00:00.531 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2829]:目前不支持 SGMII 的 EMAC 速度更改。 一月 01 00:00:00.532 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0 一月 01 00:00:00.534 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式 一月 01 00:00:00.534 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:00:00:00:01 添加到 emac0 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:ff:0c:0d:66 添加到 emac0: 17 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:00:00:00:01 添加到 emac0 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:00:00:00:01 添加到 emac0: 17 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:ff:0c:0d:66 添加到 emac0: 17 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2829]:目前不支持 SGMII 的 EMAC 速度更改。 一月 01 00:00:00.536 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 01:00:5e:00:00:01 添加到 emac0 一月 01 00:00:00.538 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:00:00:00:01 添加到 emac0 一月 01 00:00:00.538 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:00:00:00:01 添加到 emac0: 17 一月 01 00:00:00.538 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0 一月 01 00:00:00.538 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:ff:0c:0d:66 添加到 emac0: 17 一月 01 00:00:00.538 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式 进程 172057 (slog2info) 退出状态=0。 一月 01 00:01:01.630 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:00:00:00:01 添加到 emac0 一月 01 00:01:01.630 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:00:00:00:01 添加到 emac0: 17 一月 01 00:01:01.630 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2443]:将 33:33:ff:0c:0d:66 添加到 emac0 一月 01 00:01:01.630 io_pkt_v6_hc.8slog 0 WRN[src/pfe_drv.c:2450]:无法将 33:33:ff:0c:0d:66 添加到 emac0: 17 一月 01 00:01:01.630 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2495]:从 emac0 中移除 01:00:5e:00:00:01 一月 01 00:01:01.632 io_pkt_v6_hc.8slog 0 INF[src/pfe_phy_if.c:2716]:地址 01:00:5e:00:00:01 已从 emac0 中移除 一月 01 00:01:01.632 io_pkt_v6_hc.8slog 0 INF[src/pfe_drv.c:2663]:pfe0：禁用混杂模式 Re: S32G399A-RDB3 QNX PFE Driver Problems 你好， @Seneca 感谢你的帖子。 默认情况下， S32G PFE QNX 驱动程序版本 1.4.0 与 S32G PFE 固件标准版本 1.6.0 兼容，您能否使用此 PFE 固件版本再次进行测试？ BR 陈银 Re: S32G399A-RDB3 QNX PFE Driver Problems 好的，所以我下载了 BSP_nxp-s32g-evb_br-710_be-710_SVN984052_JBN51 您提到的软件包修改了 .build 文件。文件并添加 kprintf("为 EVB/RDB 上的 PFE 驱动程序保留 RAM 区域\n"); as_add_containing(0x80000000,0x80000000 + 0x4000000 - 1,AS_ATTR_RAM, "pfe_ddr","ram"); 至 src/hardware/startup/boards/s32g/s32g399a-rdb/s32g_init_raminfo.c 并将我的 ifs 文件替换为生成的 ifs-s32g399a-rdb.ui。 遗憾的是，它似乎没有执行上面的 pfe_ddr 分配。 我需要修改 uboot 参数或其他什么设置才能让这个新镜像正常工作吗？ 此致

FRDM i.MX 93 Hi. I am interested in use the FRDM i.MX 93 in a project where I need Linux operating system, and control other devices by RS232, SPI and I2C ports. I see that there is an UART port used to USB debug, there are another UART port, I2C and SPI ports that I can use?  

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RT1189 - 2 octal 166MHz HyperRAMs on SPI1 to create 16-bit wide bus? The RT1180 RM shows a Parallel FlexSPI configuration wherein two octal HyperBus memories on SPI1 to A_D7..0 and B_D7..0 to form a 16 bit wide bus.  See pages 2243 & 2244, Table 196, 6th row down which is the only entry where Effective Bus Size is listed as 16bit.  If this actually works, the max data transfer rate should be 166 MHz x 2 bytes x 2 transfers per clock period = 644 MB/s. Has anyone tried this configuration? If yes, does it work and what was the actual performance? Thanks! Re: RT1189 - 2 octal 166MHz HyperRAMs on SPI1 to create 16-bit wide bus? Hi @DoubleD , Thanks for your interest in NXP MIMXRT series! RM lists the 2×8b parallel connection mode for FLEXSPI1, but no verified RT1180 dual-HyperRAM 16-bit parallel example/benchmark was found in public resources like SDK demos or ANSW. And theoretical raw line rate is 664 MB/s, but it must not be used as guaranteed bandwidth. This use case may require users to test it on a custom board. We apologize for any inconvenience this may cause at this stage. Best regards, Gavin

S32K342、HSE、設置に関する問題 S32K342カスタムボード + PEmicro。S32K344_HSE_FW_INSTALL サンプルを S32K342 に移植しました。ビルドは正常に完了し、S32K342.mac のリセットも完了しますが、 main に到達する前にコードが Default_Handler (BusFault/HardFault) にトラップされ、起動時に失敗します。ピンクは0.13.0_2.40.0 FULL_MEMです。S32K342では、どのようなスタートアップ/リンカーの変更が必要ですか？ Re: S32K342, HSE , installation issues 最近似たような問題に直面したので、使用済みのライブラリ(セミホスティングなど)が原因かもしれません。newlib_nano を選択してください（I/O なし） それ以外の場合、S32K344_HSE_FW_INSTALLを別の派生製品に移植するのは非常に簡単です。S32K342のスタートアップコードとレジスタ定義を使用する必要があります。

Default workspace Hello, I'm using MCUXpressoIDE v.24.9.25 (I know I could run a newer version, but for some reasons, I need to run 24.9.25). As I can see in "C:\NXP\MCUXpressoIDE_24.9.25\ide\configuration\config.ini", osgi.instance.area.default is "@user.home/Documents/MCUXpressoIDE_24.9.25/workspace", so it's correct. However, if I close Windows user session and open a new one with other user, when I run MCUXpressoIDE, the default workspace is the workspace of the first user, so I need to change to the second workspace directory because each user have their own directory. It seems that osgi.instance.area.default is not working fine, because @user.home/Documents/MCUXpressoIDE_24.9.25/workspace should be the home of each user, but always takes the first login user. How could I reconfigure this? Thanks. #mcux Re: Default workspace Hello, Could you help us confirm if you have the cell "Use this as the default and do not ask again" enable?  If you tick the Use this as the default and do not ask again option, then MCUXpresso IDE always starts up with the chosen workspace opened; I would recommend on not having this box checked to select the Workspace You could add the other workspace for User 2 and keep it in Recent workspaces, so you can select your desired workspace before the app open Also, In Tab Window> Preferences> General>Startup and Shutdown>Workspaces Enable the Prompt for workspace on startup. Best Regards, Luis

How can I configure GPIO_EMC_B2_18 as FLEXSPI1_A_DQS and set the clock frequency to 133 MHz? Hello, I want to configure GPIO_EMC_B2_18 as FLEXSPI1_A_DQS and set the clock frequency to 133 MHz on the i.MX RT1175. I understand that GPIO_EMC_B2_18 cannot be set to FLEXSPI1_A_DQS during boot. Therefore, I’m trying to run it at 60 MHz during boot and change it to 133 MHz in the application, but it doesn’t work. I am using the evkbmimxrt1170_flexspi_nor_polling_transfer project and have modified the relevant section of `flexspi_nor_flash_init()` in `flexspi_nor_flash_ops.c`. ``` IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS, 1U); IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS, 0x0AU); CLOCK_SetRootClockDiv(kCLOCK_Root_Flexspi1, 4); CLOCK_SetRootClockMux(kCLOCK_Root_Flexspi1, 5); config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad; ``` The system hangs when the clock frequency is set to 133MHz. ``` CLOCK_SetRootClockDiv(kCLOCK_Root_Flexspi1, 5); CLOCK_SetRootClockMux(kCLOCK_Root_Flexspi1, 5); ``` It works when the clock frequency is set to 105MHz. How can I configure GPIO_EMC_B2_18 to FLEXSPI1_A_DQS and set the clock frequency to 133 MHz? Re: How can I configure GPIO_EMC_B2_18 as FLEXSPI1_A_DQS and set the clock frequency to 133 MHz? Hi @mayliu1, Thanks for your reply. It’s true that the secondary ping group may only operate at 100 MHz, but I’m planning to use the primary ping group and change only the DQS to GPIO_EMC_B2_18. The reason is that I’m using GPIO_SD_B2_05 for USDHC2_CMD. Pin Configuration FLEXSPI1_A_SS0_B　GPIO_SD_B2_06 FLEXSPI1_A_SCLK　GPIO_SD_B2_07 FLEXSPI1_A_DATA0　GPIO_SD_B2_08 FLEXSPI1_A_DATA1　GPIO_SD_B2_09 FLEXSPI1_A_DATA2　GPIO_SD_B2_10 FLEXSPI1_A_DATA3　GPIO_SD_B2_11 FLEXSPI1_A_DQS　GPIO_SD_B2_05 (boot) In the application, only FLEXSPI1_A_DQS is changed to GPIO_EMC_B2_18. FLEXSPI1_A_DQS　GPIO_EMC_B2_18 As a test, I changed the clock frequency from 60 MHz (boot) to 133 MHz on the EVK without changing FLEXSPI1_A_DQS—leaving it set to GPIO_SD_B2_05—and it hung up in the same way. Since the xip configuration was set to .readSampleClksrc=kFlexSPIReadSampleClk_LoopbackInternally, I changed it to kFlexSPIReadSampleClk_LoopbackFromDqsPad, and was able to run it at 133 MHz. Next, I tried changing the DQS to GPIO_EMC_B2_18, and was able to run it at 133 MHz. Is this approach acceptable? Also, during boot, GPIO_SD_B2_05 is not floating. Is it okay to set it to `kFlexSPIReadSampleClk_LoopbackFromDqsPad` and run it at 60 MHz? Re: How can I configure GPIO_EMC_B2_18 as FLEXSPI1_A_DQS and set the clock frequency to 133 MHz? Hi @Shuhei_D , Thank you so much for your interest in our products and for using our community. Please refer to the following post for more details: https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/RT-1176-FlexSPI-RW-frequency-DQS/m-p/1871808 According to the RT1170 Reference Manual, when using the secondary pin group, the maximum supported FlexSPI flash frequency is 100 MHz. Could you please check your project configuration and confirm whether it matches the scenario described in the link above? Wish it helps you Best Regards May Re: How can I configure GPIO_EMC_B2_18 as FLEXSPI1_A_DQS and set the clock frequency to 133 MHz? Thank you for your reply. Upon checking the schematics, I see that GPIO_EMC_B2_18 is floating. Re: How can I configure GPIO_EMC_B2_18 as FLEXSPI1_A_DQS and set the clock frequency to 133 MHz? It seems you want to switch the SPI clock freq from 60MHz to 133MHz to drive the NOR flash external. But 105MHz seems ok so you may need to check the layout side according to signal integrity with SPI high frequncey. Do you review the schematics? Re: How can I configure GPIO_EMC_B2_18 as FLEXSPI1_A_DQS and set the clock frequency to 133 MHz? Hi @Shuhei_D , Thanks for your patience. I have double-checked your question. Please use the primary DQS pin and do not use the secondary DQS option. For your case, if the primary DQS pin is already used for another function, you may apply the following configuration. However, please note that this setting is only supported up to 60 MHz: Wish it helps you Best Regards May

Ezurio Sona NX611 support in MCUXpresso SDK Hello, Is Ezurio Sona NX611 wireless card supported in MCUXpresso SDK FreeRTOS? As it's using base NXP IW611 radio, I think it should be supported, right?

RT1176 PWMの起動に失敗しました 私はPWM + Fault + QTimerを使ってモーターパルス制御を実装していますが、PWM3サブモジュール0のPWM_Aチャネルが時々起動できず、最初のハイレベル以降は一定のままで、その後のパルスは現れません。検査の結果、PWMの「ラン」部分が正しく設定されていないことが判明しました。後からプログラムに起動時の処理を繰り返し追加したにもかかわらず、この異常は依然として発生した。 Re: RT1176 PWM startup failed こんにちは、 @liu626 さん。 カスタムボードを使用していますか、それともEVKを使用していますか？EVKを使用している場合、何か改造を加えましたか？ PWM3で使っている構成を教えてもらえますか? 何か例を参考にしていますか？もしそうなら、どの学校ですか? PWM3のみを含むプロジェクトを使用して問題を再現しようとした場合、問題は解消されますか？ これはPWM3サブモジュール0のPWM_Aチャネルだけに起こるのでしょうか?他のPWMモジュールやサブモジュールでも同様の現象が発生しましたか？ PWM3レジスタを操作し、ランビットに影響を与えたり上書きしたりする他のタスクや割り込みはありますか? よろしくお願いします、 パブロ