# README This is a mcan sdk demo on MPC5777C. Transmit data in turn and received data. CANFD is not used and extended id is used. Both Tx and Rx use interrupt. All documents are in [mpc5777c_test_mcan/mpc5777c_test_mcan_Z7_0/Documentation] folder. ## Board MPC5777C-416DS + MPC57xx MOTHERBOARD (SCH-27237 REV C) ## CAN PC Client PCAN-View ## Compiler powerpc-eabivle-gcc with S32 Design Studio for Power Architecture IDE ## MCAN MCAN0 ## Pin PC[19] - MCAN0 Tx PC[20] - MCAN0 Rx ## SDK S32_SDK_S32PA_EAR_1.8.0 ## Caution 1. Error to send data bytes which are not multiple times of 4 with MCAN_StartSendData() in mcan_driver.c. So MCAN_StartSendData() must be modified. Modified position is 606 to 607 lines in mcan_driver.c. 2. MCAN_DRV_InstallEventCallback() hasn't been implemented yet, must be added. ## Revision History Release 1.0.0 - 2018/12/19 - Jacob Peng - jacob.peng@nxp.com * Mod: MCAN_StartSendData() in mcan_driver.c * Add: MCAN_DRV_InstallEventCallback() in mcan_driver.c * Add: Demo application

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, GPIO pins. * DSPI1 module is configured as a master, DSPI2 module is configured as a slave. * First, response of slave is initialized by writing to PUSHR register of DSPI2. * Second, we write PUSHR register of DSPI1 to send data from master. * Once data are received on both master and slave, data are read from POPR. * ------------------------------------------------------------------------------ * Test HW:         MPC5746R-176DC, MPC57xx Motherboard * MCU:             PPC5746R 1N83M * Fsys:            PLL 200MHz * Debugger:        Lauterbach Trace32 * IDE:             S32DS for Power 2017.R1 * Target:          internal_FLASH (debug mode, debug_ram mode) * EVB connection: * Connect PA13 (P8.14) to PS11 (P27.12) * Connect PA10 (P8.11) to PS10 (P27.11) * Connect PG12 (P14.13) to PS13 (P27.14) * Connect PG13 (P14.14) to PS7 (P27.8) * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, Setup access right for Masters and Peripherals * on AIPS_0 * * LINFlex UART mode with FIFO transmit using DMA * LINFlex UART mode with FIFO receive using DMA * * ICache and DCache are both disabled in startup file using CACHE_ENABLE macro. * You can change the value of the macro at the following path: * project Properties/C/C++ General/Paths and Symbols/Symbols * If you change the value to 1, ICahce and DCache will be enabled in startup. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  J14.2 to P12.6 Connect LINFlexD_0 RXD to main RS232 *                  J13.2 to P12.7 Connect LINFlexD_0 TXD to main RS232 * ********************************************************************************

This document summarizes simple I2C driver implementation for MPC5xxx devices. The code follows Reference Manual's Flow-Chart of Typical I2C Interrupt Routine.

******************************************************************************** * Detailed Description: * * This example shows how to use CRC module. * - CRC32 is used * - byte stream is written into input register * - one test case uses direct access to CRC registers * - second test case uses DMA to write the data stream * - the results can be compared using this online calculator: *   http://www.zorc.breitbandkatze.de/crc.html * - screenshots from online calculator are attached * ------------------------------------------------------------------------------ * Test HW:         MPC574XG-324DS Rev.A + MPC574XG-MB Rev.C * MCU:             PPC5748GMMN6A 1N81M * Fsys:            160 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH ********************************************************************************

Hello    If you want to do nothing on MCU, no-operation is used generally.     Additional mnemonics are provided for the preferred forms of no-op, like nop, e_nop, se_nop. (Where the semantics are similar but the binary encoding differ, the standard mnemonic is typically preceded with an e_ to denote a VLE instruction. To distinguish between similar instructions available in both 16- and 32-bit forms under VLE and standard instructions, VLE instructions encoded with 16 bits have an se_ prefix.)    When you compile these code within IDE, you can get the results as below. The code could run correctly except __asm__ ("nop").  Some MPC5xxx will stop at __asm__ ("nop").    "nop"         gives Book E NOP instruction which isn't valid on VLE only cores. "e_nop"     gives 32bit VLE instruction. "se_nop"   gives 16bit VLE instruction. Based on the summary within AN4802 (thanks for Randy Dee's working), Qorivva MPC57xx e200zx Core Differences, Book E is not supported by MPC57xx. VLE instruction set is supported only.   This is the reason that user should use "e_nop" or "se_nop" except "nop" on MPC57xx or S32R2xx. Cheers! Oliver

******************************************************************************** * Detailed Description: * Example show simple flash programming routine. During runtime it changes * content of field of constants 'test' (located in internal data flash). * Also it shows how to relocate data into FLASH (used linker command file * is MPC5675K_my_sections.lcf and MPC5675K_DEBUG_my_sections.lcf). * * Note: For complex tasks use SSD driver (Freescale site for particular device, * Software&Tools/Run-Time Software/Middleware-Device Drivers * ------------------------------------------------------------------------------ * Test HW:        MPC5675KEVB * MCU:            PPC5675KFMMSJ in Lock-Step mode * Fsys:           180/150 MHz CORE_CLK * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization then it initializes EBI for external * SRAM connected to MPC5777C-516DS and test it by write and read of block of * data. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 3N45H * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  jumper J4 on position 1-2 (choosing CS0) *                  EMIOS1 (PortI P16-0) --> USER_LED_1 (P7-1) to see LED blink ******************************************************************************** Revision History: Ver  Date         Author            Description of Changes 0.1  Jun-26-2017  David Tosenovjan  Initial version 0.2  Oct-13-2017  David Tosenovjan  Lower CLKOUT frequency 0.3  Feb-02-2020  David Tosenovjan  Corrected External_SRAM_MMU_init                                     Ported to S32 design studio *******************************************************************************/

******************************************************************************** * Detailed Description: * * Configures the FlexCAN to transmit and receive a CAN message. * ECC reporting in the FlexCAN module is disabled. * * In this config, CAN_A transmits a message. CAN_B receives the message. * CAN_A MB8 is configured to send data. CAN_A sends message each 1sec. * This interval is generated by PIT. * CAN_B MB9 is configured to receive a message, SW polling is used. * * Connect CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * Connect CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *           use USB connector (J21) on minimodule * * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * This example initializes SMPU_0 and SMPU_1 to cover all memory resources for * all masters. * Simple test case is used in this example: after initialization, SMPU * configuration is changed to disable write access to last 4kB of RAM. * Once this area is written by CPU, exception will occur due to access * violation. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N81M * Target :  SRAM * Fsys:     160 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, * initializes and display notice via UART terminal and then terminal ECHO. * * You can choose TRK or Minimodule version using USED_BOARD macro * * ------------------------------------------------------------------------------ * Test HW:         XPC560P 100LQFP, XPC56XX EVB MOTHEBOARD Rev.B, TRK-MPC5604P Rev.B * MCU:             PPC5604PEFMLL 0M36W * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFLEX_0 * Fsys:            64/40 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  Jumper J8 1st position fit LED1 connected to PE4, jumpers J22,23 position 2-3 fit SCI tx and rx connected * ********************************************************************************

This example shows I2C communication with NXP PCA24S08 memory. The simple MPC5xxx I2C driver is used, see driver code/description on https://community.freescale.com/docs/DOC-330972.   EVB connection: P1.11 - A[10] .. I2C0 SDA P1.12 - A[11] .. I2C0 SCL   ------------------------------------------------------------------------------ Test HW:  TRK-MPC5606B Maskset:  0N13E Target :  RAM, Flash Terminal: 115200, 8N1 Fsys:     64 MHz PLL with 8 MHz crystal reference in RUN0.     PC terminal displays this info ...       You can see following I2C bus signals for particular conditions … Writing byte “H” into address 0x28 Read content of the address 0x28   Writing string “Hello world!” into address 0x152     Reading page (16 bytes) from memory address 0x150  

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, * * Initializes the MCU including the FlexCAN peripherals. * Configures the FlexCAN to transmit and receive a CAN message. * * Individual RX masking was added to the last version of this example. * Three messages with different ID's are sent via FlexCAN_0 MB0 MB1 and MB2. * These messages are received by FlexCAN_1 MB0, MB1 and MB2 according to masking * register settings. * * For MB0 data receive is used interrupt. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N38M * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection: * * It is necessary to remove both J32 jumpers and also both J35 jumpers. * * Connect J32.2 to PC9 (CAN_0 TX) * Connect J32.4 to PC8 (CAN_0 RX) * * Connect J35.2 to PE5 (CAN_1 TX) * Connect J35.4 to PG14 (CAN_1 RX) * * Connect CAN P5.2 to CAN2 P4.2 (CAN_0 and CAN_1 CANL) * Connect CAN P5.1 to CAN2 P4.1 (CAN_0 and CAN_1 CANH) * * This connection has to be observed, otherwise correct communication between * CAN modules is not guaranteed. * * ********************************************************************************

This document describes MPC57xx DCF (device configuration record) in details.   Before MPC57xx devices can be used by application they must pass a complex system reset sequence. During system reset sequence device initialization is done. Various self-test mechanism, configuration and trimming is executed during this time. In order to prepare correct device operation, it is necessary to configure device during reset phase. For this purpose, MPC57xx implements DCF records located in special one-time programable flash memory (UTEST).   To easy the work with DCF records we have created a DCF records calculators for each MPC57xx ad S32R274 device. Links to calculators: MPC5746R: https://community.nxp.com/docs/DOC-334130 MPC5777C: https://community.nxp.com/docs/DOC-335523 MPC5744P: https://community.nxp.com/docs/DOC-341538 MPC5746C:  https://community.nxp.com/docs/DOC-341539 MPC5748G: https://community.nxp.com/docs/DOC-341540 MPC5775K: https://community.nxp.com/docs/DOC-341541 MPC5777M: https://community.nxp.com/docs/DOC-341542 S32R274: https://community.nxp.com/docs/DOC-341633

******************************************************************************** * Detailed Description: * 200 MHz PLL with 40 MHz crystal reference + FCCU fault clearing *           example code + FCCU ALARM state configuration * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows, how to communicate with RTC module PCA8565TS/1 via I2C bus. * For this purpose is used I2C driver created by Petr Stancik. Information from * RTC are sent using DMA via UART. The whole example consists from two parts. * Second part is PC application called GraphicalTerminalExample. This application * handles data from RTC and displays them. RTC also can be set using PC application. * Microcontroller receives data from PC application using DMA via UART. * Received data are written to RTC module. * * UART connection parameters: * Baud rate 19200b/s * 8 data bits * 1 stop bit * none parity * * For correct function of java application, it is required Java 1.8.0_40 * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3B 0N76P * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection: *                     UART connection *                     J14.1 connected to P12.6 (RX) *                     J13.1 connected to P12.7 (TX) * *                     RTC connection *                     RTC pin 4 - connected to any GROUND pin *                     RTC pin 8 - connected to any 3.3V pin *                     RTC pin 6 - connected to P8.10 (SCL - I2C clock) *                     RTC pin 5 - connected to P8.11 (SDA - I2C data) * ********************************************************************************

******************************************************************************** * Detailed Description: * * Purpose of the example is to show how to intentionally generate FCCU fault * causing reset either directly or by FOSU (simulating by non-handled FCCU * fault). Example configures FCCU, then an error is injected with using of * Noncritical Fault Fake register and after re-booting reset cause is evaluated. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection:  eSCI_A is USBtoUART bridge (connector J21) * ********************************************************************************

******************************************************************************** * Detailed Description: * Example of core watchdog implementation on Cobra 55. It executes on core 0 * All the functions are in the file "watchdog.c" *WatchDogCreate(delay, FirstTimeout, SecondTimeout) -> create/configure the wathdog timer *WatchDogStart() -> start the watchdog timer *WatchDogService() -> acknowledge the watchdog timer * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-416DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * DRUN with PLL 160MHz active. * Example of INTC configuration. PIT timer is triggering an * interrupt which is served in PIT ISR. * * ------------------------------------------------------------------------------ * Test HW:  MPC57xx * Maskset:  1N06M * Target :  Internal Flash * Fsys:     160 MHz PLL * ******************************************************************************** Revision History: 1.0     Oct-29-2014     b21190(Vlna Peter)  Initial Version 1.1    Nov-20-2014    b21190(Vlna Peter)  Modified for Cut2.0 1.2    Apr-23-2015    b21190(Vlna Peter)  Added INTC driver and PIT ISR 1.3    May-14-2015    b21190(Vlna Peter)  Dissabling SWT in Startup code 1.4     Jun-06-2017    b21190(Vlna Peter)  ported for MPC5746C *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, starts second core * initializes and display notice via UART terminal and then terminals ECHO. * * * Test HW:              MPC5688EVB * MCU:                   SPC5668GMMG 0N61C * Terminal:              19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:                   116 MHz * Debugger:             Lauterbach Trace32 *                             PeMicro USB-ML-PPCNEXUS * Target:                  RAM, internal_FLASH * EVB connection:   User LED 4 connected to pin P28-10 * *