Preliminary Updates to the Reference Manual - MCXNx4xRM

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Preliminary Updates to the Reference Manual - MCXNx4xRM

Preliminary Updates to the Reference Manual - MCXNx4xRM

The table below contains notable updates to the current release of the Reference Manual. The information provided here is preliminary and subject to change without notice.

Affected Modules Issue Summary Description  Date
MCXNx4x Pinout xlsx Attachment Defeature PF* pins Erroneous pinouts to PF* signals on ALT11 are removed. 

Before: 
joseph_hernandez_0-1709937861704.png

 

After: 

joseph_hernandez_1-1709937951033.png

 





01 March 2024
System Boot ROM API Missing Boot Modes sections in ROM API chapter of System Boot New sections added:

15.3 Boot modes

15.3.1 Master boot mode

Master boot mode supports the following boot devices:

  • Internal flash memory boot
  • FlexSPI NOR flash memory boot
  • SPI 1-bit NOR recovery boot
  • Secondary bootloader boot

Table 229. Image offsets for different boot media

 

Boot media

Image offset

Internal flash memory boot

0h

FlexSPI NOR flash memory boot

1000h

SPI 1-bit NOR recovery boot

0h

Secondary bootloader boot

0h

 

15.3.2 Secondary bootloader mode

 

The Secondary bootloader mode can be enabled by setting the CMPA[BOOT_SRC] as 2, the image loaded in the Bank1_IFR0 region (0x0100_8000 to 0x0100_FFFF) will be set as primary boot mode, and the secondary boot image will boot first after the device reset. The secondary boot image type can be plain, crc or signed image, but cannot set as the SB file.

 

Based on the CMPA[OEM_BANK1_IFR0_PROT](0x01004004[5:7]) setting, after the secondary boot image boot, the Bank1_IFR0 region will be configured with different MBC setting:

 

Lifecycle

CMPA[OEM_BANK1_IFR0_PROT]

Secondary bootloader mode MBC

IFR0 recovery boot MBC

Develop (0x3)

NA

GLABC0

GLBAC0

Develop2 (0x7),
In-field (0xF),
In-field Locked (0xCF),
Field Return OEM (1F)

0

GLBAC4

GLBAC4

 

1

GLBAC4

2

GLBAC2

3

GLBAC6

4

GLBAC4

5

6

7

 


 

01 March 2024
Input Multiplexing (INPUTMUX) Clarification to CMP trigger input registers

Update to the CMPx_TRIG Register function description for the following registers:
CMP0_TRIG (260h), CMP1_TRIG (4EOh), and CMP2_TRIG (500h)

 Before: 

Function

This register selects the CMPx trigger inputs

 

After:

Function

This register selects the CMPx SAMPLE/WINDOW input

01 March 2024

 

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Last update:
‎03-20-2024 02:17 PM
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