Introduction
The MCX N has a Programmable Logic Unit (PLU) capable of creating combinational and sequential logic circuits that operate independently of the cores. The PLU does this by preprogramming look up tables or LUTs that dictate the behavior of designated outputs for all inputs of the PLU. The features of the MCX N PLU module includes:
- An array of 26 inter-connectable, 5-input look-up table (LUT) elements.
- 4 flip-flops.
- Six primary inputs pins.
- Eight primary output pins.
- An external clock to drive the four flip-flops if a sequential network is implemented.
- Capability to generate interrupts and wakeup requests from Sleep and Deep Sleep modes.
Module architecture
The PLU is composed of 3 main elements: Look Up Tables (LUTs), Multiplexers and Flip Flops. Look Up Tables are used to create the actual logic of the PLU’s network, while multiplexers route these logic signals to and from other LUTs, as well as the PLU’s input and output pins. Flip Flops provide a method of gating logic signals from LUT elements to a shared clock input, adding a mechanism of synchronization and delay to the logic network.
Look Up Table (LUT)
The PLU module has 26 inter-connectable Look Up Tables (LUTs), which can implement any combinational function with up to five inputs at once. The LUTs work by storing a pre-programmed output for every combination of inputs. This allows the look up tables to reproduce a specific output of logical 0 or 1 as soon as the input is changed without any processing required. By interconnecting LUT elements with one another, more complex programmable networks can be achieved, providing functionality of many logic gates at once.
Multiplexers
The PLU module includes a variety of multiplexers that select the inputs and outputs for each Look Up Table (LUT) element. Each LUT element has 5 input multiplexers that route a signal to each of its 5 inputs. The available input signals for each LUT include:
- PLU Input pads.
- Other LUT element outputs.
- State Flip Flop outputs.
The PLU also has one output multiplexer for each PLU output pad (eight in total) that selects what Look-Up Table or Flip Flop state will drive each output pad.
Flip Flops
The final PLU element is a type D flip flop that allows for retention of data, providing the means for sequential logic circuits and simple state machines.
The PLU module has 4 flip flops that are connected to the outputs of LUTs[3:0] as well as the external PLU_CLKIN signal that is used for timing and synchronization between flip flops. In order to use the flip flop elements, a clock signal must be supplied via the PLU_CLKIN pad. Note that since the flip flops are directly connected to the outputs of the first 4 LUT elements, the corresponding LUT elements must be set up in order to use each Flip Flop element.
PLU Setup
The following steps must be done in order to achieve a logic network on the PLU module:
- Enable clocks for the PLU using the SYSCON_SYSAHBCLKCTRLx register and then toggle the PLU Reset bit from the SYSCON_PRESETCTRLx register.
- Assign pins using the PORTx_PCRn registers.
- Create logic network using the following steps:
- Write the logic behavior in the truth table register for each of the LUT elements that will be used.
- Program the input multiplexer registers to select the source of up to five inputs presented to each LUT.
- Program the output multiplexer register to select up to eight primary outputs from the PLU module.
- (Optional) Set the wakeup behavior by using the WAKEINT_CTRL register to select the outputs to be used as wakeup sources, as well as setting a deglitching method.
Creating logic networks
Basic logic gates
With a simple configuration of two inputs and one output on a single LUT element, all of the basic logic gates can be achieved. This would be achieved, for example, using a configuration of PLU_IN0 and PLU_IN1 pads as inputs and PLU_OUT0 pad as output for LUT0.
The first step of creating any logic network is to understand the truth table of the desired logic circuit. For a single AND gate using the previous configuration, the truth table would equate to the following:
|
# |
|
PLU_IN1 |
PLU_IN0 |
PLU_OUT0 |
|
0 |
|
0 |
0 |
0 |
|
1 |
|
0 |
1 |
0 |
|
2 |
|
1 |
0 |
0 |
|
3 |
|
1 |
1 |
1 |
The LUT would have to be set up in a way were the output is HIGH only when PLU_IN1 and PLU_IN0 are both HIGH, which is coincidentally the third combination of the LUT inputs for the previous truth table. Therefore, we need to program the LUT to output HIGH for combination #3. We can program this logic gate by writing a '1' on bit number 3 of the LUT’s truth table register. This way, when both LUT0 inputs are HIGH, the LUT element will “look up and find” a ‘1’, so it will output HIGH. On the other hand, for every other combination it will find a ‘0’ and output LOW.
|
Combination # (Input) |
Truth table register (Output) |
|
0 (0b00) |
0 |
|
1 (0b01) |
0 |
|
2 (0b10) |
0 |
|
3 (0b11) |
1 |
Taking this into account, it is easy to see that all the LUT element does is "look up" each combination of inputs on a predefined table to know what logic to output. This table is programmed via the 32 bit LUTa_TRUTH register for each LUT element. The 32 bit value required for the previous logic gate expressed in hexadecimal would then be as follows:
AND gate
|
LUT inputs[1:0] |
11 |
10 |
01 |
00 |
||
|
LUT0_TRUTH |
1 |
0 |
0 |
0 |
→ |
0x00000008 |
And, for the rest of the basic logic gates:
OR gate
|
LUT inputs[1:0] |
11 |
10 |
01 |
00 |
||
|
LUT0_TRUTH |
1 |
1 |
1 |
0 |
→ |
0x0000000E |
XOR gate
|
LUT inputs[1:0] |
11 |
10 |
01 |
00 |
||
|
LUT0_TRUTH |
0 |
1 |
1 |
0 |
→ |
0x00000006 |
NAND gate
|
LUT inputs[1:0] |
11 |
10 |
01 |
00 |
||
|
LUT0_TRUTH |
0 |
1 |
1 |
1 |
→ |
0x00000007 |
NOR gate
|
LUT inputs[1:0] |
11 |
10 |
01 |
00 |
||
|
LUT0_TRUTH |
0 |
0 |
0 |
1 |
→ |
0x00000001 |
XNOR gate
|
LUT inputs[1:0] |
11 |
10 |
01 |
00 |
||
|
LUT0_TRUTH |
1 |
0 |
0 |
1 |
→ |
0x00000009 |
NOT gate
|
LUT inputs[0] |
1 |
0 |
||
|
LUT0_TRUTH |
0 |
1 |
→ |
0x00000001 |
Buffer gate
|
LUT inputs[0] |
1 |
0 |
||
|
LUT0_TRUTH |
1 |
0 |
→ |
0x00000002 |
Note that the truth table value for a NOR gate and a NOT gate is the same in this case, as both require an output of ‘1’ for the first combination of inputs and ‘0’ for the rest. This demonstrates how the PLU does not actually create an array of logic gates but rather, simply outputs predefined values from a table of all possible combinations of inputs.
The previous tables show the register values to achieve all of the basic logic gates with the previous setup of LUT0. However, in order to achieve this configuration with input pins PLU_IN0 and PLU_IN1 as well as output pin PLU_OUT0, the multiplexers would have to be set up in the following manner:
In order to achieve this, pin PLU_IN0 must be routed as input[0] of LUT0 and PLU_IN1 as input[1] of LUT0. Additionally, the output of LUT0 will be routed to the PLU_OUT0 pad. This configuration to set up both input sources, route the output source and write the truth table register to result in an AND gate can be achieved with the following code:
/* Select input pin PLU_IN0 as LUT Input 0 (Input MUX0) for LUT0 on module PLU0 */
PLU_SetLutInputSource(PLU0, kPLU_LUT_0, kPLU_LUT_IN_0, kPLU_LUT_IN_SRC_PLU_IN_0);
/* Select input pin PLU_IN1 as LUT Input 1 (Input MUX1) for LUT0 on module PLU0 */
PLU_SetLutInputSource(PLU0, kPLU_LUT_0, kPLU_LUT_IN_1, kPLU_LUT_IN_SRC_PLU_IN_1);
/* Set Truth Table 0x08 for LUT element 0 on module PLU0 */
PLU_SetLutTruthTable(PLU0, kPLU_LUT_0, 0x08); // This will result in an AND gate
/* Select LUT0 output as driver for PLU_OUT0 pin on module PLU0 */
PLU_SetOutputSource(PLU0, kPLU_OUTPUT_0, kPLU_OUT_SRC_LUT_0);
Conclusion
The PLU module of the MCX N is modest when it comes to the complexity of the inner components as it is only made up from a series of look-up tables, multiplexers and flip flops. In spite of that, more elaborate and powerful logic networks can be achieved from those basic elements, providing on-chip solutions to many essential digital circuits and avoiding the need of external components for these digital applications. Not only that, but its interruption and wake up capabilities also enable the PLU to be a simple but effective addition to many low power applications. The PLU’s flexibility and built-in features enable this module to be a very effective addition to the MCX N series of MCUs that should not be overlooked. More information as well as example codes for combinational, sequential, and low-power applications can be found on the full article on Application Code Hub.
