Overview The purpose of this document is to demonstrate how to enable USB Bluetooth Dongle based on i.MX6 Android ICS. Hardware i.MX6Dual/Quad or i.MX6DualLite SabreSD board USB Bluetooth Dongle Software i.MX6DQ/MX6DL Android ICS R13.4 or R13.4.1 Release Changes 0001-enable-usb-dongle-BT.patch: Update bluedroid to disable RFKILL and enable HCIATTACH property for USB Bluetooth Dongle. diff --git a/bluedroid/Android.mk b/bluedroid/Android.mk index 17df49b..569be44 100644 --- a/bluedroid/Android.mk +++ b/bluedroid/Android.mk @@ -5,6 +5,13 @@ LOCAL_PATH:= $(call my-dir) include $(CLEAR_VARS) +ifeq ($(BOARD_BLUETOOTH_DOES_NOT_USE_RFKILL),true) +  LOCAL_CFLAGS := $(LOCAL_CFLAGS) -DBLUETOOTH_DOES_NOT_USE_RFKILL +endif + +ifeq ($(BOARD_BLUETOOTH_USES_HCIATTACH_PROPERTY),true) +  LOCAL_CFLAGS := $(LOCAL_CFLAGS) -DBLUETOOTH_HCIATTACH_USING_PROPERTY +endif LOCAL_SRC_FILES := \   bluetooth.c diff --git a/bluedroid/bluetooth.c b/bluedroid/bluetooth.c index 4cc9204..2636942 100644 --- a/bluedroid/bluetooth.c +++ b/bluedroid/bluetooth.c @@ -44,7 +44,7 @@ static int rfkill_id = -1; static char *rfkill_state_path = NULL; - +#ifndef BLUETOOTH_DOES_NOT_USE_RFKILL static int init_rfkill() {      char path[64];      char buf[16]; @@ -135,6 +135,7 @@ out:      if (fd >= 0) close(fd);      return ret; } +#endif static inline int create_hci_sock() {      int sk = socket(AF_BLUETOOTH, SOCK_RAW, BTPROTO_HCI); @@ -151,13 +152,20 @@ int bt_enable() {      int ret = -1;      int hci_sock = -1;      int attempt; - +#ifndef BLUETOOTH_DOES_NOT_USE_RFKILL      if (set_bluetooth_power(1) < 0) goto out; - +#endif +#ifndef BLUETOOTH_HCIATTACH_USING_PROPERTY      LOGI("Starting hciattach daemon"); -    if (property_set("ctl.start", "hciattach") < 0) { +    if (property_set("ctl.start", "hciattach") < 0) +#else +    if (property_set("bluetooth.hciattach", "true") < 0) +#endif +    {          LOGE("Failed to start hciattach"); +#ifndef BLUETOOTH_DOES_NOT_USE_RFKILL          set_bluetooth_power(0); +#endif          goto out;      } @@ -186,14 +194,18 @@ int bt_enable() {          if (property_set("ctl.stop", "hciattach") < 0) {              LOGE("Error stopping hciattach");          } +#ifndef BLUETOOTH_DOES_NOT_USE_RFKILL          set_bluetooth_power(0); +#endif          goto out;      }      LOGI("Starting bluetoothd deamon");      if (property_set("ctl.start", "bluetoothd") < 0) {          LOGE("Failed to start bluetoothd"); +#ifndef BLUETOOTH_DOES_NOT_USE_RFKILL          set_bluetooth_power(0); +#endif          goto out;      } @@ -222,14 +234,20 @@ int bt_disable() {      ioctl(hci_sock, HCIDEVDOWN, HCI_DEV_ID);      LOGI("Stopping hciattach deamon"); -    if (property_set("ctl.stop", "hciattach") < 0) { +#ifndef BLUETOOTH_HCIATTACH_USING_PROPERTY +    if (property_set("ctl.stop", "hciattach") < 0) +#else +   if (property_set("bluetooth.hciattach", "false") < 0) +#endif +   {          LOGE("Error stopping hciattach");          goto out;      } - +#ifndef BLUETOOTH_DOES_NOT_USE_RFKILL      if (set_bluetooth_power(0) < 0) {          goto out;      } +#endif      ret = 0; out: @@ -246,9 +264,10 @@ int bt_is_enabled() {      // Check power first +#ifndef BLUETOOTH_DOES_NOT_USE_RFKILL      ret = check_bluetooth_power();      if (ret == -1 || ret == 0) goto out; - +#endif      ret = -1;      // Power is on, now check if the HCI interface is up 0002-usb_dongle-on-SabreSD.patch: Update MX6 board configuration files to enable USB Bluetooth dongle feature. diff --git a/imx6/imx6.mk b/imx6/imx6.mk @@ -63,6 +63,7 @@ PRODUCT_PACKAGES += \ PRODUCT_PACKAGES += \   audio.tinyalsa.freescale   \   audio.legacy.freescale    \ +        audio.a2dp.default                      \   alsa_aplay                \   alsa_arecord    \   alsa_amixer        \ diff --git a/imx6/sabresd/SabreSDBoardConfigComm.mk b/imx6/sabresd/SabreSDBoardConfigComm.mk index 03d8ce5..1a8a6bd 100755 --- a/imx6/sabresd/SabreSDBoardConfigComm.mk +++ b/imx6/sabresd/SabreSDBoardConfigComm.mk -# atheros 3k BT -BOARD_USE_AR3K_BLUETOOTH := true +# Default use USB BT dongle for imx6, so should enable below +BOARD_BLUETOOTH_DOES_NOT_USE_RFKILL := true +BOARD_BLUETOOTH_USES_HCIATTACH_PROPERTY := true + USE_ION_ALLOCATOR := false USE_GPU_ALLOCATOR := true diff --git a/imx6/sabresd/init.rc b/imx6/sabresd/init.rc index ff9f0ff..f127177 100755 --- a/imx6/sabresd/init.rc +++ b/imx6/sabresd/init.rc @@ -84,9 +84,12 @@ on boot      # No bluetooth hardware present      setprop hw.bluetooth 0      setprop wlan.interface wlan0 +    setprop hw.bluetooth 1 diff --git a/imx6/sabresd/required_hardware.xml b/imx6/sabresd/required_hardware.xml index c9a2271..f7db37b 100644 --- a/imx6/sabresd/required_hardware.xml +++ b/imx6/sabresd/required_hardware.xml @@ -22,6 +22,7 @@      <feature name="android.hardware.camera.flash" />      <feature name="android.hardware.camera.front" />      <feature name="android.hardware.location" /> +    <feature name="android.hardware.bluetooth" />      <feature name="android.hardware.location.network" />      <feature name="android.hardware.location.gps" />      <feature name="android.hardware.telephony" />

The i.MX6Q-SDP is used to stream OV5642 parallel camera video encoded as JPEG using the hardware CODEC engine to a Linux client which decodes and displays on the screen.

Abstract This is a small tutorial about running a simple OpenCL application in an i.MX6Q. It covers a very small introduction to OpenCL, the explanation of the code and how to compile and run it.   Requirements   Any i.MX6Q board. Linux BSP with the gpu-viv-bin-mx6q package (for instructions on how to build the BSP, check the BSP Users Guide)   OpenCL overview   OpenCL allows any program to use the GPGPU features of the GC2000 (General-Purpose Computing on Graphics Processing Units) that means to use the i.MX6Q GPU processing power in any program.   OpenCL uses kernels which are functions that can be executed in the GPU. These functions must be written in a C99 like code. In our current GPU there is no scheduling so each kernel will execute in a FIFO fashion. iMx6Q GPU is OpenCL 1.1 EP conformant. The Code   The example provided here performs a simple addition of arrays in the GPU. The header needed to use openCL is cl.h and is under /usr/include/CL in your BSP rootfs when you install the gpu-viv-bin-mx6q package. The header is typically included like this: #include <CL/cl.h> The libraries needed to link the program are libGAL.so and libOpenCL.so those are under /usr/lib in your BSP rootfs.   For details on the OpenCL API check the khronos page: http://www.khronos.org/opencl/ Our kernel source is as follows: __kernel void VectorAdd(__global int* c, __global int* a,__global int* b) {      // Index of the elements to add      unsigned int n = get_global_id(0);      // Sum the nth element of vectors a and b and store in c      c[n] = a[n] + b[n]; } The kernel is declared with the signature     __kernel void VectorAdd(__global int* c, __global int* a,__global int* b).   This takes vectors a and b as arguments adds them and stores the result in the vector c. It looks like a normal C99 method except for the keywords kernel and global. kernel tells the compiler this function is a kernel, global tells the compiler this attributes are of global address space. get_global_id built-in function   This function will tell us to which index of the vector this kernel corresponds to. And in the last line the vectors are added. Below is the full source code commented. //************************************************************ // Demo OpenCL application to compute a simple vector addition // computation between 2 arrays on the GPU // ************************************************************ #include <stdio.h> #include <stdlib.h> #include <CL/cl.h> // // OpenCL source code const char* OpenCLSource[] = { "__kernel void VectorAdd(__global int* c, __global int* a,__global int* b)", "{", " // Index of the elements to add \n", " unsigned int n = get_global_id(0);", " // Sum the nth element of vectors a and b and store in c \n", " c[n] = a[n] + b[n];", "}" }; // Some interesting data for the vectors int InitialData1[20] = {37,50,54,50,56,0,43,43,74,71,32,36,16,43,56,100,50,25,15,17}; int InitialData2[20] = {35,51,54,58,55,32,36,69,27,39,35,40,16,44,55,14,58,75,18,15}; // Number of elements in the vectors to be added #define SIZE 100 // Main function // ************************************************************ int main(int argc, char **argv) {      // Two integer source vectors in Host memory      int HostVector1[SIZE], HostVector2[SIZE];      //Output Vector      int HostOutputVector[SIZE];      // Initialize with some interesting repeating data      for(int c = 0; c < SIZE; c++)      {           HostVector1[c] = InitialData1[c%20];           HostVector2[c] = InitialData2[c%20];           HostOutputVector[c] = 0;      }      //Get an OpenCL platform      cl_platform_id cpPlatform;      clGetPlatformIDs(1, &cpPlatform, NULL);      // Get a GPU device      cl_device_id cdDevice;      clGetDeviceIDs(cpPlatform, CL_DEVICE_TYPE_GPU, 1, &cdDevice, NULL);      char cBuffer[1024];      clGetDeviceInfo(cdDevice, CL_DEVICE_NAME, sizeof(cBuffer), &cBuffer, NULL);      printf("CL_DEVICE_NAME: %s\n", cBuffer);      clGetDeviceInfo(cdDevice, CL_DRIVER_VERSION, sizeof(cBuffer), &cBuffer, NULL);      printf("CL_DRIVER_VERSION: %s\n\n", cBuffer);      // Create a context to run OpenCL enabled GPU      cl_context GPUContext = clCreateContextFromType(0, CL_DEVICE_TYPE_GPU, NULL, NULL, NULL);      // Create a command-queue on the GPU device      cl_command_queue cqCommandQueue = clCreateCommandQueue(GPUContext, cdDevice, 0, NULL);      // Allocate GPU memory for source vectors AND initialize from CPU memory      cl_mem GPUVector1 = clCreateBuffer(GPUContext, CL_MEM_READ_ONLY |      CL_MEM_COPY_HOST_PTR, sizeof(int) * SIZE, HostVector1, NULL);      cl_mem GPUVector2 = clCreateBuffer(GPUContext, CL_MEM_READ_ONLY |      CL_MEM_COPY_HOST_PTR, sizeof(int) * SIZE, HostVector2, NULL);      // Allocate output memory on GPU      cl_mem GPUOutputVector = clCreateBuffer(GPUContext, CL_MEM_WRITE_ONLY,      sizeof(int) * SIZE, NULL, NULL);      // Create OpenCL program with source code      cl_program OpenCLProgram = clCreateProgramWithSource(GPUContext, 7, OpenCLSource, NULL, NULL);      // Build the program (OpenCL JIT compilation)      clBuildProgram(OpenCLProgram, 0, NULL, NULL, NULL, NULL);      // Create a handle to the compiled OpenCL function (Kernel)      cl_kernel OpenCLVectorAdd = clCreateKernel(OpenCLProgram, "VectorAdd", NULL);      // In the next step we associate the GPU memory with the Kernel arguments      clSetKernelArg(OpenCLVectorAdd, 0, sizeof(cl_mem), (void*)&GPUOutputVector);      clSetKernelArg(OpenCLVectorAdd, 1, sizeof(cl_mem), (void*)&GPUVector1);      clSetKernelArg(OpenCLVectorAdd, 2, sizeof(cl_mem), (void*)&GPUVector2);      // Launch the Kernel on the GPU      // This kernel only uses global data      size_t WorkSize[1] = {SIZE}; // one dimensional Range      clEnqueueNDRangeKernel(cqCommandQueue, OpenCLVectorAdd, 1, NULL,      WorkSize, NULL, 0, NULL, NULL);      // Copy the output in GPU memory back to CPU memory      clEnqueueReadBuffer(cqCommandQueue, GPUOutputVector, CL_TRUE, 0,      SIZE * sizeof(int), HostOutputVector, 0, NULL, NULL);      // Cleanup      clReleaseKernel(OpenCLVectorAdd);      clReleaseProgram(OpenCLProgram);      clReleaseCommandQueue(cqCommandQueue);      clReleaseContext(GPUContext);      clReleaseMemObject(GPUVector1);      clReleaseMemObject(GPUVector2);      clReleaseMemObject(GPUOutputVector);      for( int i =0 ; i < SIZE; i++)           printf("[%d + %d = %d]\n",HostVector1[i], HostVector2[i], HostOutputVector[i]);      return 0; } How to compile in Host   Get to your ltib folder and run $./ltib m shell This way you will be using the cross compiler ltib uses and the default include and lib directories will be the ones in your bsp. Then run LTIB> gcc cl_sample.c -lGAL -lOpenCL -o cl_sample. How to run in the i.MX6Q   Insert the GPU module root@freescale/home/user $ modprobe galcore Copy the compiled CL program and then run root@freescale /home/user$ ./cl_sample References   [1] ttp://www.khronos.org/opencl/ Original Attachment has been moved to: libOpenCL.so.zip Original Attachment has been moved to: libCLC_Android.so.zip Original Attachment has been moved to: libOpenCL_Android.so.zip Original Attachment has been moved to: libCLC.so.zip

Issue Description When running Android R10.4 on MX51 BBG, the system can not resume sometimes by following the test steps: 1) Enable CLAA-WVGA lcd panel - single display. 2) Play a video in Gallery. 3) Press power key to suspend the system. 4) Press power key to resume the system. 5) Do 3) and 4) continuously. Debug Details When adding the following debug information into vpu_resume function in file drivers/mxc/vpu/mxc_vpu.c, the system gets hang into while loop with the log "VPU Blocking 1**************": static int vpu_resume(struct platform_device *pdev) {         int i;                 WRITE_REG(BITVAL_PIC_RUN, BIT_INT_ENABLE);                 WRITE_REG(0x1, BIT_BUSY_FLAG);                 WRITE_REG(0x1, BIT_CODE_RUN);                 while (READ_REG(BIT_BUSY_FLAG)) {                           printk("VPU Blocking 1**************\r\n");                }; } Root Cause In some use cases,  VPU power gating didn't happen after vpu_suspend() returned successfully because some other devices refused to suspend or other reasons. So vpu_resume() ran FW init code when VPU was idle instead of power off, which could keep BIT_BUSY_FLAG always be 1. Solution In vpu_resume(), if VPU PC is not 0, which means VPU is still running, skip running FW init code. See attached patch based on R10.4.

Overview This purpose of this document is to introduce how to support recovery mode for POR reboot event based on MX6 Android R13.4.1. Background If you boot Android R13.4.1 on MX6 SabreSD board, the reboot reason is Watchdog. But if the reboot reason is changed from Watchdog to POR, the recovery mode is failed to enter after factory reset. In R13.4.1, the bit 8 of SRC_GPR10 is used as the persistent bit of recovery mode. This bit is expected to be kept after reboot so that U-boot can use this bit to distinguish what mode should enter. However all SRC registers will be reset on POR sequence according to i.MX6DQRM Section 59.4.1.2.3 IPP_RESET_B (POR). So when the reboot reason is POR, the persistent bit of recovery mode is cleared even if the software set it before reboot. It causes the bootloader won't enter recovery mode after reboot. Software Changes According to i.MX6DQRM, the SNVS_LP General Purpose Register provides a 32 bit read write register, which can be used by any application for retaining 32 bit data during a power-down mode. So to support recovery mode for POR event, the SNVS_LP register can be used to store the persistent bit of recovery mode. The following changes are reqiured to apply (See patches.tar.gz) Apply for Uboot patch bootable/bootloader/uboot-imx/0001-ENGR00235817-mx6-use-SNVS-LPGPR-register-to-store-bo.patch. diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c index 257c930..bd47130 100644 --- a/cpu/arm_cortexa8/mx6/generic.c +++ b/cpu/arm_cortexa8/mx6/generic.c @@ -1146,14 +1146,14 @@ int check_and_clean_recovery_flag(void) {   int flag_set = 0;   u32 reg; - reg = readl(SRC_BASE_ADDR + SRC_GPR10); + reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR);   flag_set = !!(reg & ANDROID_RECOVERY_BOOT);   /* clean it in case looping infinite here.... */   if (flag_set) {    reg &= ~ANDROID_RECOVERY_BOOT; -  writel(reg, SRC_BASE_ADDR + SRC_GPR10); +  writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR);   }   return flag_set; @@ -1168,14 +1168,15 @@ int fastboot_check_and_clean_flag(void) {   int flag_set = 0;   u32 reg; - reg = readl(SRC_BASE_ADDR + SRC_GPR10); + + reg = readl(SNVS_BASE_ADDR + SNVS_LPGPR);   flag_set = !!(reg & ANDROID_FASTBOOT_BOOT);   /* clean it in case looping infinite here.... */   if (flag_set) {    reg &= ~ANDROID_FASTBOOT_BOOT; -  writel(reg, SRC_BASE_ADDR + SRC_GPR10); +  writel(reg, SNVS_BASE_ADDR + SNVS_LPGPR);   }   return flag_set; diff --git a/include/asm-arm/arch-mx6/mx6.h b/include/asm-arm/arch-mx6/mx6.h index efb90c2..45381e2 100644 --- a/include/asm-arm/arch-mx6/mx6.h +++ b/include/asm-arm/arch-mx6/mx6.h @@ -732,6 +732,8 @@ #define SRC_GPR9  0x40 #define SRC_GPR10  0x44 +#define SNVS_LPGPR              0x68 + /* Get Board ID */ #define board_is_rev(system_rev, rev) (((system_rev & 0x0F00) == rev) ? 1 : 0) #define chip_is_type(system_rev, rev) \ Apply for kernel patch kernel_imx/0001-ENGR00235817-mx6-use-SNVS-LPGPR-register-to-store-bo.patch diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index 6d24f22..61649c5 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -563,7 +563,7 @@ void mxc_clear_mfgmode(void) #endif #ifdef CONFIG_MXC_REBOOT_ANDROID_CMD -/* This function will set a bit on SRC_GPR10[7-8] bits to enter +/* This function will set a bit on SNVS_LPGPR[7-8] bits to enter   * special boot mode.  These bits will not clear by watchdog reset, so   * it can be checked by bootloader to choose enter different mode.*/ @@ -574,18 +574,18 @@ void do_switch_recovery(void) {   u32 reg; - reg = __raw_readl(SRC_BASE_ADDR + SRC_GPR10); + reg = __raw_readl(MX6Q_SNVS_BASE_ADDR + SNVS_LPGPR);   reg |= ANDROID_RECOVERY_BOOT; - __raw_writel(reg, SRC_BASE_ADDR + SRC_GPR10); + __raw_writel(reg, MX6Q_SNVS_BASE_ADDR + SNVS_LPGPR); } void do_switch_fastboot(void) {   u32 reg; - reg = __raw_readl(SRC_BASE_ADDR + SRC_GPR10); + reg = __raw_readl(MX6Q_SNVS_BASE_ADDR + SNVS_LPGPR);   reg |= ANDROID_FASTBOOT_BOOT; - __raw_writel(reg, SRC_BASE_ADDR + SRC_GPR10); + __raw_writel(reg, MX6Q_SNVS_BASE_ADDR + SNVS_LPGPR); } #endif diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h index 48b04b1..bb22de0 100644 --- a/arch/arm/plat-mxc/include/mach/mx6.h +++ b/arch/arm/plat-mxc/include/mach/mx6.h @@ -302,6 +302,8 @@ #define SRC_GPR9   0x40 #define SRC_GPR10   0x44 +#define SNVS_LPGPR   0x68 + /* GPC offsets */ #define MXC_GPC_CNTR_OFFSET  0x0

Overview i.MX6Dual/Quad and i.MX6DualLite supports 32-bit and 64-bit DDR3. Freescale i.MX6 SabreSD board deploys 64bit DDR3 and 64bit DDR3 script is delivered into Linux/Android Software release. This document introduces how to create i.MX6 32bit DDR script based on 64bit DDR script when deploying 32bit DDR on customized board. Changes Set the DSE field in the following iomux registers to 0 - disable unused IO pad to save power: IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 IOMUXC_SW_PAD_CTL_GRP_B4DS IOMUXC_SW_PAD_CTL_GRP_B5DS IOMUXC_SW_PAD_CTL_GRP_B6DS IOMUXC_SW_PAD_CTL_GRP_B7DS IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 Update MMDC registers to reflect 32bit DDR changes: MMDC0_MDASP: Update CS0_END if CS size is changed. MMDC0_MDCTL: set DSIZ to 32 bit MMDC1_MPODTCTRL: Set it as 0 and disable the odt of higher byte Follow "i.MX 6 Series DDR Calibration" Application note to calibrate DDR parameters. Reference One example about 32bit DDR script is located under uboot-imx git ( File: board/freescale/mx6q_sabresd/flash_header.S). Open it and you can see the following script: #if defined CONFIG_MX6DL_DDR3 #if defined CONFIG_DDR_32BIT ... #endif You can refer to it and create your 32bit DDR script.

Starting from $52, the VAR-SOM-MX6 sets the bar for unparalleled design flexibility. The VAR-SOM-MX6 ensures scalable and simplified development, while also extending the product lifecycle. Thanks to four CPU core assembly options, customers can apply a single System on Module in a broad range of applications to achieve short time-to-market for their current innovations, while still accommodating potential R&D directions and marketing opportunities.     VAR-SOM-MX6 CPU: Freescale iMX6 Key features include: Freescale i.MX6 1.2GHz Quad / Dual / Single core Cortex-A9       2GB DDR3, 1GB SLC NAND Flash       Full HD 1080p video encoding/decoding capability       Vivante GPU providing 2D/3D acceleration       Simultaneous multiple display support       Gigabit Ethernet       TI WiLink™ 6.0 single-chip connectivity solution (Wi-Fi, Bluetooth®)       PCI-Express 2.0, S-ATA 3.0       Camera interface       USB 2.0: Host, OTG       Audio In/Out       Dual CAN Bus This versatile solution's -40 to 85°C temperature range and Dual CAN support is ideal for industrial applications, while 1080p video and graphics accelerations make it equally suitable for intensive multimedia applications. The impressive scalability of the VAR-SOM-MX6 satisfies the needs of the most demanding future application requirements whether faster processing power, enhanced algorithms or improved graphics and video performance to name just a few. The VAR-SOM-MX6 is an all-round solution with broad connectivity and sophisticated video and acceleration graphic capabilities, delivering a range of middle to high end assembly options all from the same product. For more details, please see VAR-SOM-MX6 CPU: Freescale iMX6

The attached patch applies to iMX6_Platform_SDK for i.MX6 Dual and Quad and brings 2 additional SDMA memory to memory scripts: fixed destination address, increasing source address fixed source address, increasing destination address. With this patch, the new scripts are also integrated in the SDMA Test menu of the Platform SDK. I created these scripts starting from the ROM script ap_to_ap. In order to dump the content of the SDMA ROM, I used mxc_printSDMAcontext function which is also included in the attached patch and can be invoked when needed.

Apply this patch into the LTIB folder.

Some i.MX25 customers reported an issue for the GPT timer, when using 120MHz (240MHz UPLL divided 2) clock source as the GPT per_clk, the timer will not be increased all the time in free-run mode. If using 66.5MHz IPG clock and 133MHz PER clock as the clock source, there are no such issue. There are 4 test cases in the attached test code. Case 0: in CCM_MCR, set bit 5 as 0 for 133MHz HCLK as the gpt_per_clk source;  in GPT_CR bit[8:6], set 0b001 ipg_clk (66.5MHz). There is no issue, the GPT counter is fixed at 4 between old_cnt and new_cnt. Case 1: in CCM_MCR, set bit 5 as 0 for 133MHz HCLK as the gpt_per_clk source;  in GPT_CR bit[8:6], set 0b010 ipg_clk_highfreq (133MHz). There is no issue, the GPT counter is fixed at 8 between old_cnt and new_cnt. Case 2: in CCM_MCR, set bit 5 as 1 for 240MHz UPLL divided by 2 as the gpt_per_clk source;  in GPT_CR bit[8:6], set 0b001 ipg_clk (60MHz). There is no issue, the GPT counter is fixed at 4 between old_cnt and new_cnt. Case 3: in CCM_MCR, set bit 5 as 0 for 240MHz UPLL divided by 2 as the gpt_per_clk source;  in GPT_CR bit[8:6], set 0b010 ipg_clk_highfreq (120MHz). There is issue, the GPT counter is not a fixed value between old_cnt and new_cnt, and sometimes it will be negative. Count 9874: 4 old_cnt: 0x188849dc new_cnt: 0x188849e0 Count 9877: 12 old_cnt: 0x18918400 new_cnt: 0x1891840c Count 9915: 4 old_cnt: 0x189aea90 new_cnt: 0x189aea94 Count 9937: -12 old_cnt: 0x18a42458 new_cnt: 0x18a4244c Count 9967: 4 old_cnt: 0x18adb17c new_cnt: 0x18adb180 In fact, it is not an issue, when using UPLL as the GPT clock source, the maxim frequency should be 60MHz. That's why all other three test case is OK and it only failed on this case.

In L2.6.35_11.09.01_ER BSP Uboot, the MMC driver was updated, but there is issue that when you modified some uboot code, the MMC driver has chance to fail to work. The root cause is that mmc->has_init hasn't been initialized. Sometimes the value will be not zero, then mmc driver will be skipped for initialization. Attached is the patch to fix this issue in L2.6.35_11.09.01_ER BSP Uboot.

This is a generic script which flashes a Linux System (U-boot, uImage and root filesystem) into a SD card. Steps:     1. Download the script into a Linux system     2. Make the script executable (chmod +x mk_mx_sd)     3. Run it with '-H' to know its usage.     4. Run the script with real parameters, specifying the paths for U-boot, uImage and the root filesystem as seen above     5. Plug the SD into your target, boot the board and change the corresponding U-boot variables $ IMAGE=/data/BSP/L2.6.35_11.09.01_ER/L2.6.35_11.09.01_ER_images_MX5X $ ./mk_mx_sd  -d /dev/sdc \                       -u $IMAGE/u-boot-mx53-loco.bin \                       -k $IMAGE/uImage \                       -r $IMAGE/rootfs     6. In case you only want to flash a single binary (like U-boot), just specify the U-boot parameter (-u)

This link contains the scripts, U-boot commands, and patch code shown on the application note AN5409 titled 'i.MX6 Dual/6 Quad Power Consumption Measurement'.

In FSL i.MX53 reference design, it is configured as: static struct mxc_audio_platform_data sgtl5000_data = { .ssi_num = 1, .src_port = 2, .ext_port = 5, .hp_irq = gpio_to_irq(HEADPHONE_DEC_B), .hp_status = headphone_det_status, .init = mxc_sgtl5000_init, .ext_ram_rx = 1, }; by default. If change the configuration to be : static struct mxc_audio_platform_data sgtl5000_data = { .ssi_num = 0, .src_port = 1, .ext_port = 5, .hp_irq = gpio_to_irq(HEADPHONE_DEC_B), .hp_status = headphone_det_status, .init = mxc_sgtl5000_init, .ext_ram_rx = 1, }; There will prompt "imx_ssi_irq mxc_ssi SISR 8003a3 SIER 180100 fifo_errs=XXXX"  constantly, and audio is greatly distorted. The root cause of this issue is that SSI1/3 use SDMA, and also use IPMUX, but there is not the clock dependency between SDMA and IPMUX, so sometimes IPMUX clock is closed automatically. The attached patch may fix this issue. NOTE: If use SSI2 .ssi_num = 1,             .src_port = 2, If use SSI1 .ssi_num = 0,             .src_port = 1,

Introduction The SABRE Board for Smart Devices Based on the i.MX 6 Series is an evalutaion board featuring the i.MX6 Quad Core Cortex-A9 processor. Freescale ported the Linux Operating System (as of this writing version 3.0.35) and the Board Support Package (BSP) containing the Linux Kernel, build system called LTIB, GCC compiler tools, boot loader, u-boot, and root file system is available for download, install, and build. LTIB is a perl script and is the acroynm for Linux Target Image Builder. This document describes setting up a CentOS 6.3 64-bit host in a virtual machine for using the BSP and running the images on i.MX6Q-SDB evaluation board. References Description Reference CentOS 6.3 LiveCD installed in a virtual machine from virtual box. http://centos.org CentOS-6.3-x86_64-LiveCD.iso 9953ff1cc2ef31da89a0e1f993ee6335 Virtual Box - A Virtual Machine used for creating the CentOS host. Virtual Box installed on Windows 7 64-bit Pro, then create the VM. Allocated 20 GB Hard disk and 1 MB RAM. The steps for installations are found at the virtual box web site. http://www.virtualbox.org The BSP provides, a build system called ltib, GNU tools, U-Boot, Linux Kernel, and root file system: Download archive from http://freescale.com/sabresdb L3.0.35_12.09.01.0_GA_source.tar.gz 5ab4198278e92e03be74ca602227afad Document Conventions Bold lines are Linux commands and edits run on CentOS. The '$' indicates running the command as a regular user The '#' indicates running the command as root user. CentOS Host Setup For this example a virtual machine is used, however a dedicated PC running only CentOS linux could be used. 1. Add user login to sudo'ers file           Login as user root and run the visudo command          # visudo           Add the following line and save the file:           user     ALL=(ALL)     ALL 2. Update the system packages:           $ sudo yum udpate 3. Install package for "ltib" operations:           $ sudo yum install make gcc gcc-c++ kernel-devel bison libuuid-devel ncurses-devel zlib-devel lzo-devel intltool libtool tcl rpm-build perl-ExtUtils-MakeMaker ld-linux.so.2 zlib-1.2.3-27.el6.i686 4. Update sudo'ers file for supporting ltib rpm           $ sudo visudo           Add the following line and save the file:           user     ALL=NOPASSWD: /bin/rpm,/opt/freescale/ltib/usr/bin/rpm Install BSP The sources are in a tar gziped archive file which is downloaded from http://freescale.com/sabresdb, selecting the Software & Tools tab then expanding Run-time Software in the middle of the page. A free login is required for download which can be registered for by selecting the Login at the top right of the freescale.com page. Once downloaded, verify the md5 checksum (see references above for the value). $ mkdir ~/imx6 $ tar -zxf L3.0.35_12.09.01.01_GA_source.tar.gz -C ~/imx6 $ cd ~/imx6/*source $ ./install Read and accept the licensing information. Choose a directory to install too, for this example entered .. which is the parent directory. Build the i.MX6Q SDB $ cd ~/imx6/ltib $ ./ltib After some time (depends on how fast your host computer is) the menuing system is shown which allows you to select build configurations. The second screen selects the development platform which is imx6q for the SDB. For this example the Min profile is chosen which is the default. Use the arrow keys to move and the enter key to select. The space bar selects/deselects an entry. Use the right arrow key to move to <Exit> and press the enter key. The save dialog box is presented, save. The next menu is the iMX6x Base Boards which leaving all as default except for the U-boot board selection which is mx6q_sabresd for the SDB. Save and exit. Images When ltib completes, the images are found in <ltib>/rootfs/boot. Bootloader = u-boot.bin Linux Kernel = uImage File system = </ltib>/rootfs

prebuilt image: image_imx-android-13.4.1_6qsabresd u-boot variables: bootcmd=booti mmc2 bootargs=console=ttymxc0,115200 init=/init androidboot.console=ttymxc0 video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24

When flashing a Linux System on a SD card using the script mk_mx28_sd on a Ubuntu 12.04 host, one needs to modify it so partitions are created correctly.  Just follow these steps on the console: $ cd $SDK/L2.6.35_10.12.01_SDK_scripts $ cat > first_partition_sector.patch << EOF diff -Naur a/mk_mx28_sd b/mk_mx28_sd --- a/mk_mx28_sd        2010-10-06 09:47:42.000000000 -0500 +++ b/mk_mx28_sd        2012-11-30 13:38:34.508199154 -0600 @@ -178,7 +178,7 @@ n p 1 -1 +2048 +32M t b EOF $ patch -p1 < first_partition_sector.patch then, you can run the mk_mx28_sd command again with the device as parameter                $ cd $LIB $ export PATH=$PATH:$SDK/L2.6.35_10.12.01_SDK_scripts $ mk_mx28_sd /dev/$SDX

Join FSL-community-bsp project: https://lists.yoctoproject.org/listinfo/meta-freescale In order to test Yocto Project for i.MX6 or any other supported board please follow the instructions pointed by FSL Community BSP. In order to download the source code, please follow this instructions FSL Community BSP. With the downloaded source code, you can follow the steps from this training: Yocto Training - HOME If you face a problem, please, send an email to https://lists.yoctoproject.org/listinfo/meta-freescale This page made sense when there was not other tutorial to point people on how to download and build the very first image using Yocto Project tools for i.MX family boards. Today, FSL Community BSP has become a complete environment with its own landing page (FSL Community BSP) and a collaborative community around meta-freescale mailing list. I encourage you to register in meta-freescale mailing list. I configured this document to be closed for new comments. In case of any issue or bug, please, send an email to meta-freescale.

File related to the following question: MX53 u-boot Splash Screen support

Test digital zoom with ipu for camera preview.   Board :sarbre-sd (imx6dq) BSP   : android 13.4ga In the above flow, one frame buffer is processed in four steps at camera preview. Add the step to change the frame buffer before step 4 , the added step which  zoom one preview frame.   The figure below shows the crop function of ipu lib, we use this function scale the frame.   Test result: preview zoom levle 0:   preview zoom level max:     When taking pictures with 5M pixels and the zoom is over level 1, the picture size is not 2592x1944 but 2016x1512. The underlying reason for it is that ipu crop function only supports the 2048x2048 maximum output .   Thumbnails of test result :