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Hi All, The i.MX6 Android R13.4-GA.03 patch release is now available on www.freescale.com ·         Files available # Name Description 1 IMX6_R13.4.03_ANDROID_PATCH This patch release is based on the i.MX 6 Android R13.4   release. The purpose of this patch release is correct the PFD workflow in   U-Boot, fix the miscalibration issue for the thermal sensor and corrects   ramp-up time of the internal LDOs
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Hi All, The i.MX6 Android R13.4.1.04 patch release is now available onwww.freescale.com ·         Files available # Name Description 1 IMX6_R13.4.1.04_ANDROID_PATCH This patch release is based on the i.MX 6 Android R13.4.1   release. The purpose of this patch release is correct the PFD workflow in   U-Boot, fix the miscalibration issue for the thermal sensor and corrects   ramp-up time of the internal LDOs
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The i.MX 6 D/Q L3.035_1.0.3 patch release is now available on www.freescale.com ·         Files available # Name Description 1 L3.0.35_1.0.3_TEMP_PFD_PATCH This patch release is based on the i.MX 6Dual/6Quad Linux   12.09.01 release. The purpose of this patch release is update thermal sensor   calibration routine and correct the PFD workflow in U-Boot. More details in   the release notes.
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The i.MX 6 D/Q L3.035_1.1.3 patch release is now available on the www.freescale.com ·         Files available # Name Description 1 L3.0.35_1.1.3_TEMP_PATCH This patch release is based on the i.MX 6Dual/6Quad Linux   L3.0.35_1.1.0 release. The purpose of this patch release is fix the   miscalibration issue for the thermal sensor.
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i.MX6 Quad/6Dual/6SoloLite Errata ERR006282: ROM code uses non-reset PFDs to generate clocks which may lead to random boot failures This PDF contains information about an issue affecting i.MX 6Quad/6Dual/6SoloLite Phase Fractional Dividers (PFDs) and boot. This erratum will be included in the next update of the i.MX6x Silicon Errata documentation but is being provided here for reference until then.
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This is the prototype demo to enable surround view demo on SabreSD.   The attached Files are HW&SW guides and demo video. Updating Notes: Add miniPCIE Surround View_Rev A design file (include schematic and layout) as attachement. Add Gerber file   i.MX6Q Surround view patch https://community.freescale.com/docs/DOC-95143 Original Attachment has been moved to: Gerber-file.zip Original Attachment has been moved to: miniPCIe-Surround-View_Rev-A.zip
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This is the prototype solution to enable second display showing different things on JB4.2.2 SabreSD. Make use of Class Presentation provided by android to be embedded into Status bar. When unlock the screen, the Presentation will show on second display. Now, the solution requires one .mp4 video placed in root sdcard. Of course, you may change it to show anything. The attached Files are a layout xml file, a patch and a recorded video. The layout file should be put into android/frameworks/base/packages/SystemUI/res/layout/ folder. The patch should be applied to frameworks/base.git. The recorded video shows the dual display demo as a reference.
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The i.MX 6 D/Q L3.035_1.0.2 patch release is now available on the www.freescale.com ·         Files available # Name Description 1 L3.0.35_1.0.2_LDO_PATCH This patch release is based on the i.MX 6Dual/6Quad Linux   12.09.01 release. The purpose of this patch release is to manage the LDO and   PMIC ramp-up time correctly.
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The i.MX 6 Android 13.4.1.03 patch release is now available on www.freescale.com IMX6_R13.4103_ANDROID_LDO_PATCH This patch release is based on the i.MX6 Android R13.4.1 release. The purpose of this patch release is to manage the LDO and PMIC ramp-up time correctly.
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These questions and answers are about interrupt generation at a dedicated (configurable) video output port. The i.MX6D manual (Rev. 0) Image Processing Unit (IPU) chapter mentions: Every DI has 10 timing generator counters. The IPU Interrupt Generator has 10 DI0 counters (1...10) and just 2 DI1 counters (3 & 😎 as interrupt sources. The Interrupt Control Register lists 11 DI0 counters (0...10) Q1. Are the DI timing-generator counters linked to the counters in the interrupt controller, or are they different counters? A1. Yes, the DI timing generator counters are linked to the counters in the interrupt controller. Q2. Why are there 11 counters listed in the interrupt controller, but just 10 counters in the timing generator? A2. There is disp_clk_en_pre in the interrupt controller. Thus the 11 counters: 10 timing generator counters and 1 disp clock generator counter. Q3. Is configurable timing feasible for DI0 by using the timing generator counters? A3. Yes, using the 10 internal timing counters you can generate various timing relationships. In addition, you can detect any of the interrupt counters. For example, if you use counter 8, then you can detect the interrupt associated with counter 8. Q4. Explain the impact of the DI1 counter access of only channels 3 and 8. A4. DI1 also has 10 timing generator counters and 1 disp clock generator counter, which you can use to generate desired waveforms. This is similar to DI0. The difference is only 2 of the 10 counters (plus another disp_clk) are connected to the interrupt controller for DI1. Therefore, there is a restriction for detection. If you use counter 7, read out the counter 7 interrupt of DI1 is not possible. However, 2 channels should be sufficient. These interrupts are usually used to indicate a frame start or a frame end. We usually use counter 3 to represent Vsync. So normally we only use counter 3 interrupt. DI1 has only 3 accesses because this covers the anticipated use case and the desire was to restrict register size. The extra counters facilitate flexible DI1 timing generation.
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The SNVS LDO output (VDD_SNVS_CAP) requires an external capacitor. Freescale's updated recommendation is that this should be a single 0.22 uF capacitor. Freescale is working to get documents in alignment. As of Feb 2013, some documents (such as schematics or user guides) show a single 0.22 uF capacitor, others do not.
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Overview The purpose of this doument is to introduce how to enable PCIe WiFi into i.MX6 Android release. Environment Setup Hardware: i.MX6 SABRE-SD board Software: Android Jelly Bean 4.2 Software Configurations The source codes of Intel PCIe WiFi have been integrated for i.MX6 SABRE-SD board into i.MX6 Android release. However it's disabled by default. To enable it for i.MX6 SABRE-SD board, you can do the following: Change BOARD_WLAN_VENDOR to INTEL in device/fsl board configuration files. For example, diff --git a/sabresd_6dq/BoardConfig.mk b/sabresd_6dq/BoardConfig.mk index 9c8a32d..912e752 100755 --- a/sabresd_6dq/BoardConfig.mk +++ b/sabresd_6dq/BoardConfig.mk @@ -11,7 +11,7 @@ TARGET_BOOTLOADER_BOARD_NAME := SABRESD PRODUCT_MODEL := SABRESD-MX6DQ # Wifi -BOARD_WLAN_VENDOR                       := ATHEROS +BOARD_WLAN_VENDOR                       := INTEL # for atheros vendor ifeq ($(BOARD_WLAN_VENDOR),ATHEROS) BOARD_WLAN_DEVICE                       := ar6003 @@ -30,6 +30,7 @@ WIFI_COMPAT_MODULE_ARG                         := "" endif #for intel vendor ifeq ($(BOARD_WLAN_VENDOR),INTEL) +BOARD_WLAN_DEVICE                       := INTEL BOARD_HOSTAPD_PRIVATE_LIB               ?= private_lib_driver_cmd BOARD_WPA_SUPPLICANT_PRIVATE_LIB        ?= private_lib_driver_cmd WPA_SUPPLICANT_VERSION                  := VER_0_8_X After changing BOARD_WLAN_VENDOR as "INTEL", the following files will be compiled for intel WiFi: device/fsl-proprietary/pcie-wifi/ external/wpa_supplicant_8 hardware/imx/wlan/intel/ hardware/libhardware_legacy/wifi/wifi_intel.c Enable PCIe WiFi driver in kernel_imx by running "make menuconfig" command: Select "System Type -> Freescale MXC Implementations -> PCI Express support" as "*" Select "Networking support -> Wireless ->  cfg80211 - wireless configuration API" as "*". Then select "Networking support -> Wireless -> Generic IEEE 802.11 Networking Stack (mac80211)" as "*" Select "Device Drivers ->  Network device support -> Wireless LAN -> Intel Wireless WiFi 4965AGN (iwl4965)" as "*" Then run "make" command to build kernel. The followings are the dependencies files to enable above configuration: Kernel configuration: * -> System Type -> Freescale MXC Implementations Select the PCI Express support. Then config intel WIFI driver: Generic IEEE 802.11 Networking Stack (mac80211) used by WIFI devices Symbol: MAC80211 [=y] Type : tristate Prompt: Generic IEEE 802.11 Networking Stack (mac80211) Defined at net/mac80211/Kconfig:1 Depends on: NET [=y] && WIRELESS [=y] && CFG80211 [=y] Location: -> Networking support (NET [=y]) -> Wireless (WIRELESS [=y]) Intel iwl4965 or iwl6300 card driver Symbol: IWL4965 [=y] Type : tristate Prompt: Intel Wireless WiFi 4965AGN (iwl4965) Defined at drivers/net/wireless/iwlegacy/Kconfig:65 Depends on: NETDEVICES [=y] && WLAN [=y] && PCI [=y] && MAC80211 [=y] Location: -> Device Drivers -> Network device support (NETDEVICES [=y]) Then you can follow up the instructions into Android User guide to build Android image. Known Limitation PCIe low power mode is not supported according to BSP release note. So when building in PCIe, the system suspend/resume should be disabled now.
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Here are two patches to support BT656 and BT1120 output for i.MX6 ipuv3. With this patch, the i.MX6 can support the CVBS output on TV encoder. It is useful for a TV box. "L3.0.35_1.1.0_GA_bt656_output_patch.zip" is the patch for Freescale L3.0.35_1.1.0_GA_iMX6DQ BSP. "r13.4.1_bt656_output_patch.zip" is the patch for Freescale Android R13.4.1 BSP. 1. Features supported:     1) Support BT656(8 bits) and BT1120 (16 bits)interlaced output on display port.     2) Support both RGB and YUV frame buffer for BT656/BT1120 output.     3) Support PAL and NTSC mode.     4) Support on the fly switch between PAL and NTSC mode.     5) Support CVBS output based on adv7391 TV encoder. 2. Hardware link between iMX6 and adv7391 TV encoder chip.     IPU1_DI0_DISP_CLK connected to adv7391 CLKIN pin.     IPU1_DISP0_DAT_23~DISP0_DAT_16 connected to adv7391 P7~P0 pins.     IPU1_DI0_PIN2 connected to adv7391 HSYNC pin. (option)     IPU1_DI0_PIN4 connected to adv7391 VSYNC pin. (option)   - Android R13.4.1 kernel. 3. How to use -- Copy the two patch files to kernel folder.     $ git apply ./0001-Support-BT656-and-BT1120-output-for-iMX6-ipuv3.patch     $ git apply ./0002-Support-adv739x-TV-encoder-for-BT656-output.patch -- Select them in kernel config and build the new kernel image:                     Device Drivers  --->                       Graphics support  --->                           [*]   MXC BT656 and BT1120 output                           [*]   ADV7390/7391 TV Output Encoder -- Uboot parameters for video mode    Output BT656 NTSC data to display port with UVYV frame buffer mode:       "video=mxcfb0:dev=bt656,BT656-NTSC,if=BT656,fbpix=UYVY16"    Output BT656 NTSC data to display port with RGB565 frame buffer mode:       "video=mxcfb0:dev=bt656,BT656-NTSC,if=BT656,fbpix=RGB565"    Output BT656 PAL data to display port with RGB24 frame buffer mode:       "video=mxcfb0:dev=bt656,BT656-PAL,if=BT656,fbpix=RGB24"    Output CVBS NTSC signal on adv7391 with UYVY frame buffer mode:       "video=mxcfb0:dev=adv739x,BT656-NTSC,if=BT656,fbpix=UYVY16"    Output CVBS PAL signal on adv7391 with RGB565 frame buffer mode:       "video=mxcfb0:dev=adv739x,BT656-PAL,if=BT656,fbpix=RGB565" -- Switch between PAL and NTSC    $ echo D:720x480i-60 > /sys/class/graphics/fb0/mode    $ echo D:720x576i-50 > /sys/class/graphics/fb0/mode 4. Note     1) For 8 bits BT656 interface, the default data pins are "DISP0_DAT_23~DISP0_DAT_16", it can also        be any other continued display data pins, for example if "DISP0_DAT_7~DISP0_DAT_0" are used, the        macro "BT656_IF_DI_MSB" in "kernel_imx/drivers/mxc/ipu3/ipu_disp.c" should be changed from "23"        to "7".     2) For 16 bits BT1120 interface, the default data pins are "DISP0_DAT_23~DISP0_DAT_8", it can also        be any other continued display data pins, the macro "BT656_IF_DI_MSB" should be modified if the        hardware pins are changed.     3) When bt656 interface is the second display for each IPU,1-layer-fb (it can be checked with command        "$ cat /sys/class/graphics/fbx/fsl_disp_propperty"), the frame buffer can only be YUV format. In this        case, the IPU DC channel was used for BT656 display, it has no CSC function, so RGB frame buffer was        not supported. 2013-08-09 updated: The new release package "L3.0.35_1.1.0_GA_bt656_output_patch_2013-08-09.zip" had fixed the BT656 dual display issue on iMX6S/DL. Removed the old release package. 2013-09-04 updated: The new release package "r13.4.1_bt656_output_patch_2013-09-04.zip" had fixed the BT656 dual display issue on iMX6S/DL. For default, the dual display was tested with HDMI + CVBS, HDMI is the main display and adv739x CVBS output is the second display. For iMX6DQ which has two IPUs, please assign dual display to two IPUs, for example adv739x is on IPU1 DI0, it is fixed, because hardware pins used for it is fixed. Then we can assign HDMI or LVDS to another IPU (IPU2). For iMX6S/DL which has only one IPU, since adv739x had used IPU1 DI0, another display should be IPU1 DI1. 2013-09-30 updated: Added patch for L3.0.35_4.1.0_GA BSP, the file is "L3.0.35_4.1.0_GA_bt656_output_patch_2013-09-30.zip". 2014-07-21 updated: Added patch for L3.10.17_1.0.0_GA BSP, the file is "L3.10.17_1.0.0_GA_bt656_output_patch_2014-07-21.zip". 2015-01-26 updated: Updated the IPU microcode for 1080i50 and 1080i60 BT1120 output, the parameters "N" for command BMA is a 8 bits parameters, so its max value is 255, but for 1080i50 and 1080i60 output, it needs more blank data in each line, the "N" will be bigger than 255, the updated IPU microcode can fix this limitation. The updated file is "IPU_Microcode_Update_for_BT1120_1080i_20150126.zip". You can update the macro "DC_MCODE_BT656_xxx"  and function _ipu_dc_setup_bt656_interlaced() to the old patch if you used BT1120 mode to support 1080i display. The verified 1080i display mode is: {    /* 1080I60 Interlaced output */   "BT1120-1080I60", 30, 1920, 1080, 13468,   20, 3,   20, 2,   280, 1,   FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,   FB_VMODE_INTERLACED,   FB_MODE_IS_DETAILED,}, {   /* 1080I50 Interlaced output */   "BT1120-1080I50", 25, 1920, 1080, 13468,   20, 3,   20, 2,   720, 1,   FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,   FB_VMODE_INTERLACED,   FB_MODE_IS_DETAILED,}, 2016-01-28 updated: Updated IPU microcode to align with BT656.4 specification for NTSC output. For other BSP version with NTSC format support, please reference to ipu_disp_update.c for the final microcode. File "L3.0.35_4.1.0_GA_bt656_output_patch_20160128.zip"., Details, please reference to the readme.txt file in the package. 2016-06-24 update: Added BT656 and BT1120 progressive mode support. File "L3.0.35_4.1.0_GA_bt656_output_patch_20160624.zip". Details, please reference to the readme.txt file in the package. The patch for 3.14.52 GA1.1.0 BSP will be released in next week. 2016-06-27 update: Add BT656 and BT1120 display patch for 3.14.52 BSP. File "L3.14.52_1.1.0_GA_bt656_output_patch_2016-06-27.zip", details, please reference to the readme.txt in the package. 2017-03-10 update: Fixed a hard coding DC macro issue for progressive mode. Added patch "0008-Fixed-a-hard-coding-DC-macro-issue-for-progressive-m.patch" in L3.0.35_4.1.0_GA_bt656_output_patch_2017-03-10.zip. The code in patch "L3.14.52_1.1.0_GA_bt656_output_patch_2016-06-27" is correct.
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Overview i.MX6Dual/Quad supports using internal LDO or bypass internal LDO. LDO bypass is helpful to save power consumption and reduce thermal under high loading use cases because the power consumption on internal LDO can be saved. The purpose of this document is to introduce how to enable LDO bypass based on i.MX6 R13.4.1 release on i.MX6Dual/Quad SabreSD board. Constraint LDO Bypass solution currently can only be applied to i.MX6Dual/Quad 1GHz. LDO bypass function will force disabled on i.MX6Dual/Quad 1.2GHz, but customer can estimate this function through limit the max ARM frequency to 1GHz by command line 'arm_freq=1000' on i.MX6Dual/Quad 1.2GHz . Hardware Voltage Settings The following table lists the voltage settings in each working CPU frequency and VPU frequency with LDO bypass solution: VPU Frequency ARM Frequency VDDARM_IN (V) VDDSOC_IN (V) 0 to 352MHz 996MHz 1.25 1.25 264-> 352MHz 702MHz 1.15 1.25 0 to 264MHz 792MHz 1.15 1.175 264->352MHz 396MHz 0.95 1.25 <264MHz 396MHz 0.95 1.175 VDDARM_IN and VDDSOC_IN voltage setting should be within the voltage range, considering the ripple: VDDARM_IN - ripple>VDDARM_INmin VDDARM_IN + ripple<VDDARM_Inmax For the Min/Max value, refer to the i.MX6Dual/Quad data sheet. The above list is based on SabreSD PFuse-100. Software Changes Please apply the patches into Android-13.4.1-LDO_BYPASS-pathes.tar.gz.gz based on R13.4.1. The change lists: uboot-imx: move LDO bypass code and one PFUZE1.0 workaround code to kernel. Remove CONFIG_MX6_INTER_LDO_BYPASS in u-boot. kernel: A set of patches are used to support LDO bypass enable/disable by command option. How to Enable/Disable LDO Bypass After applying for above patches, you can add command option into boot command line to enable or disable LDO: Command option “ldo_active=off”: Enable LDO bypass mode Command option “ldo_active=on”: Enable LDO active
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Attached is the Kernel image needed to construct the Linux Image i.MX 6Dual/6Quad Power Consumption Measurement Linux Image
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Attached is the Kernel needed to construct the following image: i.MX 6Dual/6Quad Power Consumption Measurement Linux Image
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Attached is the U-boot binary needed to construct the following image: i.MX 6Dual/6Quad Power Consumption Measurement Linux Image
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Overview The purpose of this document is to provide the patches to fix display mess issue in TextView based on MX6 Android R13.4-GA and R13.4.1 ICS release. Please note these patches are only validated basically for dedicated issues. If you find any side effect with these patches, please add the comments into this document. Issue Description Software: R13.4-GA or R13.4.1 Android releases Hardware: i.MX6Dual/Quad SabreSD board or i.MX6DualLite SabreSD board. Test steps: Install testviewtest.apk Run this APK and key in the text, you will see the text display mess after key in more texts. You can also get the issue descriptions from https://community.freescale.com/thread/303194 Patches You can get the patches from attached textview_fix.zip. For R13.4-GA, please apply the following patches: kernel_imx, unzip Kernel/r13.4-ga/kernel-patch-r13.4-ga-gpu4.6.9p10.tar.gz and apply the patches. device/fsl-proprietary/gpu-viv: unzip gpu_lib/gpu-viv-lib-4.6.9p10-font-libGAL-crash-fix.tar.gz and replace lib folder. For R13.4.1, please apply the following patches: kernel_imx, Apply the patch Kernel/r13.4.1/0001-upgrade-gpu-4.6.9p10-kernel-driver_r13.4.1.patc device/fsl-proprietary/gpu-viv: unzip gpu_lib/gpu-viv-lib-4.6.9p10-font-libGAL-crash-fix.tar.gz and replace lib folder.
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Starting from $52, the VAR-SOM-MX6 sets the bar for unparalleled design flexibility. The VAR-SOM-MX6 ensures scalable and simplified development, while also extending the product lifecycle. Thanks to four CPU core assembly options, customers can apply a single System on Module in a broad range of applications to achieve short time-to-market for their current innovations, while still accommodating potential R&D directions and marketing opportunities.     VAR-SOM-MX6 CPU: Freescale iMX6 Key features include: Freescale i.MX6 1.2GHz Quad / Dual / Single core Cortex-A9       2GB DDR3, 1GB SLC NAND Flash       Full HD 1080p video encoding/decoding capability       Vivante GPU providing 2D/3D acceleration       Simultaneous multiple display support       Gigabit Ethernet       TI WiLink™ 6.0 single-chip connectivity solution (Wi-Fi, Bluetooth®)       PCI-Express 2.0, S-ATA 3.0       Camera interface       USB 2.0: Host, OTG       Audio In/Out       Dual CAN Bus This versatile solution's -40 to 85°C temperature range and Dual CAN support is ideal for industrial applications, while 1080p video and graphics accelerations make it equally suitable for intensive multimedia applications. The impressive scalability of the VAR-SOM-MX6 satisfies the needs of the most demanding future application requirements whether faster processing power, enhanced algorithms or improved graphics and video performance to name just a few. The VAR-SOM-MX6 is an all-round solution with broad connectivity and sophisticated video and acceleration graphic capabilities, delivering a range of middle to high end assembly options all from the same product. For more details, please see VAR-SOM-MX6 CPU: Freescale iMX6
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The attached patch applies to iMX6_Platform_SDK for i.MX6 Dual and Quad and brings 2 additional SDMA memory to memory scripts: fixed destination address, increasing source address fixed source address, increasing destination address. With this patch, the new scripts are also integrated in the SDMA Test menu of the Platform SDK. I created these scripts starting from the ROM script ap_to_ap. In order to dump the content of the SDMA ROM, I used mxc_printSDMAcontext function which is also included in the attached patch and can be invoked when needed.
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